Publications

Journals

[J79] E. Glukhov, T. Li, V. Gupta, and P. Gupta, “Learned approximate computing: algorithm hardware co-optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
[Bibtex]

@article{J79,
author = {Egor Glukhov and Tianmu Li and Vaibhav Gupta and Puneet Gupta},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
title = {Learned Approximate Computing: Algorithm Hardware Co-optimization},
year = {2024}
}


[J81] Z. Chen, H. Hassan A., R. Ramadhan, Y. Li, C. K. Yang, S. Pamarti, and P. Gupta, “A comparative analysis of low temperature and room temperature circuit operation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024.
[Bibtex]

@article{J81,
author = {Chen, Z. and Hassan, A., H. and Ramadhan, R. and Li, Y. and Yang, C. K. and Pamarti, S. and Gupta, P.},
doi = {10.1109/TVLSI.2024.3508673},
journal = {{{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}},
title = {A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation},
year = {2024}
}


[J78] I. Alam and P. Gupta, “Achieving dram-like pcm by trading off capacity for latency,” IEEE Transactions on Computers, 2024.
[Bibtex]

@article{J78,
author = {Irina Alam and Puneet Gupta},
journal = {{IEEE Transactions on Computers}},
title = {Achieving DRAM-like PCM By Trading Off Capacity For Latency},
year = {2024}
}


[J80] S. Pal, A. Mallik, and P. Gupta, “System technology co-optimization for advanced integration,” Nature Reviews Electrical Engineering, 2024.
[Bibtex]

@article{J80,
author = {Pal, S. and Mallik, A. and Gupta, P},
doi = {10.1038/s44287-024-00078-x},
journal = {{Nature Reviews Electrical Engineering}},
title = {System technology co-optimization for advanced integration},
year = {2024}
}


[J74] T. Li, W. Romaszkan, S. Pamarti, and P. Gupta, “REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.
[Bibtex]

@article{J74,
author = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
month = {June},
publisher = {{IEEE}},
title = {{REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration}},
year = {2023}
}


[J73] V. K. Jacob, J. Yang, H. He, P. Gupta, K. Wang, and S. Pamarti, “A Nonvolatile Compute-In-Memory Macro Using Voltage-Controlled MRAM and In-Situ Magnetic-to-Digital Converter,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2023.
[Bibtex]

@article{J73,
author = {Jacob, Vinod Kurian and Yang, Jiyue and He, Haoran and Gupta, Puneet and Wang, Kang and Pamarti, Sudhakar},
doi = {10.1109/JXCDC.2023.3258431},
journal = {{IEEE Journal on Exploratory Solid-State Computational Devices and Circuits}},
month = {March},
paperurl = {https://ieeexplore.ieee.org/document/10075423},
publisher = {{IEEE}},
title = {{A Nonvolatile Compute-In-Memory Macro Using Voltage-Controlled MRAM and In-Situ Magnetic-to-Digital Converter}},
year = {2023}
}


[J77] N. Ardalani, S. Pal, and P. Gupta, “Deepflow: a cross-stack pathfinding framework for distributed ai systems,” ACM Transactions on Design Automation of Electronic Systems, 2023.
[Bibtex]

@article{J77,
author = {Newsha Ardalani and Saptadeep Pal and Puneet Gupta},
doi = {10.1145/3635867},
journal = {{ACM Transactions on Design Automation of Electronic Systems}},
title = {DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems},
year = {2023}
}


[J76] A. Lee, I. Alam, J. Yang, D. Wu, S. Pamarti, P. Gupta, and K. L. Wang, “Low-energy shared-current write schemes for voltage-controlled spin-orbit-torque memory,” IEEE Transactions on Electron Devices, vol. 70, iss. 2, pp. 478-484, 2023.
[Bibtex]

@article{J76,
author = {Lee, Albert and Alam, Irina and Yang, Jiyue and Wu, Di and Pamarti, Sudhakar and Gupta, Puneet and Wang, Kang L.},
doi = {10.1109/TED.2022.3228831},
journal = {{IEEE Transactions on Electron Devices}},
number = {2},
pages = {478-484},
title = {Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory},
volume = {70},
year = {2023}
}


[J72] W. Romaszkan, T. Li, and P. Gupta, “SASCHA – Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,” , p. 12, 2022. – Best paper nomination
[Bibtex]

@article{J72,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
doi = {},
keywords = {mledge},
month = {October},
note = {Best paper nomination},
pages = {12},
title = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},
year = {2022}
}


[J71] Z. Hu, S. Li, R. Schwartz, M. Solyanik-Gorgone, M. Miscuglio, P. Gupta, and V. Sorger, “High-Throughput Multichannel Parallelized Diffraction Convolutional Neural Network Accelerator,” Laser & Photonics Reviews, 2022.
[Bibtex]

@article{J71,
author = {Hu, Zibo and Li, Shurui and Schwartz, Russel and Solyanik-Gorgone, Maria and Miscuglio, Mario and Gupta, Puneet and Sorger, Volker},
journal = {{Laser \& Photonics Reviews}},
month = {October},
publisher = {{Wiley}},
title = {{High-Throughput Multichannel Parallelized Diffraction Convolutional Neural Network Accelerator}},
year = {2022}
}


[J70] W. Romaszkan, T. Li, R. Garg, J. Yang, S. Pamarti, and P. Gupta, ” A 4.4-75 TOPS/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator,” IEEE Solid State Circuits Letters, 2022.
[Bibtex]

@article{J70,
author = {Romaszkan, Wojciech and Li, Tianmu and Garg, Rahul and Yang, Jiyue and Pamarti, Sudhakar and Gupta, Puneet},
journal = {{IEEE Solid State Circuits Letters}},
keywords = {mledge},
month = {August},
publisher = {{IEEE}},
title = {{ A 4.4-75 TOPS/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator}},
year = {2022}
}


[J69] I. Alam, T. Li, S. Brock, and P. Gupta, “DRDebug: Automated Design Rule Debugging,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022.
[Bibtex]

@article{J69,
author = {Alam, Irina and Li, Tianmu and Brock, Sean and Gupta, Puneet},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
publisher = {{IEEE}},
title = {{DRDebug: Automated Design Rule Debugging}},
year = {2022}
}


[J65] E. Chu, Y. Luo, and P. Gupta, “Design Impacts of Back-End-of-Line Line Edge Roughness,” IEEE Transactions on Semiconductor Manufacturing, 2020.
[Bibtex]

@article{J65,
author = {Chu, Eugene and Luo, Yandong and Gupta, Puneet},
doi = {https://ieeexplore.ieee.org/document/8902181},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
month = {February},
publisher = {{IEEE}},
title = {{Design Impacts of Back-End-of-Line Line Edge Roughness}},
year = {2020}
}


[J64] W. Wang, Y. Wu, and P. Gupta, “Reverse Engineering for 2.5D Split Manufactured ICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
[Bibtex]

@article{J64,
author = {Wang, Wei-Che and Wu, Yizhang and Gupta, Puneet},
doi = {https://doi.org/10.1109/TCAD.2019.2957359},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
publisher = {{IEEE}},
title = {{Reverse Engineering for 2.5D Split Manufactured ICs}},
year = {2020}
}


[J66] S. Pal, D. Petrisko, R. Kumar, and P. Gupta, “Design Space Exploration for Chiplet Assembly Based Processors,” IEEE Transactions on Very Large Scale Integration Systems, 2020.
[Bibtex]

@article{J66,
author = {Pal, Saptadeep and Petrisko, Daniel and Kumar, Rakesh and Gupta, Puneet},
doi = {https://ieeexplore.ieee.org/document/8998304},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {{2.5-D integration, chiplet assembly, micro-architectural design space exploration (DSE), multichiplet optimization, wsi}},
publisher = {{IEEE}},
title = {{Design Space Exploration for Chiplet Assembly Based Processors}},
year = {2020}
}


[J67] M. Miscuglio, Z. Hu, S. Li, J. George, R. Capanna, P. Bardet, P. Gupta, and V. Sorger, “Massively parallel amplitude-only Fourier neural network,” Optica, 2020.
[Bibtex]

@article{J67,
author = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and George, Jonathan and Capanna, Roberto and Bardet, Philippe and Gupta, Puneet and Sorger, Volker},
journal = {{Optica}},
publisher = {{OSA}},
title = {{Massively parallel amplitude-only Fourier neural network}},
year = {2020}
}


[J63] W. Romaszkan, T. Li, and P. Gupta, “3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning,” ACM Transactions on Embedded Computing Systems (TECS), 2019.
[Bibtex]

@article{J63,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
journal = {{ACM Transactions on Embedded Computing Systems (TECS)}},
keywords = {mledge, 3pxnet},
month = {November},
publisher = {ACM},
title = {{3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning}},
year = {2019}
}


[J62] C. Schoeny, F. Sala, M. Gottscho, I. Alam, P. Gupta, and L. Dolecek, “Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories,” IEEE Transactions on Information Theory, 2019.
[Bibtex]

@article{J62,
author = {Schoeny, Clayton and Sala, Frederic and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},
journal = {{IEEE Transactions on Information Theory}},
keywords = {memres},
month = {October},
title = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},
year = {2019}
}


[J61] S. Pal, E. Ebrahimi, A. Zulfiqar, Y. Fu, V. Zhang, S. Migacz, D. Nellans, and P. Gupta, “Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training,” IEEE Micro, 2019.
[Bibtex]

@article{J61,
author = {Pal, Saptadeep and Ebrahimi, Eiman and Zulfiqar, Arslan and Fu, Yaosheng and Zhang, Victor and Migacz, Szymon and Nellans, David and Gupta, Puneet},
journal = {{{IEEE Micro}}},
month = {September},
publisher = {IEEE},
title = {{Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training}},
year = {2019}
}


[J60] W. Wang, Y. Yona, Y. Wu, S. Diggavi, and P. Gupta, “SLATE: A Secure Lightweight Entity Authentication Hardware Primitive,” IEEE Transactions on Information Forensics and Security, 2019.
[Bibtex]

@article{J60,
author = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Diggavi, Suhas and Gupta, Puneet},
journal = {{{IEEE Transactions on Information Forensics and Security}}},
month = {May},
publisher = {IEEE},
title = {{SLATE: A Secure Lightweight Entity Authentication Hardware Primitive}},
year = {2019}
}


[J68] P. Gupta and S. S. Iyer, “Goodbye Motherboard, Hello Silicon Interconnect Fabric,” IEEE Spectrum, 2019.
[Bibtex]

@article{J68,
author = {Gupta, Puneet and Iyer, S.S.},
journal = {{IEEE Spectrum}},
publisher = {{IEEE}},
title = {{Goodbye Motherboard, Hello Silicon Interconnect Fabric}},
year = {2019}
}


[J57] W. Wang, C. Zhao, and P. Gupta, “Assessing Layout Density Benefits of Vertical Channel Devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.
[Bibtex]

@article{J57,
author = {Wang, Wei-Che and Zhao, Charles and Gupta, Puneet},
issue = {},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
month = {},
title = {{Assessing Layout Density Benefits of Vertical Channel Devices}},
volume = {},
year = {2018}
}


[J58] H. Lee, A. Lee, S. Wang, F. Ebrahimi, P. Gupta, P. K. Amiri, and K. L. Wang, “Analysis and Compact Modeling of Magnetic Tunner Junctions Using Voltage-Controlled Magnetic Anisotropy,” IEEE Transactions on Magnetics, 2018.
[Bibtex]

@article{J58,
author = {H. Lee and A. Lee and S. Wang and F. Ebrahimi and P. Gupta and P.K. Amiri and K.L. Wang},
journal = {{IEEE Transactions on Magnetics}},
title = {{Analysis and Compact Modeling of Magnetic Tunner Junctions Using Voltage-Controlled Magnetic Anisotropy}},
year = {2018}
}


[J59] S. Wang, H. Lee, C. Grezes, K. P. Amiri, K. L. Wang, and P. Gupta, “Adaptive MRAM Write and Read with MTJ Variation Monitor,” Transactions on Emerging Topics in Computing, 2018.
[Bibtex]

@article{J59,
author = {Wang, Shaodi and Lee, Hochul and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Gupta, Puneet},
journal = {{Transactions on Emerging Topics in Computing}},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J59_paper.pdf},
title = {{Adaptive MRAM Write and Read with MTJ Variation Monitor}},
year = {2018}
}


[J56] W. Wang, Y. Yona, S. Diggavi, and P. Gupta, “Design and Analysis of Stability-Guaranteed PUFs,” IEEE Transactions on Information Forensics and Security (TIFS), 2017.
[Bibtex]

@article{J56,
author = {Wang, Wei-Che and Yona, Yair and Diggavi, Suhas and Gupta, Puneet},
journal = {{IEEE Transactions on Information Forensics and Security (TIFS)}},
month = {November},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J56_paper.pdf},
title = {{Design and Analysis of Stability-Guaranteed PUFs}},
volume = {},
year = {2017}
}


[J54] M. Gottscho, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, “Low-Cost Memory Fault Tolerance for IoT Devices,” ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS), 2017.
[Bibtex]

@article{J54,
author = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
journal = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},
keywords = {memres},
month = {October},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J54_paper.pdf},
title = {{Low-Cost Memory Fault Tolerance for IoT Devices}},
volume = {},
year = {2017}
}


[J53] L. Lai and P. Gupta, “System-level Dynamic Variation Margining in Presence of Monitoring and Actuation,” IEEE Embedded System Letters, 2017.
[Bibtex]

@article{J53,
author = {Lai, Liangzhen and Gupta, Puneet},
journal = {{IEEE Embedded System Letters}},
keywords = {Monitoring, Temperature measurement, Temperature sensors, Actuators, Power system dynamics, Aging, Clocks},
month = {June},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J53_paper.pdf},
title = {{System-level Dynamic Variation Margining in Presence of Monitoring and Actuation}},
volume = {},
year = {2017}
}


[J51] H. Lee, A. Lee, S. Wang, F. Ebrahimi, P. Gupta, K. P. Amiri, and K. L. Wang, “A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory,” IEEE Transactions on Very Large Scale Integration Systems, 2017.
[Bibtex]

@article{J51,
author = {Lee, Hochul and Lee, Albert and Wang, Shaodi and Ebrahimi, Farbod and Gupta, Puneet and Amiri, P. Khalili and Wang, Kang L.},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {},
month = {March},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J51_paper.pdf},
title = {{A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory}},
volume = {},
year = {2017}
}


[J52] Y. Badr and P. Gupta, “Technology path-finding framework for directed-self assembly for via layers,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2017.
[Bibtex]

@article{J52,
author = {Badr, Yasmine and Gupta, Puneet},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J52_paper.pdf},
title = {Technology path-finding framework for directed-self assembly for via layers},
year = {2017}
}


[J50] C. Grezes, H. Lee, A. Lee, S. Wang, F. Ebrahimi, X. Li, K. Wong, Q. Hu, P. Gupta, K. P. Amiri, and K. L. Wang, “Write Error Rate and Read Disturbance in Electric-Field-Controlled MRAM,” IEEE Magnetic Letters, vol. 8, 2017.
[Bibtex]

@article{J50,
author = {Grezes, Cecile and Lee, Hochul and Lee, Albert and Wang, Shaodi and Ebrahimi, Farbod and Li, Xiang and Wong, Kin and Hu, Qi and Gupta, Puneet and Amiri, P. Khalili and Wang, Kang L.},
journal = {{IEEE Magnetic Letters}},
keywords = {},
month = {},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J50_paper.pdf},
title = {{Write Error Rate and Read Disturbance in Electric-Field-Controlled MRAM}},
volume = {8},
year = {2017}
}


[J49] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operation,” IEEE Transactions on Electronic Devices, vol. 64, 2017.
[Bibtex]

@article{J49,
author = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
issue = {1},
journal = {{IEEE Transactions on Electronic Devices}},
keywords = {Negative differential resistance, Magnetic tunnel junction, Magnetic random access memory, MRAM, read, write termination},
month = {1},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J49_paper.pdf},
title = {{Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operation}},
volume = {64},
year = {2017}
}


[J55] S. Wang, A. Pan, C. Grezes, P. Amiri, C. O. Chui, and P. Gupta, “Leveraging NMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory,” IEEE Transactions on Electronic Devices, vol. PP, 2017.
[Bibtex]

@article{J55,
author = {Wang, Shaodi and Pan, Andrew and Grezes, Cecile and Amiri, Pedram and Chui, Chi On and Gupta, Puneet},
journal = {{IEEE Transactions on Electronic Devices}},
keywords = {Negative differential resistance, Magnetic tunnel junction, Magnetic random access memory, MRAM, read, write termination},
month = {8},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J55_paper.pdf},
title = {{Leveraging NMOS Negative Differential Resistance
for Low Power, High Reliability Magnetic Memory}},
volume = {PP},
year = {2017}
}


[J47] S. Wang, H. Hu, H. Zheng, and P. Gupta, “MEMRES: A Fast Memory System Reliability Simulator,” IEEE Transactions on Reliability, vol. 65, pp. 1783-1797, 2016.
[Bibtex]

@article{J47,
author = { Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},
issue = {4},
journal = {{IEEE Transactions on Reliability}},
keywords = {Memory fault, memory reliability, simulator, reliability management, memory page retirement, sparing, memory mirroring, STT-RAM, MRAM, write error, retention error},
month = {October},
pages = {1783-1797},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J47_paper.pdf},
title = {{MEMRES}: {A} {F}ast {M}emory {S}ystem {R}eliability {S}imulator},
volume = {65},
year = {2016}
}


[J48] Y. Badr, A. Torres, and P. Gupta, “Mask Assignment and Dsa Grouping for DSA-MP Hybrid Lithography for sub-7nm Contact/Via Holes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.
[Bibtex]

@article{J48,
author = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},
category = {J48},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J48_paper.pdf},
title = {{M}ask {A}ssignment and {D}SA {G}rouping for {DSA-MP} {H}ybrid {L}ithography for sub-7nm {C}ontact/{V}ia {H}oles},
year = {2016}
}


[J46] M. Gottscho, M. Shoaib, S. Govindan, B. Sharma, D. Wang, and P. Gupta, “Measuring the Impact of Memory Errors on Application Performance,” IEEE Computer Architecture Letters (CAL), 2016.
[Bibtex]

@article{J46,
author = {Gottscho, Mark and Shoaib, Mohammed and Govindan, Sriram and Sharma, Bikash and Wang, Di and Gupta, Puneet},
issue = {},
journal = {{IEEE Computer Architecture Letters (CAL)}},
keywords = {memres},
month = {August},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J46_paper.pdf},
title = {{Measuring the Impact of Memory Errors on Application Performance}},
volume = {},
year = {2016}
}


[J42] S. Wang, H. Lee, F. Ebrahimi, K. P. Amiri, K. L. Wang, and P. Gupta, “Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2016.
[Bibtex]

@article{J42,
author = {Wang, Shaodi and Lee, Hochul and Ebrahimi, Farbod and Amiri, P. Khalili and Wang, Kang L. and Gupta, Puneet},
journal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},
keywords = {STT-RAM, MeRAM, MTJ, process variation, write error rate, MTJ Model},
month = {June},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J42_paper.pdf},
title = {{C}omparative {E}valuation of {S}pin-{T}ransfer-{T}orque and {M}agnetoelectric {R}andom {A}ccess {M}emory},
volume = {},
year = {2016}
}


[J45] L. Zhu, Y. Badr, S. Wang, S. Iyer, and P. Gupta, “Assessing Benefits of a Buried Interconnect Layer in Digital Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.
[Bibtex]

@article{J45,
author = {Zhu, Liheng and Badr, Yasmine and Wang, Shaodi and Iyer, Subramanian and Gupta, Puneet},
category = {J45},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J45_paper.pdf},
title = {Assessing {B}enefits of a {B}uried {I}nterconnect {L}ayer in {D}igital {D}esigns},
year = {2016}
}


[J40] G. Leung, S. Wang, A. Pan, P. Gupta, and C. O. Chui, “An Evaluation Framework for Nanotransfer Printing Based Feature-Level Heterogeneous Integration in VLSI Circuits,” IEEE Transactions on Very Large Scale Integration Systems, 2016.
[Bibtex]

@article{J40,
author = {Leung, Greg and Wang, Shaodi and Pan, Andrew and Gupta, Puneet and Chui, Chi On},
issue = {},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J40_paper.pdf},
title = {{A}n {E}valuation {F}ramework for {N}anotransfer {P}rinting {B}ased {F}eature-{L}evel {H}eterogeneous {I}ntegration in {VLSI} {C}ircuits},
volume = {},
year = {2016}
}


[J41] W. Wang and P. Gupta, “Efficient Layout Generation and Design Evaluation of Vertical Channel Devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.
[Bibtex]

@article{J41,
author = {Wang, Wei-Che and Gupta, Puneet},
issue = {},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J41_paper.pdf},
title = {{Efficient Layout Generation and Design Evaluation of Vertical Channel Devices}},
volume = {},
year = {2016}
}


[J44] T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, and A. B. Kahng, “Benchmarking of Mask Fracturing Heuristics,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016
[Bibtex]

@inproceedings{J44,
author = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. },
booktitle = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
category = {J44},
keywords = {dats},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J44_paper.pdf},
title = {Benchmarking of {M}ask {F}racturing {H}euristics},
year = {2016}
}


[J43] H. Lee, C. Grezes, S. Wang, K. P. Amiri, P. Gupta, and K. L. Wang, “A Source Line Sensing (SLS) Scheme in Magnetoelectric Random Access Memory (MeRAM) for Reducing Read Disturbance and Improving Sensing Margin,” IEEE Magnetics Letters, vol. 7, 2016.
[Bibtex]

@article{J43,
author = { Lee, Hochul and Grezes, Cecile and Wang, Shaodi and Amiri, P. Khalili and Gupta, Puneet and Wang, Kang L.},
journal = {{IEEE Magnetics Letters}},
keywords = {MeRAM, MTJ, read disturbance, source line sensing, sensing scheme},
month = {},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J43_paper.pdf},
title = {A {S}ource {L}ine {S}ensing ({SLS}) {S}cheme in {M}agnetoelectric {R}andom {A}ccess {M}emory ({MeRAM}) for {R}educing {R}ead {D}isturbance and {I}mproving {S}ensing {M}argin},
volume = {7},
year = {2016}
}


[J39] M. Gottscho, A. BanaiyanMofrad, N. Dutt, A. Nicolau, and P. Gupta, “DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era,” ACM Transactions on Architecture and Code Optimization (TACO), vol. 12, 2015.
[Bibtex]

@article{J39,
author = {Gottscho, Mark and BanaiyanMofrad, Abbas and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},
issue = {3},
journal = {{ACM Transactions on Architecture and Code Optimization (TACO)}},
month = {August},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J39_paper.pdf},
title = {{DPCS}: {D}ynamic {P}ower/{C}apacity {S}caling for {SRAM} {C}aches in the {N}anoscale {E}ra},
volume = {12},
year = {2015}
}


[J38] L. Wanner, L. Lai, A. Rahimi, M. Gottscho, P. Mercati, C. Huang, F. Sala, Y. Agarwal, L. Dolecek, N. Dutt, P. Gupta, R. Gupta, R. Jhala, R. Kumar, S. Lerner, M. Subhasish, A. Nicolau, T. S. Rosing, M. B. Srivastava, S. Swanson, D. Sylvester, and Y. Zhou, “NSF Expedition on Variability-Aware Software: Recent Results and Contributions,” De Gruyter Information Technology (it), vol. 57, pp. 181-198, 2015.
[Bibtex]

@article{J38,
author = {Wanner, Lucas and Lai, Liangzhen and Rahimi, Abbas and Gottscho, Mark and Mercati, Pietro and Huang, Chu-Hsiang and Sala, Frederic and Agarwal, Yuvraj and Dolecek, Lara and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh and Jhala, Ranjit and Kumar, Rakesh and Lerner, Sorin and Mitra Subhasish and Nicolau, Alexandru and Rosing, Tajana Simunic and Srivastava, Mani B. and Swanson, Steve and Sylvester, Dennis and Zhou, Yuanyuan},
issue = {3},
journal = {{De Gruyter Information Technology (it)}},
month = {June},
pages = {181-198},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J38_paper.pdf},
title = {{NSF} {E}xpedition on {V}ariability-{A}ware {S}oftware: {R}ecent {R}esults and {C}ontributions},
volume = {57},
year = {2015}
}


[J33] M. Gottscho, L. A. D. Bathen, N. Dutt, A. Nicolau, and P. Gupta, “ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings,” IEEE Transactions on Computers, vol. 64, p. 1483–1496, 2015.
[Bibtex]

@article{J33,
author = {Gottscho, Mark and Bathen, Luis A. D. and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},
issue = {5},
journal = {{IEEE Transactions on Computers}},
keywords = {DRAM, variability, energy-aware systems, main memory, allocation/deallocation strategies, operating systems},
month = {May},
pages = {1483--1496},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J33_paper.pdf},
title = {{V}i{P}{Z}on{E}: {H}ardware {P}ower {V}ariability-{A}ware {V}irtual {M}emory {M}anagement for {E}nergy {S}avings},
volume = {64},
year = {2015}
}


[J37] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “Proceed: a pareto optimization-based circuit-level evaluator for emerging devices,” IEEE Transactions on Very Large Scale Integration Systems, 2015.
[Bibtex]

@article{J37,
author = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {Emerging device, evaluator, proceed },
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J37_paper.pdf},
title = {PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices},
year = {2015}
}


[J34] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, iss. 8, pp. 1168-1179, 2014.
[Bibtex]

@article{J34,
author = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {hsi},
month = {Aug},
number = {8},
pages = {1168-1179},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J34_paper.pdf},
title = {{S}lack{P}robe: {A} {F}lexible and {E}fficient {I}n {S}itu {T}iming {S}lack {M}onitoring {M}ethodology},
volume = {33},
year = {2014}
}


[J32] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “BTI-Gater: An Aging-Resilient Clock Gating Methodology,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, iss. 2, pp. 180-189, 2014.
[Bibtex]

@article{J32,
author = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},
journal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},
keywords = {hsi, NBTI},
month = {June},
number = {2},
pages = {180-189},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J32_paper.pdf},
title = {{B}{T}{I}-{G}ater: {A}n {A}ging-{R}esilient {C}lock {G}ating {M}ethodology},
volume = {4},
year = {2014}
}


[J36] Y. Badr, K. Ma, and P. Gupta, “Layout pattern-driven design rule evaluation,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2014.
[Bibtex]

@article{J36,
author = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J36_paper.pdf},
title = {Layout Pattern-driven Design Rule Evaluation},
year = {2014}
}


[J35] A. A. Kagalwalla and P. Gupta, “Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), vol. 13, iss. 4, p. 43005, 2014.
[Bibtex]

@article{J35,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
doi = {10.1117/1.JMM.13.4.043005},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
number = {4},
pages = {043005},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J35_paper.pdf},
title = {Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects},
volume = {13},
year = {2014}
}


[J30] R. S. Ghaida, M. Gupta, and P. Gupta, “Framework for exploring the interaction between design rules and overlay control,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), vol. 12, iss. 3, 2013.
[Bibtex]

@article{J30,
author = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {variability},
month = {August },
number = {3},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J30_paper.pdf},
title = {Framework for exploring the interaction between design rules and overlay control},
volume = {12},
year = {2013}
}


[J29] S. Wang, G. Leung, A. Pan, C. O. Chui, and P. Gupta, “Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless Finfet Technologies,” IEEE Transactions on Electronic Devices, vol. 60, iss. 7, pp. 2186-2193, 2013.
[Bibtex]

@article{J29,
author = {Wang, Shaodi and Leung, Greg and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
journal = {{IEEE Transactions on Electronic Devices}},
keywords = {variability},
month = {July },
number = {7},
pages = {2186 - 2193},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J29_paper.pdf},
title = {{E}valuation of {D}igital {C}ircuit-{L}evel {V}ariability in {I}nversion-{M}ode and {J}unctionless {F}inFET {T}echnologies},
volume = {60},
year = {2013}
}


[J31] T. Chan, P. Gupta, A. B. Kahng, and L. Lai, “Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors,” IEEE Transactions on Very Large Scale Integration Systems, 2013.
[Bibtex]

@article{J31,
author = {Chan, Tuck-Boon and Gupta, Puneet and Kahng, A. B. and Lai, Liangzhen},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi, DDRO},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J31_paper.pdf},
title = {{S}ynthesis and {A}nalysis of {D}esign-{D}ependent {R}ing {O}scillator ({D}{D}{R}{O}) {P}erformance {M}onitors},
year = {2013}
}


[J28] A. A. Kagalwalla and P. Gupta, “Design-Aware Defect-Avoidance Floorplanning of EUV Masks,” IEEE Transactions on Semiconductor Manufacturing, vol. 26, 2013.
[Bibtex]

@article{J28,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
issue = {1},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J28_paper.pdf},
title = {{Design-Aware Defect-Avoidance Floorplanning of EUV Masks}},
volume = {26},
year = {2013}
}


[J22] G. Leung, L. Lai, P. Gupta, and C. O. Chui, “Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32nm Finfet Technologies,” IEEE Transactions on Electronic Devices, vol. 59, iss. 8, pp. 2057-2063, 2012.
[Bibtex]

@article{J22,
author = {Leung, Greg and Lai, Liangzhen and Gupta, Puneet and Chui, Chi On},
journal = {{IEEE Transactions on Electronic Devices}},
keywords = {variability},
month = {aug. },
number = {8},
pages = {2057 -2063},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J22_paper.pdf},
title = {{D}evice- and {C}ircuit-{L}evel {V}ariability {C}aused
by {L}ine {E}dge {R}oughness for {S}ub-32nm {F}inFET {T}echnologies},
volume = {59},
year = {2012}
}


[J18] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-Aware Mask Inspection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
[Bibtex]

@article{J18,
author = {Kagalwalla, Abde Ali and Puneet Gupta and Progler, Chris and McDonald, Steve},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J18_paper.pdf},
title = {Design-{A}ware {M}ask {I}nspection},
year = {2012}
}


[J19] R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
[Bibtex]

@article{J19,
author = {Ghaida, R. S. and Gupta, P.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {design rules, technology assessment, dre, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J19_paper.pdf},
title = {{DRE}: a {F}ramework for {E}arly {C}o-{E}valuation of {D}esign {R}ules, {T}echnology {C}hoices, and {L}ayout {M}ethodologies},
year = {2012}
}


[J20] M. Gottscho, A. A. Kagalwalla, and P. Gupta, “Power Variability in Contemporary DRAMs,” IEEE Embedded Systems Letters, vol. 4, p. 37–40, 2012.
[Bibtex]

@article{J20,
author = {Gottscho, Mark and Kagalwalla, Abde Ali and Gupta, Puneet},
issue = {2},
journal = {{IEEE Embedded Systems Letters}},
keywords = {DRAM, DDR3, power, variability, hsi},
pages = {37--40},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J20_paper.pdf},
title = {{P}ower {V}ariability in {C}ontemporary {DRAM}s},
volume = {4},
year = {2012}
}


[J21] T. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,” IEEE Transactions on Semiconductor Manufacturing, 2012.
[Bibtex]

@article{J21,
author = {Chan, Tuck-Boon and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {Process monitoring, wafer pruning, variability},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J21_paper.pdf},
title = {{D}esign {D}ependent {P}rocess {M}onitoring for {W}afer {M}anufacturing and {T}est {C}ost {R}eduction},
year = {2012}
}


[J25] S. Mok, J. Lee, and P. Gupta, “Discrete sizing for leakage power optimization in physical design: a comparative study,” ACM Transactions on Design Automation of Electronic Systems, 2012.
[Bibtex]

@article{J25,
author = {Santiago Mok and John Lee and Puneet Gupta},
journal = {{ACM Transactions on Design Automation of Electronic Systems}},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J25_paper.pdf},
title = {Discrete Sizing for Leakage Power Optimization in Physical Design: A Comparative Study},
year = {2012}
}


[J23] L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “Hardware Variability-Aware Duty Cycling for Embedded Sensors,” IEEE Transactions on Very Large Scale Integration Systems, 2012.
[Bibtex]

@article{J23,
author = {Lucas Wanner and Charwak Apte and Rahul Balani and Puneet Gupta and Mani Srivastava},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/j23.pdf},
title = {{H}ardware {V}ariability-{A}ware {D}uty {C}ycling for {E}mbedded {S}ensors},
year = {2012}
}


[J24] J. Lee and P. Gupta, “ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes,” ACM Transactions on Design Automation of Electronic Systems, 2012.
[Bibtex]

@article{J24,
author = {John Lee and Puneet Gupta},
journal = {{ACM Transactions on Design Automation of Electronic Systems}},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J24_paper.pdf},
title = {{ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes}},
year = {2012}
}


[J26] P. Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. N. T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester, “Underdesigned and opportunistic computing in presence of hardware variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012. – Keynote Paper
[Bibtex]

@article{J26,
author = {Puneet Gupta and Yuvraj Agarwal and Lara Dolecek and Nikil Dutt and Rajesh K. Gupta and Rakesh Kumar and Subhasish Mitra and Alexandru Nicolauand Tajana Simunic Rosing and Mani B. Srivastava and Steven Swanson and Dennis Sylvester},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {hsi},
note = {Keynote Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/UnO_keynote.pdf},
title = {Underdesigned and Opportunistic Computing in Presence of Hardware Variability},
year = {2012}
}


[J27] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, “Layout Decomposition and Legalization for Double-Patterning Technology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
[Bibtex]

@article{J27,
author = {Ghaida, R. S. and Agarwal, K. B. and Nassif, S. R. and Yuan, X. and Liebmann, L. W. and Gupta, P.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi, multiple-patterning},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J27_paper.pdf},
title = {{L}ayout {D}ecomposition and {L}egalization for {D}ouble-{P}atterning {T}echnology},
year = {2012}
}


[J17] A. Pant, P. Gupta, and M. van der Schaar, “Appadapt: opportunistic application adaptation in presence of hardware variation,” IEEE Transactions on Very Large Scale Integration Systems, 2011.
[Bibtex]

@article{J17,
author = {Aashish Pant and Gupta, Puneet and Mihaela van der Schaar},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/VarAwareAdapt.pdf},
title = {AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation},
year = {2011}
}


[J16] P. Kulkarni, P. Gupta, and M. D. Ercegovac, “Trading accuracy for power in a multiplier architecture,” Journal of Low Power Electronics, 2011.
[Bibtex]

@article{J16,
author = {Kulkarni, P. and Gupta, P. and Ercegovac, M.D.},
journal = {{Journal of Low Power Electronics}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/JOLPE_v3.pdf},
title = {Trading Accuracy for Power in a Multiplier Architecture},
year = {2011}
}


[J15] T. B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2011.
[Bibtex]

@article{J15,
author = {Chan, T.B. and Kagalwalla, Abde Ali and Gupta, P. },
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J15_paper.pdf},
title = {{M}easurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},
year = {2011}
}


[J12] J. Cong, P. Gupta, and J. Lee, “Evaluating Statistical Power Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, iss. 11, p. 1750–1762, 2010.
[Bibtex]

@article{J12,
author = {Cong, J. and Gupta, P. and Lee, John},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {sizing, mad},
month = {Nov},
number = {11},
pages = {1750--1762},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J12_paper.pdf},
title = {{Evaluating Statistical Power Optimization}},
volume = {29},
year = {2010}
}


[J10] R. S. Ghaida and P. Gupta, “Within-Layer Overlay Impact for Design in Metal Double Patterning,” IEEE Transactions on Semiconductor Manufacturing, 2010.
[Bibtex]

@article{J10,
author = {Ghaida, R. S. and Gupta, P.},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {double patterning, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J10_paper.pdf},
title = {Within-{L}ayer {O}verlay {I}mpact for {D}esign in {M}etal {D}ouble {P}atterning},
year = {2010}
}


[J14] L. Cheng, P. Gupta, C. J. Spanos, K. Qian, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2010.
[Bibtex]

@article{J14,
author = {Cheng, L. and Gupta, P. and Spanos, C. J. and Qian, K. and He, L.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J14_paper.pdf},
title = {{P}hysically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},
year = {2010}
}


[J13] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,” IEEE Transactions on Semiconductor Manufacturing, 2010.
[Bibtex]

@article{J13,
author = {Ghaida, R. S. and Torres, G. and Gupta, P.},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {double patterning, stdpl, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J13_paper.pdf},
title = {{S}ingle-{M}ask {D}ouble-{P}atterning {L}ithography for {R}educed {C}ost and {I}mproved {O}verlay {C}ontrol},
year = {2010}
}


[J11] P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, “Electrical Assessment of Lithographic Gate Line-End Patterning,” spieJ, 2010.
[Bibtex]

@article{J11,
author = {Gupta, P. and Jeong, K. and Kahng, A.B. and Park, C.-H.},
journal = {{spieJ}},
keywords = {mad, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J11_paper.pdf},
title = {Electrical {A}ssessment of {L}ithographic {G}ate {L}ine-{E}nd {P}atterning},
year = {2010}
}


[J9] L. Cheng, P. Gupta, and L. He, “Efficient Additive Statistical Leakage Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2009.
[Bibtex]

@article{J9,
author = {Cheng, L. and Gupta, P. and He, L.},
category = {J9},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J9_paper.pdf},
title = {Efficient {A}dditive {S}tatistical {L}eakage {E}stimation},
year = {2009}
}


[J7] P. Gupta, A. B. Kahng, and C. -H. Park, “Detailed Placement for Enhanced Control of Resist and Etch CDs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2007.
[Bibtex]

@article{J7,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H.},
category = {J7},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
month = {December},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J7_paper.pdf},
title = {Detailed {P}lacement for {E}nhanced {C}ontrol of {R}esist and {E}tch {CD}s},
year = {2007}
}


[J6] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2007.
[Bibtex]

@article{J6,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},
category = {J6},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J6_paper.pdf},
title = {Self-{C}ompensating {D}esign for {R}eduction of {T}iming and {L}eakage {S}ensitivity to {S}ystematic {P}attern {D}ependent {V}ariation},
year = {2007}
}


[J8] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven Optical Proximity Correction for Mask Cost Reduction,” spieJ, 2007.
[Bibtex]

@article{J8,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
category = {J8},
journal = {{spieJ}},
keywords = {dats},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J8_paper.pdf},
title = {Performance-{D}riven {O}ptical {P}roximity {C}orrection for {M}ask {C}ost {R}eduction},
year = {2007}
}


[J4] P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, “Gate-Length Biasing for Runtime Leakage Control,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2006.
[Bibtex]

@article{J4,
author = {Gupta, P. and Kahng, A. B. and Sharma, P. and Sylvester, D.},
category = {J4},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {sizing, mad},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J4_paper.pdf},
title = {Gate-{L}ength {B}iasing for {R}untime {L}eakage {C}ontrol},
year = {2006}
}


[J5] P. Gupta, A. B. Kahng, C. -H. Park, K. Samadi, and X. Xu, “Wafer Topography-Aware Optical Proximity Correction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2006.
[Bibtex]

@article{J5,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Samadi, K. and Xu, X.},
category = {J5},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
month = {April},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J5_paper.pdf},
title = {Wafer {T}opography-{A}ware {O}ptical {P}roximity {C}orrection},
year = {2006}
}


[J2] P. Gupta, A. B. Kahng, I. I. Mandoiu, and P. Sharma, “Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2005.
[Bibtex]

@article{J2,
author = {Gupta, P. and Kahng, A. B. and Mandoiu, I.I. and Sharma, P.},
category = {J2},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J2_paper.pdf},
title = {Layout-{A}ware {S}can {C}hain {S}ynthesis for {I}mproved {P}ath {D}elay {F}ault {C}overage},
year = {2005}
}


[J3] P. Gupta, A. B. Kahng, and S. Muddu, “Quantifying Error in Dynamic Power Estimation of CMOS Circuits,” Journal of Analog Integrated Circuits and Signal Processing, 2005.
[Bibtex]

@article{J3,
author = {Gupta, P. and Kahng, A. B. and Muddu, S.},
category = {J3},
journal = {{Journal of Analog Integrated Circuits and Signal Processing}},
keywords = {},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J3_paper.pdf},
title = {Quantifying {E}rror in {D}ynamic {P}ower {E}stimation of {CMOS} {C}ircuits},
year = {2005}
}


[J1] P. Gupta, A. B. Kahng, and S. Mantik, “Routing Driven Scan Chain Ordering,” ACM Transactions on Design Automation of Electronic Systems, 2005.
[Bibtex]

@article{J1,
author = {Gupta, P. and Kahng, A. B. and Mantik, S.},
category = {J1},
journal = {{ACM Transactions on Design Automation of Electronic Systems}},
keywords = {},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J1_paper.pdf},
title = {Routing {D}riven {S}can {C}hain {O}rdering},
year = {2005}
}

---

Conferences

[C131] A. Graening, D. A. Patel, G. Sisto, E. Lenormand, M. Perumkunnil, N. Pantano, V. B. Y. Kumar, P. Gupta, and A. Mallik, “Cost-performance co-optimization for the chiplet era,” in IEEE Electronics Packaging Technology Conference (EPTC), 2024, p. 6
[Bibtex]

@inproceedings{C131,
author = {Graening, Alexander and Patel, Darayus Adil and Sisto, Giuliano and Lenormand, Erwan and Perumkunnil, Manu and Pantano, Nicolas and Kumar, Vinay B.Y. and Gupta, Puneet and Mallik, Arindam},
booktitle = {{IEEE Electronics Packaging Technology Conference (EPTC)}},
doi = {},
keywords = {},
month = {December},
number = {},
pages = {6},
title = {Cost-Performance Co-Optimization for the Chiplet Era},
volume = {},
year = {2024}
}


[C127] W. Romaszkan, J. Yang, A. Graening, V. Jacob, J. Sen, S. Pamarti, and P. Gupta, “SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras,” in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024, p. 12
[Bibtex]

@inproceedings{C127,
author = {Romaszkan, Wojciech and Yang, Jiyue and Graening, Alexander and Jacob, Vinod and Sen, Jishnu and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
doi = {},
keywords = {},
month = {September},
pages = {12},
title = {{SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras}},
year = {2024}
}


[C129] J. Kundu, W. Guo, A. BanaGozar, U. D. Alwis, S. Sengupta, P. Gupta, and A. Mallik, “Performance Modeling and Workload Analysis of Distributed Large Language Model Training and Inference,” in IEEE International Symposium on Workload Characterization, 2024, p. 12 – Best paper nomination
[Bibtex]

@inproceedings{C129,
author = {Kundu, Joyjit and Guo, Wenzhe and BanaGozar, Ali and Alwis, Udari De and Sengupta, Sourav and Gupta, Puneet and Mallik, Arindam},
booktitle = {{IEEE International Symposium on Workload Characterization}},
doi = {},
keywords = {},
month = {September},
note = {Best paper nomination},
pages = {12},
title = {{Performance Modeling and Workload Analysis of Distributed
Large Language Model Training and Inference}},
year = {2024}
}


[C126] S. Pal, J. Yang, S. Bauer, P. Gupta, and S. Pamarti, “Novel Energy-Efficient and Latency-Improved PVT Tolerant Read Scheme for SRAM Design in Video Processing and Machine Learning Applications,” in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2024, p. 4
[Bibtex]

@inproceedings{C126,
author = {Pal, Soumitra and Yang, Jiyue and Bauer, Stephen and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{{IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)}}},
doi = {},
keywords = {},
month = {August},
note = {},
pages = {4},
title = {{Novel Energy-Efficient and Latency-Improved PVT Tolerant Read Scheme for SRAM Design in Video Processing and Machine Learning Applications}},
year = {2024}
}


[C128] J. Yang, A. Graening, W. Romaszkan, V. K. Jacob, P. Gupta, and S. Pamarti, “A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera,” in IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p. 2
[Bibtex]

@inproceedings{C128,
author = {Yang, Jiyue and Graening, Alexander and Romaszkan, Wojciech and Jacob, Vinod K. and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)}},
doi = {},
keywords = {},
month = {June},
pages = {2},
title = {{A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera}},
year = {2024}
}


[C130] A. H. Hassan, P. Gupta, S. Pamarti, and C. K. Yang, “Cryogenic alternative: cmos versus dynamic-based logic,” in 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS), 2024, pp. 1007-1010
[Bibtex]

@inproceedings{C130,
author = {Hassan, Ali H. and Gupta, Puneet and Pamarti, Sudhakar and Yang, Chih-Kong Ken},
booktitle = {{2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)}},
doi = {10.1109/MWSCAS60917.2024.10658785},
keywords = {Costs;Cooling;Liquid nitrogen;FinFETs;Threshold voltage;Energy efficiency;Logic;Cryogenic Computing;Efficient Computing;CryoCMOS;CMOS Logic;Domino Logic;NORA Logic;Adders},
number = {},
pages = {1007-1010},
title = {Cryogenic Alternative: CMOS Versus Dynamic-Based Logic},
volume = {},
year = {2024}
}


[C125] S. Li, H. Yang, C. W. Wong, V. J. Sorger, and P. Gupta, “ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator,” in IEEE/ACM International Symposium on Microarchitecture (MICRO), 2023, p. 13
[Bibtex]

@inproceedings{C125,
author = {Li, Shurui and Yang, Hangbo and Wong, Chee Wei and Sorger, Volker J. and Gupta, Puneet},
booktitle = {{IEEE/ACM International Symposium on Microarchitecture (MICRO)}},
doi = {https://doi.org/10.1145/3613424.3623798.},
keywords = {photonic neural network,deep learning, accelerator, photonics},
month = {October},
note = {},
pages = {13},
title = {{ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator}},
year = {2023}
}


[C124] A. Graening, S. Pal, and P. Gupta, “Chiplets: How Small is too Small?,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2023, p. 6
[Bibtex]

@inproceedings{C124,
author = {Graening, Alexander and Pal, Saptadeep and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
doi = {},
keywords = {chiplets,wsi},
month = {July},
note = {},
pages = {6},
title = {{Chiplets: How Small is too Small?}},
year = {2023}
}


[C123] T. Li, S. Li, and P. Gupta, “Training Neural Networks for Execution on Approximate Hardware,” in International Research Symposium on Tiny Machine Learning (tinyML), 2023, p. 6
[Bibtex]

@inproceedings{C123,
author = {Li, Tianmu and Li, Shurui and Gupta, Puneet},
booktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},
doi = {},
keywords = {approximate computing, neural networks, training},
month = {March},
note = {},
pages = {6},
title = {{Training Neural Networks for Execution on Approximate Hardware}},
year = {2023}
}


[C122] S. Li, H. Yang, C. W. Wong, V. J. Sorger, and P. Gupta, “PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator,” in IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023, p. 12
[Bibtex]

@inproceedings{C122,
author = {Li, Shurui and Yang, Hangbo and Wong, Chee Wei and Sorger, Volker J. and Gupta, Puneet},
booktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},
doi = {},
keywords = {photonics, neural network, accelerator},
month = {February},
note = {},
pages = {12},
title = {{PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator}},
year = {2023}
}


[C121] J. Yang, T. Li, W. Romaszkan, P. Gupta, and S. Pamarti, “A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor,” in IEEE Asian Solid-State Circuits Conference, 2022, p. 2
[Bibtex]

@inproceedings{C121,
author = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{IEEE Asian Solid-State Circuits Conference}},
doi = {},
keywords = {mledge},
month = {November},
note = {},
pages = {2},
title = {{A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor}},
year = {2022}
}


[C120] W. Romaszkan, T. Li, and P. Gupta, “SASCHA – Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,” in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022, p. 12 – Best paper nomination
[Bibtex]

@inproceedings{C120,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
doi = {},
keywords = {mledge},
month = {October},
note = {Best paper nomination},
pages = {12},
title = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},
year = {2022}
}


[C119] S. Li and P. Gupta, “Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors,” in Conference on Machine Learning and Systems (MLSys), 2022, p. 10
[Bibtex]

@inproceedings{C119,
author = {Li, Shurui and Gupta, Puneet},
booktitle = {{Conference on Machine Learning and Systems (MLSys)}},
doi = {},
keywords = {mledge},
month = {August},
note = {},
pages = {10},
title = {{Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors}},
year = {2022}
}


[C118] I. Alam and P. Gupta, “COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors,” in IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2022, p. 13
[Bibtex]

@inproceedings{C118,
author = {Alam, Irina and Gupta, Puneet},
booktitle = {{IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)}},
doi = {},
keywords = {},
month = {June},
note = {},
pages = {13},
title = {{COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors}},
year = {2022}
}


[C117] V. Gupta, T. Li, and P. Gupta, “LAC: Learned Approximate Computing,” in IEEE/ACM Design, Automation and Test in Europe, 2022, p. 4
[Bibtex]

@inproceedings{C117,
author = {Gupta, Vaibhav and Li, Tianmu and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {},
keywords = {},
month = {March},
note = {},
pages = {4},
title = {{LAC: Learned Approximate Computing}},
year = {2022}
}


[C116] S. Pal, J. Liu, I. Alam, N. Cebry, H. Suhail, S. Bu, S. S. Iyer, S. Pamarti, R. Kumar, and P. Gupta, “Designing a 2048-Chiplet, 14336-Core Waferscale Processor,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2021
[Bibtex]

@inproceedings{C116,
author = {Pal, Saptadeep and Liu, Jingyang and Alam, Irina and Cebry, Nicholas and Suhail, Haris and Bu, Shi and Iyer, Subramanian S. and Pamarti, Sudhakar and Kumar, Rakesh and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
doi = {},
keywords = {wsi},
month = {December},
note = {},
pages = {},
title = {{Designing a 2048-Chiplet, 14336-Core Waferscale Processor}},
year = {2021}
}


[C115] J. Yang, D. Wu, A. Lee, S. A. Razavi, P. Gupta, K. L. Wang, and S. Pamarti, “A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM,” in IEEE European Solid-State Circuits Conference (ESSCIRC), 2021, p. 4
[Bibtex]

@inproceedings{C115,
author = {Yang, Jiyue and Wu, Di and Lee, Albert and Razavi, Seyed Armin and Gupta, Puneet and Wang, Kang L. and Pamarti, Sudhakar},
booktitle = {{IEEE European Solid-State Circuits Conference (ESSCIRC)}},
doi = {},
keywords = {},
month = {September},
note = {},
pages = {4},
title = {{A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM}},
year = {2021}
}


[C114] S. Pal, K. Sahoo, I. Alam, H. Suhail, R. Kumar, S. Pamarti, P. Gupta, and S. S. Iyer, “I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor,” in IEEE Electronic Components and Technology Conference (ECTC), 2021
[Bibtex]

@inproceedings{C114,
author = {Pal, Saptadeep and Sahoo, Krutikesh and Alam, Irina and Suhail, Haris and Kumar, Rakesh and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},
booktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},
doi = {},
keywords = {wsi},
month = {June},
note = {},
pages = {},
title = {{I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor}},
year = {2021}
}


[C113] S. Li, W. Romaszkan, A. Graening, and P. Gupta, “SWIS – Shared Weight bIt Sparsity for Efficient Neural Network Acceleration,” in International Research Symposium on Tiny Machine Learning (tinyML), 2021
[Bibtex]

@inproceedings{C113,
author = {Li, Shurui and Romaszkan, Wojciech and Graening, Alexander and Gupta, Puneet},
booktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},
doi = {},
keywords = {mledge, quantization, systolic array},
month = {March},
note = {},
pages = {},
title = {{SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration}},
year = {2021}
}


[C112] T. Li, W. Romaszkan, S. Pamarti, and P. Gupta, “GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks,” in IEEE/ACM Design, Automation and Test in Europe, 2021
[Bibtex]

@inproceedings{C112,
author = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {},
keywords = {mledge},
month = {February},
note = {},
pages = {},
title = {{GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks}},
year = {2021}
}


[C111] S. Pal and P. Gupta, “Pathfinding for 2.5D Interconnect Technologies,” in System-Level Interconnect – Problems and Pathfinding Workshop, New York, NY, USA, 2020
[Bibtex]

@inproceedings{C111,
address = {New York, NY, USA},
author = {Pal, Saptadeep and Gupta, Puneet},
booktitle = {{System-Level Interconnect - Problems and Pathfinding Workshop}},
keywords = {wsi},
location = {San Diego, California},
month = {November},
numpages = {8},
publisher = {ACM},
series = {SLIP '20},
title = {{Pathfinding for 2.5D Interconnect Technologies}},
year = {2020}
}


[C110] I. Alam and P. Gupta, “SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge,” in Proceedings of the International Symposium on Memory Systems, New York, NY, USA, 2020
[Bibtex]

@inproceedings{C110,
address = {New York, NY, USA},
author = {Alam, Irina and Gupta, Puneet},
booktitle = {{Proceedings of the International Symposium on Memory Systems}},
keywords = {memres},
location = {Washington, District of Columbia},
month = {September},
numpages = {13},
publisher = {ACM},
series = {MEMSYS '20},
title = {{SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge}},
year = {2020}
}


[C109] W. Romaszkan, T. Li, T. Melton, S. Pamarti, and P. Gupta, “ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing,” in IEEE/ACM Design, Automation and Test in Europe, 2020, pp. 768-773 – Best paper nomination
[Bibtex]

@inproceedings{C109,
author = {Romaszkan, Wojciech and Li, Tianmu and Melton, Tristan and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {10.23919/DATE48585.2020.9116289},
keywords = {mledge},
month = {March},
note = {Best paper nomination},
pages = {768-773},
title = {{ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing}},
year = {2020}
}


[C108] I. Alam, S. Pal, and P. Gupta, “Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories,” in Proceedings of the International Symposium on Memory Systems, New York, NY, USA, 2019, p. 85–100
[Bibtex]

@inproceedings{C108,
acmid = {3357533},
address = {New York, NY, USA},
author = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},
booktitle = {{Proceedings of the International Symposium on Memory Systems}},
doi = {10.1145/3357526.3357533},
isbn = {978-1-4503-7206-0},
keywords = {memres},
location = {Washington, District of Columbia},
month = {September},
numpages = {16},
pages = {85--100},
publisher = {ACM},
series = {MEMSYS '19},
title = {{Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},
url = {http://doi.acm.org/10.1145/3357526.3357533},
year = {2019}
}


[C107] S. Pal, D. Petrisko, M. Tomei, S. S. Iyer, P. Gupta, and R. Kumar, “Architecting Waferscale Processors – A GPU Case Study,” in IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2019, pp. 250-263
[Bibtex]

@inproceedings{C107,
author = {Pal, Saptadeep and Petrisko, Daniel and Tomei, Matthew and Iyer, Subramanian S. and Gupta, Puneet and Kumar, Rakesh},
booktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},
doi = {10.1109/HPCA.2019.00042},
issn = {1530-0897},
keywords = {wsi},
month = {February},
pages = {250-263},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C106_paper.pdf},
title = {{Architecting Waferscale Processors - A GPU Case Study}},
year = {2019}
}


[C106] C. Schoeny, I. Alam, M. Gottscho, P. Gupta, and L. Dolecek, “Error Correction and Detection for Computing Memories Using System Side Information,” in IEEE Information Theory Workshop (ITW), 2018
[Bibtex]

@inproceedings{C106,
author = {Schoeny, Clayton and Alam, Irina and Gottscho, Mark and Gupta, Puneet and Dolecek, Lara},
booktitle = {{IEEE Information Theory Workshop (ITW)}},
keywords = {memres},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C108_paper.pdf},
title = {{Error Correction and Detection for Computing Memories Using System Side Information}},
year = {2018}
}


[C105] Y. Chae, R. Jonckheere, and P. Gupta, “Defect Avoidance for Extreme Ultraviolet Mask Defects using Intentional Pattern Deformation,” in SPIE, International Conference on Extreme Ultraviolet Lithography, 2018
[Bibtex]

@inproceedings{C105,
author = {Chae, Yoojin and Jonckheere, Rik and Gupta, Puneet},
booktitle = {{SPIE, International Conference on Extreme Ultraviolet Lithography}},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C105_paper.pdf},
title = {{Defect Avoidance for Extreme Ultraviolet Mask Defects using Intentional Pattern Deformation}},
year = {2018}
}


[C104] I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, “Parity++: Lightweight Error Correction for Last Level Caches,” in IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2018
[Bibtex]

@inproceedings{C104,
author = {Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)}},
keywords = {memres},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C104_paper.pdf},
title = {{Parity++: Lightweight Error Correction for Last Level Caches}},
year = {2018}
}


[C103] Y. Luo and P. Gupta, “Relaxing ler requirement in euv lithography,” in SPIE Advanced Lithography, 2018
[Bibtex]

@inproceedings{C103,
author = {Luo, Yandong and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography}},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C103_paper.pdf},
title = {Relaxing LER requirement in EUV Lithography},
year = {2018}
}


[C102] A. Deng, Y. Badr, and P. Gupta, “Dynamic programming approach to adaptive slicing for optimization under a global volumetric error constraint,” in SPIE Laser 3D Manufacturing V, 2018
[Bibtex]

@inproceedings{C102,
author = {Deng, Andrew and Badr, Yasmine and Gupta, Puneet},
booktitle = {{SPIE Laser 3D Manufacturing V}},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C102_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C102_slides.pptx},
title = {Dynamic programming approach to adaptive slicing for optimization under a global volumetric error constraint},
year = {2018}
}


[C100] S. Pal, D. Petrisko, A. Bajwa, S. S. Iyer, R. Kumar, and P. Gupta, “A Case for Packageless Processors,” in IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2018
[Bibtex]

@inproceedings{C100,
author = {Pal, Saptadeep and Petrisko, Daniel and Bajwa, Adeel and Iyer, Subramanian S. and Kumar, Rakesh and Gupta, Puneet},
booktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},
keywords = {wsi},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C100_paper.pdf},
title = {{A Case for Packageless Processors}},
year = {2018}
}


[C101] C. Schoeny, F. Sala, M. Gottscho, I. Alam, P. Gupta, and L. Dolecek, “Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories,” in IEEE Information Theory Workshop (ITW), 2017
[Bibtex]

@inproceedings{C101,
author = {Schoeny, Clayton and Sala, Fredric and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},
booktitle = {{IEEE Information Theory Workshop (ITW)}},
keywords = {memres},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C101_paper.pdf},
title = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},
year = {2017}
}


[C99] W. Wang, Y. Yona, Y. Wu, S. Hung, S. Diggavi, and P. Gupta, “Implementation of Stable PUFs Using Gate Oxide Breakdown,” in IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST), 2017
[Bibtex]

@inproceedings{C99,
author = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Hung, Szu-Yao and Diggavi, Suhas and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST)}},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C99_paper.pdf},
title = {{Implementation of Stable PUFs Using Gate Oxide Breakdown}},
year = {2017}
}


[C98] M. Gottscho, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, “Low-Cost Memory Fault Tolerance for IoT Devices,” , 2017. – Best paper award
[Bibtex]

@article{C98,
author = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},
keywords = {memres},
month = {October},
note = {Best paper award},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J54_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C98_slides.pptx},
title = {{Low-Cost Memory Fault Tolerance for IoT Devices}},
volume = {},
year = {2017}
}


[C96] S. Jangam, S. Pal, A. Bajwa, S. Pamarti, P. Gupta, and S. S. Iyer, “Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme,” in IEEE Electronic Components and Technology Conference (ECTC), 2017
[Bibtex]

@inproceedings{C96,
author = {Jangam, SivaChandra and Pal, Saptadeep and Bajwa, Adeel and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},
booktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},
keywords = {Silicon Interconnect Fabric; Thermal Compression Bonding; Fine Pitch Interconnect, SuperCHIPS, wsi},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C96_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C96_slides.pdf},
title = {{L}atency, {B}andwidth and {P}ower {B}enefits of the {S}uper{CHIPS} {I}ntegration {S}cheme},
year = {2017}
}


[C95] S. Wang, S. Pal, T. Li, A. Pan, C. Grezes, K. P. Amiri, K. L. Wang, C. O. Chui, and P. Gupta, “Hybrid VC-MTJ/CMOS Non-volatile Stochastic Logic for Efficient Computing,” in IEEE/ACM Design, Automation and Test in Europe, 2017 – Best paper nomination
[Bibtex]

@inproceedings{C95,
author = {Wang, Shaodi and Pal, Saptadeep and Li, Tianmu and Pan, Andrew and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Chui, Chi On and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
keywords = {mledge,Negative differential resistance, Magnetic tunnel junction, stochastic computing, stochastic bitstream generator, non-volatile computing},
month = {March},
note = {Best paper nomination},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C95_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C95_slides.pdf},
title = {{H}ybrid {VC-MTJ/CMOS} {N}on-volatile {S}tochastic {L}ogic for {E}fficient {C}omputing},
year = {2017}
}


[C97] Y. Badr and P. Gupta, “Technology Path-finding for Directed Self-assembly for Via Layers”,” in SPIE Advanced Lithography Symposium, 2017
[Bibtex]

@inproceedings{C97,
author = {Badr, Yasmine and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C97_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C97_slides.pdf},
title = {{T}echnology {P}ath-finding for {D}irected {S}elf-assembly for {V}ia {L}ayers"},
year = {2017}
}


[C92] S. Wang, H. Lee, C. Grezes, P. Khalili, K. L. Wang, and P. Gupta, “MTJ Variation Monitor-assisted Adaptive MRAM Write,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2016
[Bibtex]

@inproceedings{C92,
author = {Wang, Shaodi and Lee, Hochul and Grezes, Cecile and Khalili, Pedram and Wang, Kang L. and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {MRAM},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C92_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C92_slides.pdf},
title = { {MTJ} {V}ariation {M}onitor-assisted {A}daptive {MRAM} {W}rite},
year = {2016}
}


[C93] M. Gottscho, C. Schoeny, L. Dolecek, and P. Gupta, “Software-Defined Error-Correcting Codes,” in IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2016
[Bibtex]

@conference{C93,
author = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)}},
keywords = {ecc,memory,reliability,architecture,coding,systems,dram,caches,memres},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_slides.pptx},
title = {{Software-Defined Error-Correcting Codes}},
year = {2016}
}


[C94] W. Wang, Y. Yona, S. Diggavi, and P. Gupta, “LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016
[Bibtex]

@inproceedings{C94,
author = {Wang, Wei-Che and Yona, Yair and Diggavi, Suhas and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Hardware Oriented Security and Trust (HOST)}},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C94_paper.pdf},
title = {{LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity}},
year = {2016}
}


[C91] M. Gottscho, S. Govindan, B. Sharma, M. Shoaib, and P. Gupta, “X-Mem: A Cross-Platform and Extensible Memory Characterization Tool for the Cloud,” in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2016
[Bibtex]

@inproceedings{C91,
author = {Gottscho, Mark and Govindan, Sriram and Sharma, Bikash and Shoaib, Mohammed and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)}},
keywords = {},
month = {April},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C91_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C91_slides.pdf},
title = {{X}-{M}em: {A} {C}ross-{P}latform and {E}xtensible {M}emory {C}haracterization {T}ool for the {C}loud},
year = {2016}
}


[C89] Q. Zhang, L. Lai, M. Gottscho, and P. Gupta, “Multi-Story Power Distribution Networks for GPUs,” in IEEE/ACM Design, Automation and Test in Europe, 2016
[Bibtex]

@inproceedings{C89,
author = {Zhang, Qixiang and Lai, Liangzhen and Gottscho, Mark and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C89_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C89_slides.pptx},
title = {{M}ulti-{S}tory {P}ower {D}istribution {N}etworks for {GPU}s},
year = {2016}
}


[C90] L. Lai and P. Gupta, “Hardware Reliability Margining for the Dark Silicon Era,” in Proc. Asia and South Pacific Design Automation Conference, 2016
[Bibtex]

@inproceedings{C90,
author = {Lai, Liangzhen and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {hsi},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C90_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C90_slides.pptx},
title = {{H}ardware {R}eliability {M}argining for the {D}ark {S}ilicon {E}ra},
year = {2016}
}


[C88] L. Lai, V. Chandra, and P. Gupta, “Evaluating and Exploiting Impacts of Dynamic Power Management Schemes on System Reliability,” in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2015
[Bibtex]

@inproceedings{C88,
author = {Lai, Liangzhen and Chandra, Vikas and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)}},
keywords = {hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C88_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C88_slides.pdf},
title = {{E}valuating and {E}xploiting {I}mpacts of {D}ynamic {P}ower {M}anagement {S}chemes on {S}ystem {R}eliability},
year = {2015}
}


[C87] A. A. Kagalwalla and P. Gupta, “Effective Model-Based Mask Fracturing for Mask Cost Reduction,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2015
[Bibtex]

@inproceedings{C87,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C87_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C87_slides.pptx},
title = { {E}ffective {M}odel-{B}ased {M}ask {F}racturing for {M}ask {C}ost {R}eduction},
year = {2015}
}


[C86] Y. Badr, A. Torres, and P. Gupta, “Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts/Vias,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2015
[Bibtex]

@inproceedings{C86,
author = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C86_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C86_slides.pdf},
title = { {M}ask {A}ssignment and {S}ynthesis of {DSA}-{MP} {H}ybrid {L}ithography for sub-7nm {C}ontacts/{V}ias},
year = {2015}
}


[C85] Y. Badr, A. Torres, and P. Gupta, “Incorporating DSA in multipatterning semiconductor manufacturing technologies,” in SPIE Advanced Lithography Symposium, 2015
[Bibtex]

@inproceedings{C85,
author = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C85_paper.pdf},
title = { {I}ncorporating {DSA} in {m}ultipatterning {s}emiconductor {m}anufacturing {t}echnologies},
year = {2015}
}


[C83] S. Sarma, N. Dutt, P. Gupta, N. Venkatasubramanian, and A. Nicolau, “CyberPhysical-System-On-Chip (CPSoC) : A Self-Aware MPSoC Paradigm with Cross-Layer Virtual Sensing and Actuation,” in IEEE/ACM Design, Automation and Test in Europe, 2015
[Bibtex]

@inproceedings{C83,
author = {Sarma, Santanu and Dutt, Nikil and Gupta, Puneet and Venkatasubramanian, Nalini and Nicolau, Alex},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C83_paper.pdf},
slideurl = {},
title = {{CyberPhysical-System-On-Chip (CPSoC) : A Self-Aware MPSoC Paradigm with Cross-Layer Virtual Sensing and Actuation}},
year = {2015}
}


[C80] T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, A. B. Kahng, and E. Sahouria, “Benchmarking of Mask Fracturing Heuristics,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014
[Bibtex]

@inproceedings{C80,
author = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. and Sahouria, Emile},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C80},
keywords = {dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C80_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C80_slides.pdf},
title = {Benchmarking of {M}ask {F}racturing {H}euristics},
year = {2014}
}


[C81] W. Wang and P. Gupta, “Efficient Layout Generation and Evaluation of Vertical Channel Devices,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014
[Bibtex]

@inproceedings{C81,
author = {Wang, Wei-Che and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C81},
keywords = {dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C81_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C81_slides.pdf},
title = {{E}fficient {L}ayout {G}eneration and {E}valuation of {V}ertical {C}hannel {D}evices},
year = {2014}
}


[C82] S. Elmalaki, M. Gottscho, P. Gupta, and M. Srivastava, “A Case for Battery Charging-Aware Power Management and Deferrable Task Scheduling in Smartphones,” in USENIX Workshop on Power-Aware Computing and Systems (HotPower), 2014
[Bibtex]

@inproceedings{C82,
author = {Elmalaki, Salma and Gottscho, Mark and Gupta, Puneet and Srivastava, Mani},
booktitle = {{USENIX Workshop on Power-Aware Computing and Systems (HotPower)}},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C82_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C82_slides.pdf},
title = {{A} {C}ase for {B}attery {C}harging-{A}ware {P}ower {M}anagement and {D}eferrable {T}ask {S}cheduling in {S}martphones},
year = {2014}
}


[C79] M. Gottscho, A. Banaiyan Mofrad, N. Dutt, A. Nicolau, and P. Gupta, “Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2014
[Bibtex]

@inproceedings{C79,
author = {Gottscho, Mark and Banaiyan, Mofrad, Abbas and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {memres},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C79_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C79_slides.pdf},
title = {{P}ower / {C}apacity {S}caling: {E}nergy {S}avings {W}ith {S}imple {F}ault-{T}olerant {C}aches},
year = {2014}
}


[C78] Y. Badr, K. Ma, and P. Gupta, “Layout Pattern-driven Design Rule Evaluation,” in SPIE Advanced Lithography Symposium, 2014
[Bibtex]

@inproceedings{C78,
author = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C78_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C78_slides.pdf},
title = {{L}ayout {P}attern-driven {D}esign {R}ule {E}valuation},
year = {2014}
}


[C77] A. A. Kagalwalla and P. Gupta, “Comprehensive Defect Avoidance Framework for Mitigating EUV Mask Defects,” in SPIE Advanced Lithography Symposium, 2014
[Bibtex]

@inproceedings{C77,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C77_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C77_slides.pdf},
title = {{C}omprehensive {D}efect {A}voidance {F}ramework for {M}itigating {EUV} {M}ask {D}efects},
year = {2014}
}


[C76] P. Kulkarni, P. Gupta, and R. Beraha, “Minimizing Clock Domain Crossing in Network on Chip Interconnect,” in IEEE International Symposium on Quality Electronic Design, 2014
[Bibtex]

@inproceedings{C76,
author = {Kulkarni, Parag and Gupta, Puneet and Beraha, Rudy},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
keywords = {dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C76_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C76_slides.pdf},
title = {{M}inimizing {C}lock {D}omain {C}rossing in {N}etwork on {C}hip {I}nterconnect},
year = {2014}
}


[C73] A. A. Kagalwalla, M. Lam, K. Adam, and P. Gupta, “EUV-CDA: Pattern Shift Aware Critical Density Analysis for EUV Mask Layouts,” in Proc. Asia and South Pacific Design Automation Conference, 2014
[Bibtex]

@inproceedings{C73,
author = {Kagalwalla, Abde Ali and Lam, Michael and Adam, Kostas and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C73_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C73_slides.pdf},
title = {{EUV-CDA}: {P}attern {S}hift {A}ware {C}ritical {D}ensity {A}nalysis for {EUV} {M}ask {L}ayouts},
year = {2014}
}


[C74] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, 2014
[Bibtex]

@inproceedings{C74,
author = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,dre},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_slides.pdf},
title = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},
year = {2014}
}


[C75] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “PROCEED: a Pareto Optimization-based Circuit-level Evaluator for Emerging Devices,” in Proc. Asia and South Pacific Design Automation Conference, 2014
[Bibtex]

@inproceedings{C75,
author = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,proceed},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C75_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C75_slides.pptx},
title = {{PROCEED:} A {P}areto {O}ptimization-based {C}ircuit-level {E}valuator for {E}merging {D}evices},
year = {2014}
}


[C72] A. Sharma, J. Sloan, L. F. Wanner, S. H. Elmalaki, M. B. Srivastava, and P. Gupta, “Towards Analyzing and Improving Robustness of Software Applications to Intermittent and Permanent Faults in Hardware,” in Proc. IEEE International Conference on Computer Design, 2013
[Bibtex]

@inproceedings{C72,
author = {Sharma, Ankur and Sloan, Joseph and Wanner, Lucas F. and Elmalaki, Salma H. and Srivastava, Mani B. and Gupta, Puneet},
booktitle = {{Proc. IEEE International Conference on Computer Design}},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C72_paper.pdf},
title = {{T}owards {A}nalyzing and {I}mproving {R}obustness of {S}oftware {A}pplications to {I}ntermittent and {P}ermanent {F}aults in {H}ardware},
year = {2013}
}


[C71] M. Namaki-Shoushtari, A. Rahimi, N. Dutt, P. Gupta, and R. K. Gupta, “ARGO: Aging-aware GPGPU register file allocation,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, 2013
[Bibtex]

@inproceedings{C71,
author = {Namaki-Shoushtari, Majid and Rahimi, Abbas and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh K.},
booktitle = {{ACM International Conference on Hardware/Software Codesign and System Synthesis}},
keywords = {hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C71_paper.pdf},
title = {{A}{R}{G}{O}: {A}ging-aware {G}{P}{G}{P}{U} Register File Allocation},
year = {2013}
}


[C70] L. Wanner, S. Elmalaki, L. Lai, P. Gupta, and M. Srivastava, “VarEMU: An Emulation Testbed for Variability-Aware Software,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, 2013
[Bibtex]

@inproceedings{C70,
author = {Wanner, Lucas and Elmalaki, Salma and Lai, Liangzhen and Gupta, Puneet and Srivastava, Mani},
booktitle = {{ACM International Conference on Hardware/Software Codesign and System Synthesis}},
category = {C70},
keywords = {hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C70_paper.pdf},
title = {{V}ar{E}{M}{U}: {A}n {E}mulation {T}estbed for {V}ariability-{A}ware {S}oftware},
year = {2013}
}


[C68] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: a low overhead in situ on-line timing slack monitoring methodology,” in IEEE/ACM Design, Automation and Test in Europe, 2013
[Bibtex]

@inproceedings{C68,
author = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
catetory = {C68},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C68_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C68_slides.pdf},
title = {{S}lack{P}robe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology},
year = {2013}
}


[C69] R. S. Ghaida, M. Gupta, and P. Gupta, “A Framework for Exploring the Interaction between Design Rules and Overlay Control,” in SPIE Advanced Lithography, 2013
[Bibtex]

@inproceedings{C69,
author = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography}},
category = {C69},
keywords = {overlay, design rules, dre, alignment},
month = {Feburary},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C69_paper.pdf},
title = {A {F}ramework for {E}xploring the {I}nteraction between {D}esign {R}ules and {O}verlay {C}ontrol},
year = {2013}
}


[C64] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, “A methodology for the early exploration of design rules for multiple-patterning technologies,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012
[Bibtex]

@inproceedings{C64,
author = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C64},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_slides.pdf},
title = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},
year = {2012}
}


[C67] J. Lee and P. Gupta, “Impact of range and precision in technology on cell-based design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012
[Bibtex]

@inproceedings{C67,
author = {Lee, John and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C67},
keywords = {sizing},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C67_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C67_slides.pdf},
title = {Impact of Range and Precision in Technology on Cell-Based Design},
year = {2012}
}


[C65] L. Bathen, M. Gottscho, N. Dutt, P. Gupta, and A. Nicolau, “ViPZonE: OS-Level Memory Variability-Aware Physical Address Zoning for Energy Savings,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, 2012
[Bibtex]

@inproceedings{C65,
author = {Bathen, Luis and Gottscho, Mark and Dutt, Nikil and Gupta, Puneet and Nicolau, Alex},
booktitle = {{ACM International Conference on Hardware/Software Codesign and System Synthesis}},
category = {C65},
keywords = {hsi, vipzone, os, variability, variability-aware, dram, memory, power, zone, zoning, allocation},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C65_paper.pdf},
title = {{V}i{P}{Z}on{E}: {O}{S}-{L}evel {M}emory {V}ariability-{A}ware {P}hysical {A}ddress {Z}oning for {E}nergy {S}avings},
year = {2012}
}


[C66] J. Lee, P. Gupta, and F. Pikus, “Parametric hierarchy recovery in layout extracted netlists,” in Proc. IEEE Computer Society Annual Symposium on VLSI, 2012
[Bibtex]

@inproceedings{C66,
author = {Lee, John and Gupta, Puneet and Pikus, Fedor},
booktitle = {{Proc. IEEE Computer Society Annual Symposium on VLSI}},
category = {C66},
keywords = {variability-aware},
month = {August},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C66_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C66_slides.pdf},
title = {Parametric Hierarchy Recovery in Layout Extracted Netlists},
year = {2012}
}


[C61] L. A. D. Bathen, N. D. Dutt, A. Nicolau, and P. Gupta, “Vamv: variability-aware memory virtualization,” in DATE, 2012 – Best interactive presentation
[Bibtex]

@inproceedings{C61,
author = {L.A.D. Bathen and N.D. Dutt and A. Nicolau and P. Gupta},
booktitle = {{DATE}},
keywords = {hsi},
month = {March},
note = {Best interactive presentation},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/BathenDNG12.pdf},
title = {VaMV: Variability-aware Memory Virtualization},
year = {2012}
}


[C60] T. B. Chan, P. Gupta, A. Kahng, and L. Lai, “DDRO: a Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,” in ISQED, 2012
[Bibtex]

@inproceedings{C60,
author = {Chan, Tuck Boon and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen},
booktitle = {{ISQED}},
category = {C60},
keywords = {hsi, DDRO},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C60_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C60_slides.pdf},
title = {{DDRO}: A {N}ovel {P}erformance {M}onitoring {M}ethodology {B}ased on {D}esign-{D}ependent {R}ing {O}scillators},
year = {2012}
}


[C62] A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta, “Design-of-Experiments Based Design Rule Optimization,” in SPIE Advanced Lithography, 2012
[Bibtex]

@inproceedings{C62,
author = {Kagalwalla, Abde Ali and Muddu, Swamy and Capodieci, Luigi and Zelnik, Coby and Gupta, Puneet },
booktitle = {{SPIE Advanced Lithography}},
category = {C62},
keywords = {Design Rules, DOE, dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C62_paper.pdf},
title = {{D}esign-of-{E}xperiments {B}ased {D}esign {R}ule {O}ptimization},
year = {2012}
}


[C63] R. S. Ghaida, K. Agarwal, L. Liebmann, S. R. Nassif, and P. Gupta, “A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition,” in SPIE Advanced Lithography, 2012
[Bibtex]

@inproceedings{C63,
author = {Ghaida, R. S. and Agarwal, K. and Liebmann, L. and Nassif, S. R. and Gupta, P.},
booktitle = {{SPIE Advanced Lithography}},
category = {C63},
keywords = {triple patterning, double patterning, dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C63_paper.pdf},
title = {{A} {N}ovel {M}ethodology for {T}riple/{M}ultiple-{P}atterning {L}ayout {D}ecomposition},
year = {2012}
}


[C59] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A Framework for Double Patterning-Enabled Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011
[Bibtex]

@inproceedings{C59,
author = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C59},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C59_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C59_slides.pdf},
title = {A {F}ramework for {D}ouble {P}atterning-{E}nabled {D}esign},
year = {2011}
}


[C57] A. A. Kagalwalla, P. Gupta, D. Hur, and C. Park, “Defect-aware Reticle Floorplanning for EUV Masks,” in SPIE Advanced Lithography, 2011
[Bibtex]

@inproceedings{C57,
author = {Kagalwalla, Abde Ali and Gupta, Puneet and Hur, Duck-Hyung and Park, Chul-Hong },
booktitle = {{SPIE Advanced Lithography}},
category = {C57},
keywords = {EUV, floorplanning, dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C57_paper.pdf},
title = {{D}efect-aware {R}eticle {F}loorplanning for {EUV} {M}asks},
year = {2011}
}


[C56] L. Wanner, R. Balani, S. Zahedi, C. Apte, P. Gupta, and M. Srivastava, “Variability Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems,” in Design, Automation, and Test in Europe (DATE), 2011
[Bibtex]

@inproceedings{C56,
author = {Wanner, Lucas and Balani, Rahul and Zahedi, Sadaf and Apte, Charwak and Gupta, Puneet and Srivastava, Mani },
booktitle = {{Design, Automation, and Test in Europe (DATE)}},
category = {C56},
keywords = {variabilty-aware, embedded sensing, hsi},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C56_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C56_slides.pdf},
title = {{V}ariability {A}ware {D}uty {C}ycle {S}cheduling in {L}ong {R}unning {E}mbedded {S}ensing {S}ystems},
year = {2011}
}


[C55] T. -B. Chan, J. Sartori, P. Gupta, and R. Kumar, “On the Efficacy of NBTI Mitigation Techniques,” in Design, Automation, and Test in Europe (DATE), 2011
[Bibtex]

@inproceedings{C55,
author = {Chan, T.-B. and Sartori, John and Gupta, Puneet and Kumar, Rakesh},
booktitle = {{Design, Automation, and Test in Europe (DATE)}},
category = {C55},
keywords = {variabilty-aware, embedded sensing, hsi, ucla_rdmode},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C55_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C55_slides.pdf},
title = {{O}n the {E}fficacy of {NBTI} {M}itigation {T}echniques},
year = {2011}
}


[C54] P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading Accuracy for Power with an Underdesigned Multiplier Architecture,” in Proc. IEEE/ACM International Conference on VLSI Design, 2011
[Bibtex]

@inproceedings{C54,
author = {Kulkarni, Parag and Gupta, Puneet and Ercegovac, Milos},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C54},
keywords = {low power, hsi},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C54_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C54_slides.pdf},
title = {{T}rading {A}ccuracy for {P}ower with an {U}nderdesigned {M}ultiplier {A}rchitecture},
year = {2011}
}


[C52] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware Mask Inspection,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010
[Bibtex]

@inproceedings{C52,
author = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C52},
keywords = {mask manufacturing, inspection, dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C52_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C52_slides.pdf},
title = {{D}esign-aware {M}ask {I}nspection},
year = {2010}
}


[C53] T. -B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010
[Bibtex]

@inproceedings{C53,
author = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C53},
keywords = {process variation, process monitoring, dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_slides.pdf},
title = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},
year = {2010}
}


[C51] J. Lee and P. Gupta, “Incremental Gate Sizing for Late Process Changes,” in Proc. IEEE International Conference on Computer Design, 2010
[Bibtex]

@inproceedings{C51,
author = {Lee, John and Gupta, Puneet},
booktitle = {{Proc. IEEE International Conference on Computer Design}},
category = {C51},
keywords = {sizing, mad},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C51_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C51_slides.pdf},
title = {{I}ncremental {G}ate {S}izing for {L}ate {P}rocess {C}hanges},
year = {2010}
}


[C58] L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “A Case for Opportunistic Embedded Sensing In Presence of Hardware Power Varibility,” in HotPower’10, 2010
[Bibtex]

@conference{C58,
author = {Wanner, Lucas and Apte, Charwak and Balani, Rahul and Gupta, Puneet and Srivastava, Mani},
booktitle = {{HotPower'10}},
category = {C58},
keywords = {embedded sensing, leakage power, duty cycling, hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C58_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C58_slides.pdf},
title = {{A} {C}ase for {O}pportunistic {E}mbedded {S}ensing {I}n {P}resence of {H}ardware {P}ower {V}aribility},
year = {2010}
}


[C50] P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2010
[Bibtex]

@inproceedings{C50,
author = {Gupta, Puneet and Kahng, Andrew and Kasibhatla, Amarnath and Sharma, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C50},
keywords = {sizing, eyecharts},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C50_paper.pdf},
title = {{E}yecharts: {C}onstructive {B}enchmarking of {G}ate {S}izing {H}euristics},
year = {2010}
}


[C49] A. Pant, P. Gupta, and M. van der Schaar, “Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability,” in ACM Great Lakes Symposium on Very Large Scale Integration, 2010
[Bibtex]

@inproceedings{C49,
author = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},
booktitle = {{ACM Great Lakes Symposium on Very Large Scale Integration}},
category = {C49},
keywords = {hsi},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C49_paper.pdf},
title = {{S}oftware {A}daptation in {Q}uality {S}ensitive {A}pplications to {D}eal with {H}ardware {V}ariability},
year = {2010}
}


[C48] J. Sartori, A. Pant, R. Kumar, and P. Gupta, “Variation Aware Speed Binning of Multi-core Processors,” in IEEE International Symposium on Quality Electronic Design, 2010
[Bibtex]

@inproceedings{C48,
author = {Sartori, John and Pant, Aashish and Kumar, Rakesh and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
category = {C48},
keywords = {hsi},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C48_paper.pdf},
title = {{V}ariation {A}ware {S}peed {B}inning of {M}ulti-core {P}rocessors},
year = {2010}
}


[C46] T. -B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” in Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration, 2010
[Bibtex]

@inproceedings{C46,
author = {Chan, T.-B. and Kagalwalla, Abde Ali and Gupta, P.},
booktitle = {{Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration}},
category = {C46},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C46_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C46_slides.pdf},
title = {Measurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},
year = {2010}
}


[C45] T. -B. Chan and P. Gupta, “On Electrical Modeling of Imperfect Diffusion Patterning,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010
[Bibtex]

@inproceedings{C45,
author = {Chan, T.-B. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C45},
keywords = {dats, mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C45_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C45_slides.pdf},
title = {On {E}lectrical {M}odeling of {I}mperfect {D}iffusion {P}atterning},
year = {2010}
}


[C47] L. Cheng, P. Gupta, and L. He, “On Confidence in Characterization and Application of Variation Models,” in Proc. Asia and South Pacific Design Automation Conference, 2010
[Bibtex]

@inproceedings{C47,
author = {Cheng, L. and Gupta, P. and He, L.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C47},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C47_paper.pdf},
title = {On {C}onfidence in {C}haracterization and {A}pplication of {V}ariation {M}odels},
year = {2010}
}


[C44] R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic Evaluation of Design Rules,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2009
[Bibtex]

@inproceedings{C44,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C44},
keywords = {dats, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C44_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C44_slides.pdf},
title = {A {F}ramework for {E}arly and {S}ystematic {E}valuation of {D}esign {R}ules},
year = {2009}
}


[C41] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2009
[Bibtex]

@inproceedings{C41,
author = {Ghaida, R. S. and Torres, G. and Gupta, P.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
keywords = {dats},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C41_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C41_slides.pdf},
title = {Single-{M}ask {D}ouble-{P}atterning {L}ithography},
year = {2009}
}


[C40] R. S. Ghaida and P. Gupta, “Design-Overlay Interactions in Metal Double Patterning,” in SPIE Advanced Lithography Symposium, 2009
[Bibtex]

@inproceedings{C40,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {double patterning, test pattern, dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C40_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C40_slides.pdf},
title = {Design-{O}verlay {I}nteractions in {M}etal {D}ouble {P}atterning},
year = {2009}
}


[C39] L. Cheng, P. Gupta, and L. He, “Accounting for Non-linear Dependence Using Function Driven Component Analysis,” in Proc. Asia and South Pacific Design Automation Conference, 2009
[Bibtex]

@inproceedings{C39,
author = {Cheng, L. and Gupta, P. and He, L.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C39},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C39_paper.pdf},
title = {Accounting for {N}on-linear {D}ependence {U}sing {F}unction {D}riven {C}omponent {A}nalysis},
year = {2009}
}


[C38] J. Cong, P. Gupta, and J. Lee, “On the Futlity of Statistical Power Optimization,” in Proc. Asia and South Pacific Design Automation Conference, 2009
[Bibtex]

@inproceedings{C38,
author = {Cong, J. and Gupta, P. and Lee, John},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C38},
keywords = {sizing, mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C38_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C38_slides.pdf},
title = {On the {F}utlity of {S}tatistical {P}ower {O}ptimization},
year = {2009}
}


[C43] L. Cheng, P. Gupta, K. Qian, C. Spanos, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2009
[Bibtex]

@inproceedings{C43,
author = {Cheng, L. and Gupta, P. and Qian, K. and Spanos, C. and He, L.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C43},
keywords = {mad},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C43_paper.pdf},
title = {Physically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},
year = {2009}
}


[C42] P. Gupta and D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2009
[Bibtex]

@inproceedings{C42,
author = {Gupta, P. and Reinhard, D.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
category = {C42},
keywords = {dats},
month = {},
title = {On {C}omparing {C}onventional and {E}lectrically {D}riven {OPC} {T}echniques},
year = {2009}
}


[C37] P. Gupta and A. B. Kahng, “Bounded Lifetime Integrated Circuits,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2008
[Bibtex]

@inproceedings{C37,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C37},
keywords = {mad},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C37_paper.pdf},
title = {Bounded {L}ifetime {I}ntegrated {C}ircuits},
year = {2008}
}


[C36] P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, “Electrical Metrics for Lithographic Line-End Tapering,” in SPIE Photomask and NGL Mask Technology, 2008
[Bibtex]

@inproceedings{C36,
author = {Gupta, P. and Jeong, K. and Kahng, A. B. and Park, C.-H},
booktitle = {{SPIE Photomask and NGL Mask Technology}},
category = {C36},
keywords = {mad, dats},
month = {April},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C36_paper.pdf},
title = {Electrical {M}etrics for {L}ithographic {L}ine-{E}nd {T}apering},
year = {2008}
}


[C35] P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, “Shaping Gate Channels for Improved Devices,” in SPIE Advanced Lithography Symposium, 2008
[Bibtex]

@inproceedings{C35,
author = {Gupta, P. and Kahng, A. B. and Shah, S. and Sylvester, D.},
booktitle = {{SPIE Advanced Lithography Symposium}},
category = {C35},
keywords = {dats, mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C35_paper.pdf},
title = {Shaping {G}ate {C}hannels for {I}mproved {D}evices},
year = {2008}
}


[C34] P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Investigation of Diffusion Rounding for Post-Lithography Analysis,” in Proc. Asia and South Pacific Design Automation Conference, 2008
[Bibtex]

@inproceedings{C34,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S. and Sylvester, D.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C34},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C34_paper.pdf},
title = {Investigation of {D}iffusion {R}ounding for {P}ost-{L}ithography {A}nalysis},
year = {2008}
}


[C33] P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, “Line End Shortening is not Always a Failure,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2007
[Bibtex]

@inproceedings{C33,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C2},
keywords = {mad, dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C33_paper.pdf},
title = {Line {E}nd {S}hortening is not {A}lways a {F}ailure},
year = {2007}
}


[C32] P. Gupta, A. B. Kahng, and S. Shah, “Standard Cell Library Optimization for Leakage Reduction,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2006
[Bibtex]

@inproceedings{C32,
author = {Gupta, P. and Kahng, A. B. and Shah, S.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C32},
keywords = {sizing},
month = {July},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C32_paper.pdf},
title = {Standard {C}ell {L}ibrary {O}ptimization for {L}eakage {R}eduction},
year = {2006}
}


[C31] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,” in SPIE Microlithography, 2006
[Bibtex]

@inproceedings{C31,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},
booktitle = {{SPIE Microlithography}},
category = {C31},
keywords = {mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C31_paper.pdf},
title = {Self-{C}ompensating {D}esign for {R}eduction of {T}iming and {L}eakage {S}ensitivity to {S}ystematic {P}attern {D}ependent {V}ariation},
year = {2006}
}


[C28] P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah, and P. Sharma, “Lithography Simulation-Based Full-Chip Design Analyses,” in SPIE Microlithography, 2006
[Bibtex]

@inproceedings{C28,
author = {Gupta, P. and Kahng, A. B. and Nakagawa, S. and Shah, S. and Sharma, P.},
booktitle = {{SPIE Microlithography}},
category = {C28},
keywords = {mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C28_paper.pdf},
title = {Lithography {S}imulation-{B}ased {F}ull-{C}hip {D}esign {A}nalyses},
year = {2006}
}


[C29] P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis,” in SPIE Microlithography, 2006
[Bibtex]

@inproceedings{C29,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S. and Sylvester, D.},
booktitle = {{SPIE Microlithography}},
category = {C29},
keywords = {mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C2999999999_paper.pdf},
title = {Modeling of {N}on-{U}niform {D}evice {G}eometries for {P}ost-{L}ithography {C}ircuit {A}nalysis},
year = {2006}
}


[C27] P. Gupta and A. B. Kahng, “Efficient Design and Analysis of Robust Power Distribution Meshes,” in Proc. IEEE/ACM International Conference on VLSI Design, 2006
[Bibtex]

@inproceedings{C27,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C27},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C27_paper.pdf},
title = {Efficient {D}esign and {A}nalysis of {R}obust {P}ower {D}istribution {M}eshes},
year = {2006}
}


[C30] P. Gupta, A. B. Kahng, S. V. Muddu, and N. S., “Modeling Edge Placement Error Distribution in Standard Cell Library,” in SPIE Microlithography, 2006
[Bibtex]

@inproceedings{C30,
author = {Gupta, P. and Kahng, A. B. and Muddu, S.V. and Nakagawa S.},
booktitle = {{SPIE Microlithography}},
category = {C30},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C30_paper.pdf},
title = {Modeling {E}dge {P}lacement {E}rror {D}istribution in {S}tandard {C}ell {L}ibrary},
year = {2006}
}


[C25] P. Gupta, A. B. Kahng, S. Muddu, O. S. Nakagawa, and C. -H. Park, “Modeling OPC Complexity for Design for Manufacturability,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2005
[Bibtex]

@inproceedings{C25,
author = {Gupta, P. and Kahng, A. B. and Muddu,S. and Nakagawa, O.S. and Park, C.-H.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
category = {C25},
keywords = {dats},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C25_paper.pdf},
title = {Modeling {OPC} {C}omplexity for {D}esign for {M}anufacturability},
year = {2005}
}


[C24] P. Gupta, A. B. Kahng, and C. -H. Park, “Enhanced Resist and Etch CD Control by Design Perturbation,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2005
[Bibtex]

@inproceedings{C24,
author = {Gupta, P. and Kahng, A. B. and C.-H. Park},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
category = {C24},
keywords = {mad},
month = {October},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C24_paper.pdf},
title = {Enhanced {R}esist and {E}tch {CD} {C}ontrol by {D}esign {P}erturbation},
year = {2005}
}


[C23] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Focus Variation,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2005
[Bibtex]

@inproceedings{C23,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D. },
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C23},
keywords = {mad},
month = {June},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C23_paper.pdf},
title = {Self-{C}ompensating {D}esign for {F}ocus {V}ariation},
year = {2005}
}


[C26] Y. Zhang, R. Gray, O. S. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and C. Progler, “Interaction and Balance of Mask Write Time and Design RET Strategies,” in SPIE Photomask and NGL Mask Technology, 2005
[Bibtex]

@inproceedings{C26,
author = {Zhang, Y. and Gray, R. and Nakagawa, O.S. and Gupta, P. and Kamberian, H. and Xiao, G. and Cottle, R. and Progler, C.},
booktitle = {{SPIE Photomask and NGL Mask Technology}},
category = {C26},
keywords = {dats},
month = {April},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C26_paper.pdf},
title = {Interaction and {B}alance of {M}ask {W}rite {T}ime and {D}esign {RET} {S}trategies},
year = {2005}
}


[C18] P. Gupta, A. B. Kahng, and P. Sharma, “A Practical Transistor-Level Threshold Voltage Assignment Methodology,” in IEEE International Symposium on Quality Electronic Design, 2005, pp. 261-265
[Bibtex]

@inproceedings{C18,
author = {Gupta, P. and Kahng, A. B. and Sharma, P.},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
category = {C18},
keywords = {sizing},
month = {March},
pages = {261-265},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C18_paper.pdf},
title = {A {P}ractical {T}ransistor-{L}evel {T}hreshold {V}oltage {A}ssignment {M}ethodology},
year = {2005}
}


[C21] P. Gupta, F. -L. Heng, and J. -F. Lee, “Toward Through-Process Layout Quality Metrics,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2005
[Bibtex]

@inproceedings{C21,
author = {Gupta, P. and Heng, F.-L. and Lee, J.-F. },
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C21},
keywords = {mad},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C21_paper.pdf},
title = {Toward {T}hrough-{P}rocess {L}ayout {Q}uality {M}etrics},
year = {2005}
}


[C20] P. Gupta, A. B. Kahng, and C. -H. Park, “Manufacturing-Aware Design Methodology for Assist Feature Correctness,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2005
[Bibtex]

@inproceedings{C20,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H.},
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C20},
keywords = {mad},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C20_paper.pdf},
title = {Manufacturing-{A}ware {D}esign {M}ethodology for {A}ssist {F}eature {C}orrectness},
year = {2005}
}


[C17] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven OPC for Mask Cost Reduction,” in IEEE International Symposium on Quality Electronic Design, 2005, pp. 270-275
[Bibtex]

@inproceedings{C17,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
category = {C17},
keywords = {dats},
month = {March},
pages = {270-275},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C17_paper.pdf},
title = {Performance-{D}riven {OPC} for {M}ask {C}ost {R}eduction},
year = {2005}
}


[C19] P. Gupta, A. B. Kahng, and C. -H. Park, “Detailed Placement for Improved Depth of Focus and CD Control,” in Proc. Asia and South Pacific Design Automation Conference, 2005
[Bibtex]

@inproceedings{C19,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C19},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C19_paper.pdf},
title = {Detailed {P}lacement for {I}mproved {D}epth of {F}ocus and {CD} {C}ontrol},
year = {2005}
}


[C22] P. Gupta, A. B. Kahng, C. -H. Park, K. Samadi, and X. Xu, “Topography-Aware Optical Proximity Correction for Better DOF margin and CD Control,” in SPIE Photomask and NGL Mask Technology, 2005
[Bibtex]

@inproceedings{C22,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Samadi, K. and Xu, X. },
booktitle = {{SPIE Photomask and NGL Mask Technology}},
category = {C22},
keywords = {dats},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C22_paper.pdf},
title = {Topography-{A}ware {O}ptical {P}roximity {C}orrection for {B}etter {DOF} margin and {CD} {C}ontrol},
year = {2005}
}


[C15] P. Gupta, A. B. Kahng, P. Sharma, and D. D. Sylvester, “Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Reduction,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2004
[Bibtex]

@inproceedings{C15,
author = {Gupta, P. and Kahng, A. B. and Sharma, P. and D. Sylvester, D.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C5},
keywords = {sizing, mad},
month = {July},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C15_paper.pdf},
title = {Selective {G}ate-{L}ength {B}iasing for {C}ost-{E}ffective {R}untime {L}eakage {R}eduction},
year = {2004}
}


[C14] P. Gupta and F. -L. Heng, “Toward a Systematic-Variation Aware Timing Methodology,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2004
[Bibtex]

@inproceedings{C14,
author = {Gupta, P. and Heng, F.-L.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C14},
keywords = {mad},
month = {July},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C14_paper.pdf},
title = {Toward a {S}ystematic-{V}ariation {A}ware {T}iming {M}ethodology},
year = {2004}
}


[C16] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward a Methodology for Manufacturability Driven Design Rule Exploration,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2004
[Bibtex]

@inproceedings{C16,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C16},
keywords = {dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C16_paper.pdf},
title = {Toward a {M}ethodology for {M}anufacturability {D}riven {D}esign {R}ule {E}xploration},
year = {2004}
}


[C11] P. Gupta, F. -L. Heng, and M. Lavin, “Merits of Cellwise Model-Based OPC,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2004
[Bibtex]

@inproceedings{C11,
author = {Gupta, P. and Heng, F.-L. and Lavin, M. },
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C11},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C11_paper.pdf},
title = {Merits of {C}ellwise {M}odel-{B}ased {OPC}},
year = {2004}
}


[C13] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Investigation of Performance Metrics for Interconnect Stack Architectures,” in Proc. g SLIP, 2004
[Bibtex]

@inproceedings{C13,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},
booktitle = {{Proc. g SLIP}},
category = {C13},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C13_paper.pdf},
title = {Investigation of {P}erformance {M}etrics for {I}nterconnect {S}tack {A}rchitectures},
year = {2004}
}


[C12] P. Gupta, F. -L. Heng, R. L. Gordon, K. Lai, and J. Lee, “Taming Focus Variation in VLSI Design,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2004
[Bibtex]

@inproceedings{C12,
author = {Gupta, P. and Heng, F.-L. and Gordon, R.L. and Lai, K. and Lee, J. },
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C12},
keywords = {mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C12_paper.pdf},
title = {Taming {F}ocus {V}ariation in {VLSI} {D}esign},
year = {2004}
}


[C10] P. Gupta, A. B. Kahng, and S. Mantik, “Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling,” in Proc. IEEE/ACM International Conference on VLSI Design, 2004
[Bibtex]

@inproceedings{C10,
author = {Gupta, P. and Kahng, A. B. and Mantik, S.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C2},
keywords = {},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C10_paper.pdf},
title = {Wire {S}wizzling to {R}educe {D}elay {U}ncertainty {D}ue to {C}apacitive {C}oupling},
year = {2004}
}


[C8] P. Gupta, A. B. Kahng, I. I. Mandoiu, and P. Sharma, “Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2003, pp. 754-759
[Bibtex]

@inproceedings{C8,
author = {Gupta, P. and Kahng, A. B. and Mandoiu, I.I. and Sharma, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C8},
keywords = {},
month = {November},
pages = {754-759},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C8_paper.pdf},
title = {Layout-{A}ware {S}can {C}hain {S}ynthesis for {I}mproved {P}ath {D}elay {F}ault {C}overage},
year = {2003}
}


[C9] P. Gupta and A. B. Kahng, “Manufacturing-Aware Physical Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2003, pp. 681-687
[Bibtex]

@inproceedings{C9,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C9},
comments = {embedded tutorial},
keyword = {mad},
month = {November},
pages = {681-687},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C9_paper.pdf},
title = {Manufacturing-{A}ware {P}hysical {D}esign},
year = {2003}
}


[C7] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2003
[Bibtex]

@inproceedings{C7,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C7},
keywords = {sizing, dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C7_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C7_slides.pdf},
title = {A {C}ost-{D}riven {L}ihographic {C}orrection {M}ethodology {B}ased on {O}ff-the-{S}helf {S}izing {T}ools},
year = {2003}
}


[C6] Y. Chen, P. Gupta, and A. B. Kahng, “Performance-Impact Limited Area Fill Synthesis,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2003
[Bibtex]

@inproceedings{C6,
author = {Chen, Y. and Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C6},
keywords = {mad},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C6_paper.pdf},
title = {Performance-{I}mpact {L}imited {A}rea {F}ill {S}ynthesis},
year = {2003}
}


[C4] P. Gupta and A. B. Kahng, “Quantifying Error in Dynamic Power Estimation of CMOS Circuits,” in IEEE International Symposium on Quality Electronic Design, 2003, pp. 273-278
[Bibtex]

@inproceedings{C4,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
category = {C4},
keywords = {},
month = {March},
pages = {273-278},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C4_paper.pdf},
title = {Quantifying {E}rror in {D}ynamic {P}ower {E}stimation of {CMOS} {C}ircuits},
year = {2003}
}


[C5] P. Gupta, A. B. Kahng, and S. Mantik, “A Proposal for Routing-Based Timing-Driven Scan Chain Ordering,” in IEEE International Symposium on Quality Electronic Design, 2003, pp. 339-343
[Bibtex]

@inproceedings{C5,
author = {Gupta, P. and Kahng, A. B. and Mantik, S.},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
category = {C5},
keywords = {},
month = {March},
pages = {339-343},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C5_paper.pdf},
title = {A {P}roposal for {R}outing-{B}ased {T}iming-{D}riven {S}can {C}hain {O}rdering},
year = {2003}
}


[C3] Y. Chen, P. Gupta, and A. B. Kahng, “Performance-Impact Limited Dummy Fill Insertion,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2003, pp. 857-862
[Bibtex]

@inproceedings{C3,
author = {Chen, Y. and Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C3},
keywords = {mad},
month = {February},
pages = {857-862},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C3_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C3_slides.pdf},
title = {Performance-{I}mpact {L}imited {D}ummy {F}ill {I}nsertion},
year = {2003}
}


[C2] P. Gupta, A. B. Kahng, and S. Mantik, “Routing-Aware Scan Chain Ordering,” in Proc. Asia and South Pacific Design Automation Conference, 2003, pp. 857-862
[Bibtex]

@inproceedings{C2,
author = {Gupta, P. and Kahng, A. B. and Mantik, S.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C2},
keywords = {},
month = {January},
pages = {857-862},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C2_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C2_slides.pdf},
title = {Routing-{A}ware {S}can {C}hain {O}rdering},
year = {2003}
}


[C1] Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI,” in IEEE ASIC/SoC Conference, 2002, pp. 411-415
[Bibtex]

@inproceedings{C1,
author = {Cao, Y. and Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{IEEE ASIC/SoC Conference}},
category = {C1},
keywords = {mad},
month = {September},
pages = {411-415},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C1_paper.pdf},
title = {Design {S}ensitivities to {V}ariability: {E}xtrapolation and {A}ssessments in {N}anometer {VLSI}},
year = {2002}
}

---

Invited Papers

[1] M. Niemier, Z. Enciso, M. M. Sharifi, X. S. Hu, I. O’Conner, A. Graening, R. Sharma, P. Gupta, J. Castrillon, J. P. C. Lima, N. Afroze, A. Khan, and J. Ryckaert, “Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers,” in IEEE/ACM Design, Automation and Test in Europe, 2024, p. 10
[Bibtex]

@inproceedings{IP19,
author = {Niemier, Michael and Enciso, Zephan and Sharifi, Mohammed Mehdi and Hu, Xiaobo Sharon and O'Conner, Ian and Graening, Alexander and Sharma, Ravit and Gupta, Puneet and Castrillon, Jeronimo and Lima, J.P.C. and Afroze, Nashrah and Khan, Asif and Ryckaert, Julien},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {},
keywords = {chiplets,wsi},
month = {March},
note = {},
pages = {10},
title = {{Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers}},
year = {2024}
}


[2] S. Li and P. Gupta, “4F optical neural network acceleration: an architecture perspective,” in SPIE 12019, AI and Optical Data Sciences III, 2022
[Bibtex]

@inproceedings{IP18,
author = {Li, Shurui and Gupta, Puneet},
booktitle = {{{SPIE 12019, AI and Optical Data Sciences III}}},
keywords = {photonics},
title = {{4F optical neural network acceleration: an architecture perspective}},
year = {2022}
}


[3] S. Pal, S. S. Iyer, and P. Gupta, “Advanced packaging and heterogeneous integration to reboot computing,” in IEEE International Conference on Rebooting Computing, 2017
[Bibtex]

@inproceedings{IP17,
author = {Pal, Saptadeep and Iyer, Subramanian S. and Gupta, Puneet},
booktitle = {{IEEE International Conference on Rebooting Computing}},
keywords = {wsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP17_paper.pdf},
title = {Advanced Packaging and Heterogeneous Integration to Reboot Computing},
year = {2017}
}


[4] N. Dutt, P. Gupta, A. Nicolau, A. BanaiyanMofrad, M. Gottscho, and M. Shoushtari, “Multi-Layer Memory Resiliency,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2014
[Bibtex]

@inproceedings{IP14,
author = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and BanaiyanMofrad, Abbas and Gottscho, Mark and Shoushtari, Majid},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP14_paper.pdf},
title = {{M}ulti-{L}ayer {M}emory {R}esiliency},
year = {2014}
}


[5] L. Lai and P. Gupta, “Accurate and inexpensive performance monitoring for variability-aware systems,” in Proc. Asia and South Pacific Design Automation Conference, 2014, pp. 467-473
[Bibtex]

@inproceedings{IP13,
author = {Lai, Liangzhen and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {hsi},
month = {Jan},
pages = {467-473},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP13_paper.pdf},
title = {Accurate and inexpensive performance monitoring for variability-aware systems},
year = {2014}
}


[6] S. S., N. Dutt, P. Gupta, A. Nicolau, and V. N., “On-Chip Self-Awareness Using Cyberphysical-Systems-On-Chip (CPSoC),” in ACM International Conference on Hardware/Software Codesign and System Synthesis, 2014
[Bibtex]

@inproceedings{IP15,
author = {Sarma S. and Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and Venkatasubramanian N.},
booktitle = {{ACM International Conference on Hardware/Software Codesign and System Synthesis}},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP15_paper.pdf},
title = {{On-Chip Self-Awareness Using Cyberphysical-Systems-On-Chip (CPSoC)}},
year = {2014}
}


[7] R. S. Ghaida, Y. Badr, and P. Gupta, “Pattern-restricted design at 10nm and beyond,” in Proc. IEEE International Conference on Computer Design, 2014
[Bibtex]

@inproceedings{IP16,
author = { Ghaida, Rani S. and Badr, Yasmine and Gupta, Puneet},
booktitle = {{Proc. IEEE International Conference on Computer Design}},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP16_paper.pdf},
title = {Pattern-restricted design at 10nm and beyond},
year = {2014}
}


[8] R. S. Ghaida and P. Gupta, “Role of design in multiple patterning: technology development, design enablement and process control,” in IEEE/ACM Design, Automation and Test in Europe, 2013
[Bibtex]

@inproceedings{IP11,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/mp_and_design_date13.pdf},
title = {Role of Design in Multiple Patterning: Technology
Development, Design Enablement and Process Control},
year = {2013}
}


[9] J. Henkel, L. Bauer, N. Dutt, P. Gupta, S. Nassif, M. Shafique, M. Tahoori, and N. Wehn, “Reliable on-chip systems in the nano-era: lessons learnt and future trends,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2013, p. 99:1–99:10
[Bibtex]

@inproceedings{IP12,
author = {Henkel, J\"{o}rg and Bauer, Lars and Dutt, Nikil and Gupta, Puneet and Nassif, Sani and Shafique, Muhammad and Tahoori, Mehdi and Wehn, Norbert},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {hsi},
pages = {99:1--99:10},
title = {Reliable on-chip systems in the nano-era: lessons learnt and future trends},
year = {2013}
}


[10] N. Dutt, P. Gupta, A. Nicolau, L. Bathen, and M. Gottscho, “Variability-Aware Memory Management for Nanoscale Computing,” in Proc. Asia and South Pacific Design Automation Conference, 2013
[Bibtex]

@inproceedings{IP10,
author = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and Bathen, Luis and Gottscho, Mark},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {hsi, variability, memory, dram, uno},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP10_paper.pdf},
title = {{V}ariability-{A}ware {M}emory {M}anagement for {N}anoscale {C}omputing},
year = {2013}
}


[11] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,” in Intl. Conf. on IC Design and Technology, 2012
[Bibtex]

@inproceedings{IP9,
author = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},
booktitle = {{Intl. Conf. on IC Design and Technology}},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ip9_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ip9_slides.pdf},
title = {O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction},
year = {2012}
}


[12] P. Gupta and R. Gupta, “Underdesigned and opportunistic computing,” in Proc. Asian Test Symposium, 2011
[Bibtex]

@inproceedings{IP8,
author = {P. Gupta and R. Gupta},
booktitle = {{Proc. Asian Test Symposium}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/uno_ats_v4.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ats_11_v1.pdf},
title = {Underdesigned and Opportunistic Computing},
year = {2011}
}


[13] A. R. Neureuther, J. Rubinstein, M. Miller, Y. K. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T. -J. K. Liu, X. Sun, K. Jeong, P. and Gupta, A. A. Kagalwalla, R. S. Ghaida, and T. -B. Chan, “Collaborative research on emerging technologies and design,” in Proc. SPIE Photomask and Next-Generation Lithography Mask Technology, 2011
[Bibtex]

@inproceedings{IP7,
author = {A.R. Neureuther and J. Rubinstein and M. Miller and K. Yamazoeand E. Chin and C. Levy and L. Wang and N. Xu and C. Spanos and K. Qian and K. Poolla and J. Ghan and A. Subramanian and T.-J. K. Liu and X. Sun and K. Jeong and and P. Gupta and Kagalwalla, Abde Ali and Ghaida, R. S. and T.-B. Chan},
booktitle = {{Proc. SPIE Photomask and Next-Generation Lithography Mask Technology}},
category = {IP7},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/pmj11.pdf},
title = {Collaborative research on emerging technologies and design},
year = {2011}
}


[14] T. -B. Chan, R. S. Ghaida, and P. Gupta, “Electrical Modeling of Lithographic Imperfections,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010 – Embedded Tutorial
[Bibtex]

@inproceedings{IP6,
author = {Chan, T.-B. and Ghaida, R. S. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {IP6},
keywords = {mad},
note = {Embedded Tutorial},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP6_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP6_slides.pdf},
title = {{E}lectrical {M}odeling of {L}ithographic {I}mperfections},
year = {2010}
}


[15] P. Gupta, A. B. Kahng, O. S. Nakagawa, and K. Samadi, “Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing,” in Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf., 2005 – Invited Paper
[Bibtex]

@inproceedings{IP4,
author = {Gupta, P. and Kahng, A. B. and Nakagawa, O.S. and Samadi, K.},
booktitle = {{Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf.}},
category = {IP4},
keywords = {mad},
month = {October},
note = {Invited Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP4_paper.pdf},
title = {Closing the {L}oop in {I}nterconnect {A}nalyses and {O}ptimization: {CMP} {F}ill, {L}ithography and {T}iming},
year = {2005}
}


[16] P. Gupta, A. B. Kahng, and C. -H. Park, “Improving OPC Quality Via Interactions Within the Design-to-Manufacturing Flow,” in SPIE Photomask and NGL Mask Technology, 2005 – Invited Paper
[Bibtex]

@inproceedings{IP3,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H.},
booktitle = {{SPIE Photomask and NGL Mask Technology}},
category = {IP3},
keywords = {dats},
month = {April},
note = {Invited Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP3_paper.pdf},
title = {Improving {OPC} {Q}uality {V}ia {I}nteractions {W}ithin the {D}esign-to-{M}anufacturing {F}low},
year = {2005}
}


[17] P. Gupta, A. B. Kahng, C. -H. Park, P. Sharma, D. Sylvester, and J. Yang, “Joining the Design and Mask Flows for Better and Cheaper Masks,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2004 – Invited Paper
[Bibtex]

@inproceedings{IP2,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Sharma, P. and Sylvester, D. and Yang, J.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
category = {IP2},
keywords = {dats},
month = {September},
note = {Invited Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP2_paper.pdf},
title = {Joining the {D}esign and {M}ask {F}lows for {B}etter and {C}heaper {M}asks},
year = {2004}
}


[18] P. Gupta and A. B. Kahng, “Manufacturing-Aware Physical Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2003 – Embedded Tutorial
[Bibtex]

@inproceedings{IP1b,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {IP1b},
keywords = {mad},
month = {November},
note = {Embedded Tutorial},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP1b_paper.pdf},
title = {Manufacturing-{A}ware {P}hysical {D}esign},
year = {2003}
}


[19] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward Performance-Driven Reduction of the Cost of RET-based Lithography Control,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2003 – Invited Paper
[Bibtex]

@inproceedings{IP1,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {IP1},
keywords = {dats},
month = {February},
note = {Invited Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP1_paper.pdf},
title = {Toward {P}erformance-{D}riven {R}eduction of the {C}ost of {RET}-based {L}ithography {C}ontrol},
year = {2003}
}

---

Books and Book Chapters

[B3] I. Alam, L. Dolecek, and P. Gupta, “Lightweight software-defined error correction for memories,” in Dependable Embedded Systems, Springer, 2020.
[Bibtex]

@incollection{B3,
author = {Alam, Irina and Dolecek, Lara and Gupta, Puneet},
booktitle = {{Dependable Embedded Systems}},
publisher = {Springer},
title = {Lightweight Software-Defined Error Correction for Memories},
year = {2020}
}


[B2] J. Lee and P. Gupta, Discrete circuit optimization: library based gate sizing and threshold voltage assignment, Now Publishers, 2012.
[Bibtex]

@book{B2,
author = {Lee, J. and Gupta, P.},
isbn = {978-1-60198-542-2},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/B2_paper.pdf},
publisher = {Now Publishers},
title = {Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment},
year = {2012}
}


[B1] P. Gupta and E. Papadopoulou, “Yield analysis and optimization,” in The Handbook of Algorithms for VLSI Physical Design Automation, CRC Press, 2010.
[Bibtex]

@incollection{B1,
author = {P. Gupta and E. Papadopoulou},
booktitle = {{The Handbook of Algorithms for VLSI Physical Design Automation}},
publisher = {CRC Press},
title = {Yield Analysis and Optimization},
year = {2010}
}

---

Invited Talks and Tutorials

[ITT32] P. Gupta, “Photonic Fourier Convolutional Neural Network Acceleration,” in IEEE Photonics Conference, 2023
[Bibtex]

@conference{ITT32,
author = {Gupta, Puneet},
booktitle = {{{IEEE Photonics Conference}}},
title = {{Photonic Fourier Convolutional Neural Network Acceleration}},
year = {2023}
}


[IT29] S. Li and P. Gupta, “4F Optical Neural Network Acceleration: An Architectural Perspective,” in SPIE Photonics West Conference (AI and Optical Data Sciences), 2022
[Bibtex]

@conference{IT29,
author = {Li, Shurui and Gupta, Puneet},
booktitle = {{SPIE Photonics West Conference (AI and Optical Data Sciences)}},
keywords = {photonics, optical neural network},
month = {February},
title = {{4F Optical Neural Network Acceleration: An Architectural Perspective}},
year = {2022}
}


[ITT31] P. Gupta, “Software-Defined Memory Error Correction,” in IEEE International Workshop on Silicon Lifecycle Management (SLM), 2022
[Bibtex]

@conference{ITT31,
author = {Gupta, Puneet},
booktitle = {{{IEEE International Workshop on Silicon Lifecycle Management (SLM)}}},
title = {{Software-Defined Memory Error Correction}},
year = {2022}
}


[ITT30] P. Gupta, “Design Technology Co-Optimization for EUV (Keynote Talk),” in IEEE International Workshop on Advanced Patterning Solutions, 2022
[Bibtex]

@conference{ITT30,
author = {Gupta, Puneet},
booktitle = {{IEEE International Workshop on Advanced Patterning Solutions}},
keywords = {dats},
title = {{Design Technology Co-Optimization for EUV (Keynote Talk)}},
year = {2022}
}


[ITT28] P. Gupta, “Pathfinding and Design of Large-Scale Chiplet-Based Systems,” in MEPTEC Road to Chiplets: Architecture Workshop, 2021
[Bibtex]

@conference{ITT28,
author = {Gupta, Puneet},
booktitle = {{{MEPTEC Road to Chiplets: Architecture Workshop}}},
title = {{Pathfinding and Design of Large-Scale Chiplet-Based Systems}},
year = {2021}
}


[ITT27] P. Gupta and J. A. Torres, “Understanding design-patterning interactions for euv and dsa,” in SPIE Advanced Lithography Symposium, 2017 – Short Course
[Bibtex]

@conference{ITT27,
author = {P. Gupta and J.A. Torres},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
note = {Short Course},
title = {Understanding Design-Patterning Interactions for EUV and DSA},
year = {2017}
}


[ITT26] P. Gupta, “Design technology co-optimization for disruptive patterning schemes,” in China Semiconductor Technology International Conference (CSTIC), 2017
[Bibtex]

@conference{ITT26,
author = {P. Gupta},
booktitle = {{China Semiconductor Technology International Conference (CSTIC)}},
keywords = {dats},
title = {Design Technology Co-optimization for Disruptive Patterning Schemes},
year = {2017}
}


[ITT20] P. Gupta and J. A. Torres, “Understanding design-patterning interactions for euv and dsa,” in SPIE Advanced Lithography Symposium, 2016 – Short Course
[Bibtex]

@conference{ITT20,
author = {P. Gupta and J.A. Torres},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
note = {Short Course},
title = {Understanding Design-Patterning Interactions for EUV and DSA},
year = {2016}
}


[ITT24] P. Gupta, “Design-technology co-optimization applications for dsa and euv,” in Lithography Workshop, 2016
[Bibtex]

@conference{ITT24,
author = {P. Gupta},
booktitle = {{Lithography Workshop}},
title = {Design-Technology Co-optimization Applications for DSA and EUV},
year = {2016}
}


[ITT21] P. Gupta, “Advancing cmos usage for high reliability markets,” in International Reliability Physics Symposium, 2016 – Panel Discussion
[Bibtex]

@conference{ITT21,
author = {P. Gupta},
booktitle = {{International Reliability Physics Symposium}},
note = {Panel Discussion},
title = {Advancing CMOS Usage for High Reliability Markets},
year = {2016}
}


[ITT23] P. Gupta, “Cross-layer reliability monitoring, margining and mitigation,” in Design Technology Coupling Workshop, Munich, 2016 – Keynote Speaker
[Bibtex]

@conference{ITT23,
author = {P. Gupta},
booktitle = {{Design Technology Coupling Workshop, Munich}},
note = {Keynote Speaker},
title = {Cross-Layer Reliability Monitoring, Margining and Mitigation},
year = {2016}
}


[ITT19] P. Gupta, A. Mallik, and J. A. Torres, “Patterning beyond multiple patterning,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2015 – Embedded tutorial
[Bibtex]

@conference{ITT19,
author = {P. Gupta and A. Mallik and J.A. Torres},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {dats},
note = {Embedded tutorial},
title = {Patterning beyond multiple patterning},
year = {2015}
}


[ITT18] P. Gupta, A. Mallik, and J. A. Torres, “Design-patterning interactions,” in SPIE Advanced Lithography Symposium, 2013 – Half-Day tutorial.
[Bibtex]

@conference{ITT18,
author = {P. Gupta and A. Mallik and J.A. Torres},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
note = {Half-Day tutorial.},
title = {Design-Patterning Interactions},
year = {2013}
}


[ITT17] R. Puri, N. Charudhattan, S. Saha, S. Rangarajan, R. Rao, and P. Gupta, “Design of deep sub-micron cmos circuit and design methodologies for high performance microprocessors,” in IEEE International Conference on VLSI Design, 2013 – Tutorial
[Bibtex]

@conference{ITT17,
author = {R. Puri and N. Charudhattan and S. Saha and S. Rangarajan and R. Rao and P. Gupta},
booktitle = {{ IEEE International Conference on VLSI Design}},
keywords = {mad},
note = {Tutorial},
title = {Design of Deep Sub-Micron CMOS Circuit and Design Methodologies for High Performance Microprocessors},
year = {2013}
}


[ITT22] M. Shafique, P. Gupta, H. Patel, and S. Garg, “Cross-layer reliability modeling and optimization for embedded systems under process variations,” in Embedded Systems Week (ESWeek), 2013
[Bibtex]

@conference{ITT22,
author = {M. Shafique and P. Gupta and H. Patel and S. Garg},
booktitle = {{Embedded Systems Week (ESWeek)}},
title = {Cross-Layer Reliability Modeling and Optimization for Embedded Systems under Process Variations},
year = {2013}
}


[ITT25] P. Gupta, “Design for nanoscale patterning,” in IEEE Custom Integrated Circuits Conference (CICC), 2013
[Bibtex]

@conference{ITT25,
author = {P. Gupta},
booktitle = {{IEEE Custom Integrated Circuits Conference (CICC)}},
title = {Design for Nanoscale Patterning},
year = {2013}
}


[ITT15] P. Gupta, “Design-assisted semiconductor manufacturing,” in IEEE International Symposium on Quality Electronic Design, 2012 – Short tutorial
[Bibtex]

@conference{ITT15,
author = {Gupta, P.},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
keywords = {mad},
note = {Short tutorial},
title = {Design-Assisted Semiconductor Manufacturing},
year = {2012}
}


[ITT16] P. Gupta, “Measuring and monitoring variability,” in IEEE International On-Line Test Symposium, 2012 – Invited Talk
[Bibtex]

@conference{ITT16,
author = {Gupta, P.},
booktitle = {{IEEE International On-Line Test Symposium}},
keywords = {hsi},
note = {Invited Talk},
title = { Measuring and Monitoring Variability},
year = {2012}
}


[ITT12] P. Gupta, “Underdesigned and opportunistic computing machines,” in Nanosystem Design and Variability Workshop, EPFL, 2011 – Invited Talk
[Bibtex]

@conference{ITT12,
author = {Gupta, P.},
booktitle = {{Nanosystem Design and Variability Workshop, EPFL}},
keywords = {hsi},
note = {Invited Talk},
title = {Underdesigned and Opportunistic Computing Machines},
year = {2011}
}


[ITT13] P. Gupta, “Designing for uncertainty: addressing process variations and aging issues in vlsi designs,” in IEEE International Symposium on VLSI Design, Automation and Test, 2011 – Tutorial
[Bibtex]

@conference{ITT13,
author = {Gupta, P.},
booktitle = {{IEEE International Symposium on VLSI Design, Automation and Test}},
keywords = {mad, hsi},
note = {Tutorial},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/vlsidat_11.pdf},
title = {Designing for Uncertainty: Addressing Process Variations and Aging Issues in VLSI Designs},
year = {2011}
}


[ITT14] P. Gupta, “Variability and reliability: will they get better or worse in future cmos technologies ?,” in IEEE Workshop on Design for Reliability and Variability, 2011 – Panel Discussion
[Bibtex]

@conference{ITT14,
author = {Gupta, P.},
booktitle = {{IEEE Workshop on Design for Reliability and Variability}},
keywords = {mad},
note = {Panel Discussion},
title = { Variability and Reliability: Will they Get Better or Worse in Future CMOS Technologies ?},
year = {2011}
}


[ITT11] P. Gupta, “Modeling performance impact of variability,” in NSF/SRC The International Variability Characterization Workshop, 2010 – Invited Talk
[Bibtex]

@conference{ITT11,
author = {Gupta, P.},
booktitle = {{NSF/SRC The International Variability Characterization Workshop}},
keywords = {mad},
note = {Invited Talk},
title = {Modeling Performance Impact of Variability},
year = {2010}
}


[ITT10] P. Gupta, “Revisiting variation models and their reliability,” in IEEE/ACM Workshop on Variability Modeling and Characterization, 2009 – Invited talk
[Bibtex]

@conference{ITT10,
author = {Gupta, P.},
booktitle = {{IEEE/ACM Workshop on Variability Modeling and Characterization}},
keywords = {mad},
note = {Invited talk},
title = {Revisiting Variation Models and Their Reliability},
year = {2009}
}


[ITT10a] P. Gupta, “Design for ultra-low-k1 patterning and manufacturing,” in IEEE International Conference on Microelectronic Teststructures (ICMTS), 2009 – Tutorial
[Bibtex]

@conference{ITT10a,
author = {Gupta, P.},
booktitle = {{IEEE International Conference on Microelectronic Teststructures (ICMTS)}},
keywords = {mad},
note = {Tutorial},
title = { Design for Ultra-low-k1 Patterning and Manufacturing},
year = {2009}
}


[ITT9] P. Gupta, “Design and Use of Tweakable Devices for Future Logic Implementation,” in IEEE International Electron Devices Meeting, 2008, pp. 1-1 – Invited Talk
[Bibtex]

@conference{ITT9,
author = {Gupta, P.},
booktitle = {{IEEE International Electron Devices Meeting}},
category = {ITT9},
keywords = {},
month = {December},
note = {Invited Talk},
pages = {1-1},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/iedm08.pdf},
title = {Design and {U}se of {T}weakable {D}evices for {F}uture {L}ogic {I}mplementation},
year = {2008}
}


[ITT5] P. Gupta, “The Electrical Design Manufacturing Interface,” in Electronic Design Processes Workshop, 2008
[Bibtex]

@conference{ITT5,
author = {Gupta, P.},
booktitle = {{Electronic Design Processes Workshop}},
category = {ITT5},
keywords = {mad, dats},
title = {The {E}lectrical {D}esign {M}anufacturing {I}nterface},
year = {2008}
}


[ITT6] P. Gupta and C. Wu, “Lithography and Memories: From Shapes to Electrical,” in IEEE VLSI Test Symposium, 2008
[Bibtex]

@conference{ITT6,
author = {Gupta, P. and Wu, C.},
booktitle = {{IEEE VLSI Test Symposium}},
category = {ITT6},
keywords = {mad},
title = {Lithography and {M}emories: {F}rom {S}hapes to {E}lectrical},
year = {2008}
}


[ITT7] D. Chidambarrao, P. Gupta, P. Elakkumanan, L. Liebmann, D. Marculescu, and N. Tamarapalli, “DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2008 – Full-day Tutorial
[Bibtex]

@conference{ITT7,
author = {Chidambarrao, D. and Gupta, P. and Elakkumanan, P. and Liebmann, L. and Marculescu, D. and Tamarapalli, N.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {ITT7},
keywords = {mad},
note = {Full-day Tutorial},
title = {{DFM} {R}evisited: {A} {C}omprehensive {A}nalysis of {V}ariability at all {L}evels of {A}bstraction},
year = {2008}
}


[ITT8] P. Gupta, “Challenges at 45nm and Beyond,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2008 – Panel Discussion
[Bibtex]

@conference{ITT8,
author = {Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {ITT8},
keywords = {mad, dats},
note = {Panel Discussion},
title = {Challenges at 45nm and {B}eyond},
year = {2008}
}


[ITT4] P. Gupta and R. Puri, “Impact of Variability On VLSI Circuits,” in SPIE Advanced Lithography Symposium, 2007 – Short Course
[Bibtex]

@conference{ITT4,
author = {Gupta, P. and Puri, R.},
booktitle = {{SPIE Advanced Lithography Symposium}},
category = {ITT4},
keywords = {mad},
note = {Short Course},
title = {Impact Of {V}ariability {O}n {VLSI} {C}ircuits},
year = {2007}
}


[ITT2] P. Gupta and A. B. Kahng, “CMP and DFM,” in CMP-MIC, 2005 – Short Tutorial
[Bibtex]

@conference{ITT2,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{CMP-MIC}},
category = {ITT2},
keywords = {mad},
note = {Short Tutorial},
title = {{CMP} and {DFM}},
year = {2005}
}


[ITT3] P. Gupta, “DFM Fundamentals,” in WesCon, 2005 – Short Tutorial
[Bibtex]

@conference{ITT3,
author = {Gupta, P.},
booktitle = {{WesCon}},
category = {ITT3},
keywords = {mad},
note = {Short Tutorial},
title = {{DFM} {F}undamentals},
year = {2005}
}

---

Patents

[P18] P. Gupta, A. Pan, and S. Wang, Memory write and read assistance using negative differential resistance devices, 2020.
[Bibtex]

@misc{P18,
author = {P. Gupta and A. Pan and S. Wang},
howpublished = {U.S. Patent No. 10,832,752},
title = {Memory write and read assistance using negative differential resistance devices},
year = {2020}
}


[P17] P. Gupta and R. S. Ghaida, Single-mask double-patterning lithography, 2013.
[Bibtex]

@misc{P17,
author = {P. Gupta and R.S. Ghaida},
howpublished = {U.S. Patent No. 8,415,089},
title = {Single-mask double-patterning lithography},
year = {2013}
}


[P16] A. B. Kahng, P. Gupta, D. Sylvester, and J. Yang, Tool for modifying mask design layout, 2012.
[Bibtex]

@misc{P16,
author = {A.B. Kahng and P. Gupta and D. Sylvester and J. Yang},
howpublished = {U.S. Patent No. 8,103,981},
title = {Tool for modifying mask design layout},
year = {2012}
}


[P14] A. B. Kahng, P. Gupta, and S. Shah, System and method for performing transistor-level static performance analysis using cell-level static analysis tools, 2011.
[Bibtex]

@misc{P14,
author = {A.B. Kahng and P. Gupta and S. Shah},
howpublished = {U.S. Patent No. 7,865,856},
title = {System and method for performing transistor-level static performance analysis using cell-level static analysis tools},
year = {2011}
}


[P15] P. Gupta, A. B. Kahng, P. Sharma, and S. Muddu, Method and system for wafer topography-aware integrated circuit design analysis and optimization, 2011.
[Bibtex]

@misc{P15,
author = {P. Gupta and A.B. Kahng and P. Sharma and S. Muddu},
howpublished = {U.S. Patent No. 8,024,675},
title = {Method and system for wafer topography-aware integrated circuit design analysis and optimization},
year = {2011}
}


[P8] P. Gupta, A. B. Kahng, and S. Shah, Method and system for integrated circuit optimization by using an optimized standard-cell library, 2010.
[Bibtex]

@misc{P8,
author = {Gupta, P. and Kahng, A.B. and Shah, S.},
howpublished = {US Patent No. 7,716,612},
title = {Method and system for integrated circuit optimization by using an optimized standard-cell library },
year = {2010}
}


[P10] P. Gupta and A. B. Kahng, Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit, 2010.
[Bibtex]

@misc{P10,
author = {Gupta, P. and Kahng, A.B.},
howpublished = {US Patent No. 7,743,349},
title = {Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit },
year = {2010}
}


[P9] P. Gupta, A. B. Kahng, and D. Reed, Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objective, 2010.
[Bibtex]

@misc{P9,
author = {Gupta, P. and Kahng, A.B. and Reed, D.},
howpublished = {US Patent No. 7,730,432},
title = {Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objective},
year = {2010}
}


[P13] P. Gupta and A. B. Kahng, Method and system for topography-aware reticle enhancement, 2010.
[Bibtex]

@misc{P13,
author = {P. Gupta and A.B. Kahng},
howpublished = {U.S. Patent No. 7,814,456},
title = {Method and system for topography-aware reticle enhancement },
year = {2010}
}


[P12] C. W. Moon, P. Gupta, P. J. Donehue, and A. B. Kahng, Method of designing a digital circuit by correlating different static timing analyzers, 2010.
[Bibtex]

@misc{P12,
author = {C.W. Moon and P. Gupta and P.J. Donehue and A.B. Kahng},
howpublished = {U.S. Patent No. 7,823,098},
title = {Method of designing a digital circuit by correlating different static timing analyzers},
year = {2010}
}


[P11] O. S. Nakagawa, A. B. Kahng, P. Wong, and P. Gupta, Arrangement of fill unit elements in an integrated circuit interconnect layer, 2010.
[Bibtex]

@misc{P11,
author = {O. S. Nakagawa and A.B. Kahng and P. Wong and P. Gupta},
howpublished = {U.S. Patent No. 7,745,239},
title = {Arrangement of fill unit elements in an integrated circuit interconnect layer},
year = {2010}
}


[P5] P. Gupta and A. B. Kahng, System and method for varying the starting conditions for a resolution enhancement program to improve the probability that design goals will be met, 2009.
[Bibtex]

@misc{P5,
author = {Gupta, P. and Kahng, A.B.},
category = {P5},
howpublished = {US Patent No. 7,627,849},
title = {System and method for varying the starting conditions for a resolution enhancement program to improve the probability that design goals will be met},
year = {2009}
}


[P6] P. Gupta, A. B. Kahng, and P. C.-H., Method and system for placing layout objects in a standard-cell layout, 2009.
[Bibtex]

@misc{P6,
author = {Gupta, P. and Kahng, A.B. and Park C.-H.},
category = {P6},
howpublished = {US Patent No. 7,640,522},
title = {Method and system for placing layout objects in a standard-cell layout},
year = {2009}
}


[P7] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, Method for correcting a mask design layout, 2009.
[Bibtex]

@misc{P7,
author = {Gupta, P. and Kahng, A.B. and Sylvester, D. and Yang, J.},
category = {P7},
howpublished = {US Patent No. 7,614,032},
title = {Method for correcting a mask design layout},
year = {2009}
}


[P3] P. Gupta, F. -L. Heng, and M. Lavin, Method of IC Fabrication, IC Mask Fabrication and Program Product, 2008.
[Bibtex]

@misc{P3,
author = {Gupta, P. and Heng, F.-L. and Lavin, M.},
category = {P3},
howpublished = {US Patent No. 7,353,492},
title = {Method of {IC} {F}abrication, {IC} {M}ask {F}abrication and {P}rogram {P}roduct},
year = {2008}
}


[P4] P. Gupta and A. B. Kahng, Gate-Length Biasing for Digital Circuit Optimization, 2008.
[Bibtex]

@misc{P4,
author = {Gupta, P. and Kahng, A.B.},
category = {P4},
howpublished = {US Patent No. 7,441,211},
title = {Gate-{L}ength {B}iasing for {D}igital {C}ircuit {O}ptimization},
year = {2008}
}


[P2] P. Gupta, F. -L. Heng, D. S. Kung, and D. Ostapko, Integrated Circuit Logic with Self Compensating Block Delays, 2006.
[Bibtex]

@misc{P2,
author = {Gupta, P. and Heng, F.-L. and Kung, D.S. and Ostapko, D.},
category = {P2},
howpublished = {US Patent No. 7,084,476},
title = {Integrated {C}ircuit {L}ogic with {S}elf {C}ompensating {B}lock {D}elays},
year = {2006}
}


[P1] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, Method for Correcting a Mask Design Layout, 2006.
[Bibtex]

@misc{P1,
author = {Gupta, P. and Kahng, A.B. and Sylvester, D. and Yang, J.},
category = {P1},
howpublished = {US Patent No. 7,149,999},
title = {Method for {C}orrecting a {M}ask {D}esign {L}ayout},
year = {2006}
}

---

Workshops (No Published Proceedings)

[W27] H. Yang, N. Pesericoa, S. Li, B. F. Motlagh, J. S. Virdi, P. Gupta, V. J. Sorger, and C. W. Wong, “Enhancing and up-scaling of integrated photonic 4F convolution neural networks,” in Smart Photonic and Optoelectronic Integrated Circuits 2024, 2024, p. 1289003
[Bibtex]

@conference{W27,
author = {Hangbo Yang and Nicola Pesericoa and Shurui Li and Benyamin Fallahi Motlagh and Jaskirat Singh Virdi and Puneet Gupta and Volker J. Sorger and Chee Wei Wong},
booktitle = {{Smart Photonic and Optoelectronic Integrated Circuits 2024}},
doi = {10.1117/12.2692958},
editor = {Sailing He and Laurent Vivien},
keywords = {Machine Learning, Convolution Neural Network, Integrated Photonics},
organization = {International Society for Optics and Photonics},
pages = {1289003},
publisher = {SPIE},
title = {{Enhancing and up-scaling of integrated photonic 4F convolution neural networks}},
url = {https://doi.org/10.1117/12.2692958},
volume = {12890},
year = {2024}
}


[W23] T. Li, W. Romaszkan, S. Pal, S. Pamarti, and P. Gupta, “REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration,” in Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech), 2023
[Bibtex]

@conference{W23,
author = {Li, Tianmu and Romaszkan, Wojciech and Pal, Soumitra and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, CNN, neural networks},
title = {{REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration}},
year = {2023}
}


[W22] J. Yang, W. Romaszkan, A. Graening, V. K. Jacob, T. Li, P. Gupta, and S. Pamarti, “A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications,” in Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech), 2023
[Bibtex]

@conference{W22,
author = {Yang, Jiyue and Romaszkan, Wojciech and Graening, Alexander and Jacob, Vinod Kurian and Li, Tianmu and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, event-based camera, accelerator},
title = {{A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications}},
year = {2023}
}


[W21] A. Graening, W. Romaszkan, S. Pamarti, and P. Gupta, “Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing,” in Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech), 2022
[Bibtex]

@conference{W21,
author = {Graening, Alexander and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, event-based camera, accelerator},
title = {{Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing}},
year = {2022}
}


[W25] J. Yang, T. Li, W. Romaszkan, P. Gupta, and S. Pamarti, “A 1.84-7.96TOPS/W 65nm DAC/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply,” in Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech), 2022
[Bibtex]

@conference{W25,
author = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, CNN, neural networks, accelerator},
title = {{A 1.84-7.96TOPS/W 65nm DAC/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply}},
year = {2022}
}


[W18] M. Miscuglio, Z. Hu, S. Li, J. K. George, R. Capanna, H. Dalir, P. M. Bardet, P. Gupta, and V. J. Sorger, “Massively-parallel Amplitude-only Fourier Optical Convolutional Neural Network,” in Conference on Lasers and Electro-Optics (CLEO), 2021
[Bibtex]

@conference{W18,
author = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and George, Jonathan K. and Capanna, Roberto and Dalir, Hamed and Bardet, Philippe M. and Gupta, Puneet and Sorger, Volker J.},
booktitle = {{Conference on Lasers and Electro-Optics (CLEO)}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://ieeexplore.ieee.org/abstract/document/9572872},
title = {{Massively-parallel Amplitude-only Fourier Optical Convolutional Neural Network}},
year = {2021}
}


[W24] W. Romaszkan, T. Li, J. Yang, A. Lee, D. Wu, K. Wang, S. Pamarti, and P. Gupta, “Machine Learning at the Edge Using Spintronic Stochastic Computing,” in Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech), 2021
[Bibtex]

@conference{W24,
author = {Romaszkan, Wojciech and Li, Tianmu and Yang, Jiyue and Lee, Albert and Wu, Di and Wang, Kang and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, CNN, neural networks},
title = {{Machine Learning at the Edge Using Spintronic Stochastic Computing}},
year = {2021}
}


[W20] Z. Hu, M. Solyanik-Gorgone, S. Li, P. Gupta, and V. J. Sorger, “High Throughput Multi-kernel Fourier Optic Classifier,” in Frontiers in Optics, 2021
[Bibtex]

@conference{W20,
author = {Hu, Zibo and Solyanik-Gorgone, Maria and Li, Shurui and Gupta, Puneet and Sorger, Volker J.},
booktitle = {{Frontiers in Optics}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://opg.optica.org/abstract.cfm?uri=fio-2021-FTh4C.5},
title = {{High Throughput Multi-kernel Fourier Optic Classifier}},
year = {2021}
}


[W19] M. Miscuglio, Z. Hu, S. Li, P. Gupta, H. Dalir, and V. J. Sorger, “Fourier Optical Convolutional Neural Network Accelerator,” in Signal Processing in Photonic Communications, 2021
[Bibtex]

@conference{W19,
author = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and Gupta, Puneet and Dalir, Hamed and Sorger, Volker J.},
booktitle = {{Signal Processing in Photonic Communications}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://opg.optica.org/abstract.cfm?uri=SPPCom-2021-SpM5C.2},
title = {{Fourier Optical Convolutional Neural Network Accelerator}},
year = {2021}
}


[W17] Z. Hu, M. Miscuglio, S. Li, J. K. George, P. Gupta, and V. J. Sorger, “Electro-Optical Hybrid Fouirer Neural Network with Amplitude-Only Modulation,” in Frontiers in Optics, 2020
[Bibtex]

@conference{W17,
author = {Hu, Zibo and Miscuglio, Mario and Li, Shurui and George, Jonathan K. and Gupta, Puneet and Sorger, Volker J.},
booktitle = {{Frontiers in Optics}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://opg.optica.org/abstract.cfm?uri=FiO-2020-FM7D.3},
title = {{Electro-Optical Hybrid Fouirer Neural Network with Amplitude-Only Modulation}},
year = {2020}
}


[W16] M. Miscuglio, Z. Hu, S. Li, J. Gu, A. Babakhani, P. Gupta, C. Wong, D. Pan, S. Bank, H. Dalir, and V. J. Sorger, “Million-channel Parallelism Fourier-optic Convolutional Filter and Neural Network Processor,” in CLEO: Applications and Technology, 2020
[Bibtex]

@conference{W16,
author = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and Gu, Jiaqi and Babakhani, Aydin and Gupta, Puneet and Wong, Chee-Wei and Pan, David and Bank, Seth and Dalir, Hamed and Sorger, Volker J.},
booktitle = {{CLEO: Applications and Technology}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://opg.optica.org/abstract.cfm?uri=cleo_at-2020-JF3A.4},
title = {{Million-channel Parallelism Fourier-optic Convolutional Filter and Neural Network Processor}},
year = {2020}
}


[W15] I. Alam, S. Pal, and P. Gupta, “Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories,” in IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), 2018
[Bibtex]

@conference{W15,
author = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {memres,compression,ecc,memory,reliability,architecture,coding,systems,stt_ram},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W15_paper.pdf},
title = {{Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},
year = {2018}
}


[W14] I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, “Parity++: Lightweight Error Correction for Last Level Caches,” in IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), 2018 – Best of SELSE
[Bibtex]

@conference{W14,
author = {Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {memres,parity,ecc,memory,reliability,architecture,coding,systems,caches},
note = {Best of SELSE},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W14_paper.pdf},
title = {{Parity++: Lightweight Error Correction for Last Level Caches}},
year = {2018}
}


[W13] M. Gottscho, C. Schoeny, L. Dolecek, and P. Gupta, “Software-Defined Error-Correcting Codes,” in IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), 2016 – Best Paper Award
[Bibtex]

@conference{W13,
author = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {memres,hsi,ecc,memory,reliability,architecture,coding,systems,dram,caches},
note = {Best Paper Award},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_slides.pptx},
title = {{Software-Defined Error-Correcting Codes}},
year = {2016}
}


[W12] S. Wang, H. Hu, H. Zheng, and P. Gupta, “MEMRES: A Fast Memory System Reliability Simulator,” in IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), 2015
[Bibtex]

@conference{W12,
author = {Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {hsi, MEMRES, memory faults},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W12_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W12_slides.pptx},
title = {{MEMRES: A Fast Memory System Reliability Simulator}},
year = {2015}
}


[W11] R. S. Ghaida, M. Gupta, and P. Gupta, “A framework for exploring the interaction between design rules and overlay control,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2012
[Bibtex]

@conference{W11,
author = {Ghaida, R. S. and Gupta, M. and Gupta, P.},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W11},
keywords = {dats, dre, design rules, overlay, alignment, process, multiple-patterning, lithography},
title = {A Framework for Exploring the Interaction Between Design Rules and Overlay Control},
year = {2012}
}


[W10] J. Lee and P. Gupta, “Parametric hierarchy recovery for layout extracted netlists,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2011
[Bibtex]

@conference{W10,
author = {Lee, John and Gupta, Puneet},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W10},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W10_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W10_slides.pdf},
title = {Parametric Hierarchy Recovery for Layout Extracted Netlists},
year = {2011}
}


[W6] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware Mask Inspection,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010
[Bibtex]

@conference{W6,
author = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W6},
keywords = {dats},
title = {{D}esign-aware {M}ask {I}nspection},
year = {2010}
}


[W8] V. Popuri, P. Gupta, and S. Pamarti, “Bias-Driven Robust Analog Circuit Sizing Scheme,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010
[Bibtex]

@conference{W8,
author = {Popuri, V. and Gupta, P. and Pamarti, S.},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W8},
keywords = {dats},
title = {{Bias-Driven Robust Analog Circuit Sizing Scheme}},
year = {2010}
}


[W7] J. Lee and P. Gupta, “Incremental gate sizing for late process changes,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010
[Bibtex]

@conference{W7,
author = {Lee, John and Gupta, Puneet},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W7},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W7_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W7_slides.pdf},
title = {Incremental Gate Sizing for Late Process Changes},
year = {2010}
}


[W9] T. -B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring,” in SRC TECHCON’10, 2010
[Bibtex]

@conference{W9,
author = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
booktitle = {{SRC TECHCON'10}},
category = {W9},
keywords = {stat},
title = {{D}esign {Dependent} {P}rocess {M}onitoring},
year = {2010}
}


[W5] L. Cheng and P. Gupta, “A Levelized Variation Modeling Scheme,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010
[Bibtex]

@conference{W5,
author = {Cheng, L. and Gupta, Puneet},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W5},
keywords = {stat},
title = {{A Levelized Variation Modeling Scheme}},
year = {2010}
}


[W4] T. -B. Chan, P. Gupta, V. Balakrishnan, and Y. Cao, “Extended Burn-in for Reduced Vth Variation,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2009
[Bibtex]

@conference{W4,
author = {Chan, T.-B. and Gupta, Puneet and Balakrishnan, Varsha and Cao, Yu},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W4},
keywords = {dats},
title = {{E}xtended {B}urn-in for {R}educed {V}th {V}ariation},
year = {2009}
}


[W3] J. Sartori, A. Pant, P. Gupta, and R. Kumar, “On Performance Binning of Multicore Processors,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2009
[Bibtex]

@conference{W3,
author = {Sartori, John and Pant, Aashish and Gupta, Puneet and Kumar, Rakesh},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W3},
keywords = {hsi-p2},
title = {{O}n {P}erformance {B}inning of {M}ulticore {P}rocessors},
year = {2009}
}


[W2] A. Pant, P. Gupta, and M. van der Schaar, “Software Adaptation to Handle Manufacturing Variability and Relax Hardware Overdesign,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2009
[Bibtex]

@conference{W2,
author = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W2},
keywords = {hsi-p1},
title = {{S}oftware {A}daptation to {H}andle {M}anufacturing {Variability} and {R}elax {H}ardware {O}verdesign},
year = {2009}
}


[W1] R. S. Ghaida and P. Gupta, “A Framework for Systematic Evaluation and Exploration of Design Rules,” in SRC TECHCON’09, 2009
[Bibtex]

@conference{W1,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{SRC TECHCON'09}},
category = {W1},
keywords = {dats},
month = {},
pages = {},
title = {A {F}ramework for {S}ystematic {E}valuation and {E}xploration of {D}esign {R}ules},
year = {2009}
}