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Mission Statement

Work in NanoCAD targets equivalent scaling improvements – perhaps as much as one full technology generation by establishing new synergies between various silos of application, architecture, design and manufacturing.

Recent Publications

    [PDF] S. Li, H. Yang, C. W. Wong, V. J. Sorger, and P. Gupta, “PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator,” in IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023, p. 12
    [PDF] J. Yang, Li Tianmu, W. Romaszkan, P. Gupta, and S. Pamarti, “A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor,” in IEEE Asian Solid-State Circuits Conference, 2022, p. 2
    [PDF] W. Romaszkan, T. Li, and P. Gupta, “SASCHA – Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,” in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022, p. 12 – Best paper nomination
    [PDF] [PP Slides] S. Li and P. Gupta, “Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors,” in Conference on Machine Learning and Systems (MLSys), 2022, p. 10


A lot of press coverage for our recent DAC paper on design of chiplet-based waferscale processors: HPCWire, EENewsEurope, Tom’s Hardware.

Prof. Gupta is elevated to IEEE Fellow.

Prof. Gupta, Prof. Ken Yang and Prof. Pamarti are awarded a new grant under DARPA LTLT project to investigate architectures and design methodologies for ultra-efficient low temperature (77K) processing.

Congratulations to Saptadeep Pal for defending his thesis on “Scale-out Packageless Processing”. Dr Pal is onto much greener pastures at a stealth mode startup.

Congratulations to Irina Alam for defending her thesis. You can find her excellent thesis on “Lightweight Opportunistic Memory Resilience” here . She joins the Apple memory team.

Congratulations to Tianmu and his collaborator, Jiyue Yang from Professor Pamarti’s group for winning this years Qualcomm Innovation Fellowship, for their project “A Stochastic Compute-In-Memory Neural Network Accelerator with Variable Precision Tuning”. Some of the related papers are here and here.


Congratulations to Wojciech Romaszkan and Tianmu Li for being nominated for best paper award at DATE 2020. The ACOUSTIC paper can be found here: [PDF]

The 3PXNet library for sparse-binarized neural network training and inference has been published on Github. More details about 3PXNet can be found in this paper: [PDF]


Prof. Gupta’s article “Goodbye, Motherboard. Hello, Silicon-Interconnect Fabric” appears in IEEE Spectrum. It discusses the emerging chiplet revolution and possibility of packageless processing.

NanoCAD lab gets a new ONR contract on photonic neural networks. This is a joint project with UT Austin and GWU. Our focus is to investigate viable architectures and network training approaches accounting for limitations of optics.

Congratulations to Saptadeep for winning the Qualcomm Innovation Fellowship, 2019! He was among the only 13 teams nation-wide to win this (acceptance rate of 11%). The winning proposal was on Revolutionizing Large-Scale Graph Processing Using Waferscale Architecture. This work is still ongoing, so we cant point you to the stellar paper that would come out of it. But a related paper is here: [PDF].

Congratulations to Saptadeep for being awarded the best talk (“Waferscale GPUs”) at the ECE Department Annual Research Review.

Congratulations to Saptadeep, Tianmu and Wojciech for making it into Qualcomm Innovation Fellowship Finals!

Our HPCA paper on waferscale processors is getting a lot of press coverage. It was covered in ExtremeTech, IEEE Spectrum, Hexus, TechXplore, etc. The paper is here: [PDF] .


Prof. Gupta along with Professors Sudhakar Pamarti and Kang Wang win a $5.9M grant from DARPA for Spin-based stochastic dataflow computing. Some of the background work appeared in our group’s papers on NDR-assisted MRAM read/write [PDF] , CMOS NDR [PDF] and spin-based stochastic computing [PDF].

Congratulations to Irina for being awarded the Outstanding M.S. Thesis Award in the ECE department at UCLA.
Congratulations to Irina for best paper award at the SELSE workshop on Parity++: Lightweight Error Correction for Last Level Caches [PDF]. The paper develops a software-informed unequal message protection ECC technique which can correct 80+% of single bit errors with just one additional bit overhead than simple parity. The paper would appear the DSN proceedings later this year.

Congratulations to Tianmu for being selected at a finalist for 2018 Qualcomm Innovation Fellowship for their very interesting proposal on Edge Node Deep Learning.

NanoCAD Group moves to its new lab location 53-135 EIV.


Our HPCA paper [PDF], making a case for packageless processors, gets coverage in Semiconductor Engineering magazine here.

Prof. Gupta’s invited talk on packageless computing [PDF] systems at International Conference on Rebooting Computing gets covered on IEEE Spectrum website and magazine. See the coverage here.

Congratulations to Irina and Mark for the Best Paper Award CASES at Embedded Systems Week on their paper on lightweight fault tolerance for embedded systems at the edge of the Internet-of-Things [PDF].

Prof. Gupta is the inaugral Vice-Chair of the new Computer Engineering degree program at UCLA. Here is a blurb about the new major in Daily Bruin.

Congratulations to Mark and Shaodi for defending their respective Ph.D. dissertations! Dr. Gottscho will head to Google while Dr. Wang will head back to China to found a hardware machine learning startup.

The VC-MTJ and NDR based Stochastic Computing Paper gets the Best Paper Nomination at DATE 2017 [PDF]. Congratulations to Shaodi, Saptadeep and Tianmu.


Congratulations to Mark for getting the Dissertation Year Fellowship at UCLA.

Congratulations, Mark for winning the Qualcomm Innovation Fellowship! The team of Mark Gottscho and Clayton Schoeny was one of the only 8 teams in the US to be selected (6% acceptance). Details of the winning teams are here. Read about the award on the department website and in the Daily Bruin campus newspaper.

Congratulations to Mark for being one of the finalists for the Qualcomm Innovation Fellowship for his radical new proposal for Software-Defined ECC. It was also presented at the 2016 SELSE Workshop, where the work was selected as a Best of SELSE paper [PDF]. It will re-appear in a special session at DSN 2016 .


Congratulations to Liangzhen Lai for defending his dissertation! Dr. Liangzhen Lai joins ARM Research.

Congratulations to Abde Ali for receiving the Outstanding Dissertation in Circuits and Embedded Systems Award.


Congratulations to Abde Ali for defending his thesis! Dr. Abde Ali Kagalwalla joins Intel.

Congratulations to Mark for receiving the Outstanding M.S. Award in Circuits and Embedded Systems in the department!


Congratulations to Mukul (joining Qualcomm) and Ankur (joining Iowa State University) for completing their M.S.

The VamV paper gets the best interactive presentation award at DATE. See the paper here.

Congratulations to Dr. Rani Ghaida has been selected to receive the 2012 Outstanding Dissertation Award in the area of “New directions in physical design, design for manufacturing and CAD for analogue circuits and MEMS” from the European Design and Automation Association (EDAA) for his dissertation “Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies.” [PDF].

Congratulations to Dr. Rani Ghaida for allowance of patent application “Single Mask Double Patterning” [PDF].


Congratulations to Dr. Rani Ghaida for defending his Ph.D thesis! Rani joins Global Foundries soon.
Congratulations to Dr. John Lee for defending his Ph.D. thesis! He joins KPMG as a data scientist.
Prof. Gupta has been selected to receive 2012 IBM Faculty Award.
Congratulations to Tanaya and Chia-Hao for their jobs at Intel and Marvell respectively.


Gate-length biasing – a design-aware manufacturing technique co-invented by Prof. Gupta reaches the Trillion Watt Hour energy saving mark. See the press release here. This [PDF] and this paper [PDF] formed the basis of the company Blaze DFM, that Prof. Gupta co-founded.

SRC issued a press release on the recent “Design-Dependent Process Monitoring” work in Nano CAD Lab. See the press release here. Read the related ICCAD 2010 paper here [PDF].

Prof. Gupta gives a half-day tutorial on “Designing for uncertainty: Addressing process variations and aging issues in VLSI designs”, at the IEEE International Symposium on VLSI Design, Automation and Test in Hsinchu, Taiwan. See the slides here.

Congratulations and best of luck to Santiago and Parag for their new jobs at Altera.


UCLA is part of the team winning one of the NSF Expeditions in Computing! See here. Work done in Nano CAD Lab was the primary driver behind the expedition. See the press release here.

Prof. Puneet Gupta receives 2010 SRC Inventor Recognition Award for patent application titled “Single-Mask Double-Patterning Lithography”.

Best of luck to Aashish at Mentor Graphics, Amarnath at Intel and Lerong at Sandisk in their new jobs.

Prof. Puneet Gupta receives 2010 ACM/SIGDA Outstanding New Faculty Award. The award was given at DAC 2010 opening ceremony.

Congratulations to Aashish Pant for getting Outstanding M.S. Award from EE Department.

Congratulations to Lerong Cheng for defending his Ph.D. thesis!


Prof. Puneet Gupta receives 2009 SRC Inventor Recognition Award for the US Patent titled “Method for correcting a mask layout” (number 7,149,999).

Prof. Puneet Gupta has been awarded 2009 NSF Faculty Early Career Development (CAREER) Award for his proposal titled “CAREER: Co-optimization of Integrated Circuit Design and Manufacturing”. See NSF website for further details.

NanoCAD Lab settles in its home at 53-109 Engr. IV! The lab furniture is here. Welcome everyone!