Thesis and Project Reports

Ph.D. Theses

[1] S. Pal, “Scale-out packageless processing,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021.
[Bibtex]

@phdthesis{PHDTH11,
author = {Pal, Saptadeep},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {},
month = {November},
title = {Scale-Out Packageless Processing},
year = {2021}
}


[2] I. Alam, “Lightweight opportunistic memory resilience,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021.
[Bibtex]

@phdthesis{PHDTH10,
author = {Alam, Irina},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {},
month = {August},
title = {Lightweight Opportunistic Memory Resilience},
year = {2021}
}


[3] W. Wang, “Hardware-enabled design for security (dfs) solutions,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2018.
[Bibtex]

@phdthesis{PHDTH9,
author = {Wang, Wei-Che},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH8_paper.pdf},
title = {Hardware-Enabled Design for Security (DFS) Solutions},
year = {2018}
}


[4] S. Wang, “Design, evaluation and co-optimization of emerging devices and circuits,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.
[Bibtex]

@phdthesis{PHDTH6,
author = {Wang, Shaodi},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {emerging technology, emerging device, emerging memory, MRAM, TFET, negative differential resistance, optimization, evaluation, stochastic computing, non-volatile memory, memory reliability},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH6_paper.pdf},
title = {Design, Evaluation and Co-optimization of Emerging Devices and Circuits},
year = {2017}
}


[5] M. W. Gottscho, “Opportunistic memory systems in presence of hardware variability,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.
[Bibtex]

@phdthesis{PHDTH7,
author = {Gottscho, Mark William},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {computer architecture, memory systems, variation-aware, hardware/software interface, reliability, error-correcting codes, caches, scratchpads, SRAM, DRAM, supercomputers, IoT, embedded systems, electronic design auomation, CAD, EDA, operating systems, Linux, tools, benchmarks, resiliency, approximate computing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH7_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH7_slides.pdf},
title = {Opportunistic Memory Systems in Presence of Hardware Variability},
year = {2017}
}


[6] Y. Badr, “Co-optimization of restrictive patterning technologies and design,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.
[Bibtex]

@phdthesis{PHDTH8,
author = {Badr, Yasmine},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH8_paper.pdf},
title = {Co-optimization of Restrictive Patterning Technologies and Design},
year = {2017}
}


[7] L. Lai, “Cross-layer approaches for monitoring, margining and mitigation of circuit variability,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2015.
[Bibtex]

@phdthesis{PHDTH5,
author = {Lai, Liangzhen},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH5_paper.pdf},
title = {Cross-Layer Approaches for Monitoring, Margining and Mitigation of Circuit Variability},
year = {2015}
}


[8] A. A. Kagalwalla, “Computational methods for design-assisted mask flows,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2014.
[Bibtex]

@phdthesis{PHDTH4,
author = {Kagalwalla, Abde Ali},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH4_paper.pdf},
title = {Computational Methods for Design-Assisted Mask Flows},
year = {2014}
}


[9] J. Lee, “Implications of modern semiconductor technologies on gate sizing,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012.
[Bibtex]

@phdthesis{PHDTH2,
author = {Lee, John},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH2_paper.pdf},
title = {Implications of Modern Semiconductor Technologies on Gate Sizing},
year = {2012}
}


[10] R. S. Ghaida, “Design enablement and design-centric assessment of future semiconductor technologies,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012.
[Bibtex]

@phdthesis{PHDTH3,
author = {Ghaida, R. S.},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH3_paper.pdf},
title = {Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies},
year = {2012}
}


[11] L. Cheng, “Statistical analysis and optimization for timing and power of vlsi circuits,” PhD Thesis, 2010.
[Bibtex]

@phdthesis{PHDTH1,
author = {Cheng, Lerong},
category = {PT1},
keywords = {stat},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH1_paper.pdf},
school = {Department of Electrical Engineering, University of California Los Angeles },
title = {Statistical Analysis and Optimization for Timing and Power of VLSI Circuits},
year = {2010}
}

---

M.S. Theses/Reports

[1] Y. Wu, “Pin assignment for 2.5d dielet assembly,” Department of Electrical and Computer Engineering, University of California Los Angeles 2019.
[Bibtex]

@techreport{MSTH6,
author = {Wu, Yizhang},
institution = {Department of Electrical and Computer Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH6_paper.pdf},
title = {Pin Assignment for 2.5D Dielet Assembly},
year = {2019}
}


[2] I. Alam, “Lightweight fault tolerance in sram based on-chip memories,” Department of Electrical and Computer Engineering, University of California Los Angeles 2018.
[Bibtex]

@techreport{MSTH4,
author = {Alam, Irina},
institution = {Department of Electrical and Computer Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH4_paper.pdf},
title = {Lightweight Fault Tolerance in SRAM Based On-Chip Memories},
year = {2018}
}


[3] Y. Chae, “Defect avoidance for extreme ultraviolet mask defects using intentional pattern deformation,” Department of Electrical and Computer Engineering, University of California Los Angeles 2018.
[Bibtex]

@techreport{MSTH5,
author = {Chae, Yoo-Jin},
institution = {Department of Electrical and Computer Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH5_paper.pdf},
title = {Defect Avoidance for Extreme Ultraviolet Mask Defects using Intentional Pattern Deformation},
year = {2018}
}


[4] V. Dokania, “Intrusive routing for improved standard cell pin access,” Department of Electrical Engineering, University of California Los Angeles 2017.
[Bibtex]

@techreport{MSTR12,
author = {Dokania, Vishesh },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR12_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR12_slides.pdf},
title = {Intrusive Routing for Improved Standard Cell Pin Access},
year = {2017}
}


[5] S. Pal, “Supervia: relieving routing congestion using double-height vias,” Department of Electrical Engineering, University of California Los Angeles 2017.
[Bibtex]

@techreport{MSTR13,
author = {Pal, Saptadeep},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR13_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR13_slides.pdf},
title = {Supervia: Relieving Routing Congestion using Double-height Vias},
year = {2017}
}


[6] N. Lyu, “Leon3 processor variability emulator for delay variability impact on performance,” Department of Electrical Engineering, University of California Los Angeles 2016.
[Bibtex]

@techreport{MSTR11,
author = {Lyu, Nan},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR11_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR11_slides.pdf},
title = {Leon3 Processor Variability Emulator for Delay Variability Impact on Performance},
year = {2016}
}


[7] Y. Agarwal, A. Bishop, T. Chan, M. Fotjik, P. Gupta, A. Kahng, L. Lai, P. Martin, M. Srivastava, D. Sylvester, L. Wanner, and B. Zhang, “Redcooper: hardware sensor enabled variability software testbed for lifetime energy constrained application,” 2014.
[Bibtex]

@techreport{TECHRP1,
author = {Agarwal, Yuvraj and Bishop, Alex and Chan, Tuck-Boon and Fotjik, Matt and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen and Martin, Paul and Srivastava, Mani and Sylvester, Dennis and Wanner, Lucas and Zhang, Bing},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/1c21g217},
title = {Redcooper: Hardware sensor enabled variability software testbed for lifetime energy constrained application},
year = {2014}
}


[8] A. Bhatia, “Varleon: fpga based processor variability emulator for variation aware software,” Department of Electrical Engineering, University of California Los Angeles 2014.
[Bibtex]

@techreport{MSTR9,
author = {Bhatia, Abishek},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR9_paper.pdf},
title = {VarLEON: FPGA Based Processor Variability Emulator for Variation Aware Software},
year = {2014}
}


[9] L. Lai and P. Gupta, “A case study of logic delay fault behaviors on general-purpose embedded processor under voltage overscaling,” 2014.
[Bibtex]

@techreport{TECHRP3,
author = {Lai, Liangzhen and Gupta, Puneet},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/3967v8hw},
title = {A Case Study of Logic Delay Fault Behaviors on General-Purpose Embedded Processor Under Voltage Overscaling},
year = {2014}
}


[10] M. Gottscho, “ViPZonE: Exploiting DRAM Power Variability for Energy Savings in Linux x86-64,” Department of Electrical Engineering, University of California Los Angeles 2014.
[Bibtex]

@techreport{MSTR10,
author = {Gottscho, Mark},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR10_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR10_slides.pdf},
title = {{V}i{P}{Z}on{E}: {E}xploiting {DRAM} {P}ower {V}ariability for {E}nergy {S}avings in {L}inux x86-64},
year = {2014}
}


[11] L. Lai, C. Chang, and P. Gupta, “Exploring total power saving from high temperature of server operations,” 2014.
[Bibtex]

@techreport{TECHRP2,
author = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/5898p020},
title = {Exploring Total Power Saving from High Temperature of Server Operations},
year = {2014}
}


[12] A. Sharma, “Understanding software application behaviour in presence of permanent and intermittent hardware faults,” Department of Electrical Engineering, University of California Los Angeles 2013.
[Bibtex]

@techreport{MSTH3,
author = {Sharma, Ankur},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH3_paper.pdf},
title = {Understanding Software Application Behaviour in Presence of Permanent and Intermittent Hardware Faults},
year = {2013}
}


[13] J. Dong, “High Level Battery Modeling Considering Discharge Rate and Temperature Effects,” Department of Electrical Engineering, University of California Los Angeles 2012.
[Bibtex]

@techreport{MSTR7,
author = {Dong, Jingyuan},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR7_paper.pdf},
title = {{High Level Battery Modeling Considering Discharge Rate and Temperature Effects}},
year = {2012}
}


[14] N. Jin, “Modelling of guardband reduction on design area,” Department of Electrical Engineering, University of California Los Angeles 2012.
[Bibtex]

@techreport{MSTR8,
author = {Jin, Ning},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {mad, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR8_paper.pdf},
title = {Modelling of Guardband Reduction on Design Area},
year = {2012}
}


[15] A. A. Kagalwalla, “Design-aware mask manufacturing,” Department of Electrical Engineering, University of California Los Angeles 2011.
[Bibtex]

@techreport{MSTH2,
author = {Kagalwalla, Abde Ali},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH2_paper.pdf},
title = {Design-Aware Mask Manufacturing},
year = {2011}
}


[16] S. Mok, “Post-Layout Sizing for Leakage Power Optimization: A Comparative Study,” Department of Electrical Engineering, University of California Los Angeles 2011.
[Bibtex]

@techreport{MSTR4,
author = {Mok, Santiago},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR4_paper.pdf},
title = {{Post-Layout Sizing for Leakage Power Optimization: A Comparative Study}},
year = {2011}
}


[17] C. Apte, “Power Consumption Variability in Embedded Processors,” Department of Electrical Engineering, University of California Los Angeles 2011.
[Bibtex]

@techreport{MSTR5,
author = {Apte, Charwak},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR5_paper.pdf},
title = {{Power Consumption Variability in Embedded
Processors}},
year = {2011}
}


[18] P. Kulkarni, “Trading Accuracy for Power with an Under-designed Multiplier Architecture,” Department of Electrical Engineering, University of California Los Angeles 2011.
[Bibtex]

@techreport{MSTR6,
author = {Kulkarni, Parag },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR6_paper.pdf},
title = {{Trading Accuracy for Power with an Under-designed
Multiplier Architecture}},
year = {2011}
}


[19] A. Pant, “Hardware-software interface in the presence of hardware manufacturing variations,” Department of Electrical Engineering, University of California Los Angeles 2010.
[Bibtex]

@techreport{MSTH1,
author = {Pant, Aashish },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH1_paper.pdf},
title = {Hardware-Software Interface in the Presence of Hardware Manufacturing Variations},
year = {2010}
}


[20] A. Kasibhatla, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” Department of Electrical Engineering, University of California Los Angeles 2010.
[Bibtex]

@techreport{MSTR3,
author = {Kasibhatla, Amarnath},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR3_paper.pdf},
title = {{Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics}},
year = {2010}
}


[21] D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” Department of Electrical Engineering, University of California Los Angeles 2010.
[Bibtex]

@techreport{MSTR2,
author = {Reinhard, Dominic},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {mad. msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR2_paper.pdf},
title = {{On Comparing Conventional and Electrically Driven OPC Techniques}},
year = {2010}
}


[22] V. Popuri, “Bias-driven Robust Analog Circuit Sizing Scheme,” Department of Electrical Engineering, University of California Los Angeles 2009.
[Bibtex]

@techreport{MSTR1,
author = {Popuri, Viswakiran},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR1_paper.pdf},
title = {{Bias-driven Robust Analog Circuit Sizing Scheme}},
year = {2009}
}