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Manufacturing-Aware Design

For design for manufacturing (DFM) models and methods to be  defensible  and  adoptable,  they  have  to  be  as  simple  as  possible  without  losing  physical  justification.  Our  ongoing  research  is  re-evaluating  several  assumptions  that  CAD  research  has  made  in  recent  years  to  avoid  “DFM  overkill”.  Starting from a deep understanding of the makeup of different physical phenomena that lead to the observed electrical variability, we have developed variability models and methods in physical design to deal with patterning constraints.

Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across-Wafer Variability

Objective: Modeling spatial variation is important for statistical analysis. In practice, all of which indicate that spatial variation comes from deterministic across-wafer variation, and purely random spatial variation is not significant. We analytically study the impact of across-wafer variation and show how it gives an appearance of correlation. We have developed a new die-level variation model considering deterministic across-wafer variation and derived the range of conditions under which ignoring spatial variation altogether may be acceptable.

Package: Spatial_detect is a Matlab script to extract across-wafer variation from measurement data. It assumes the across wafer variation to be a quadratic function. In this detection, we have two different spatial variation models: 1) Random field based spatial variation model [1, 2]; 2) Modeling across-wafer variation [3]. In practice, modeling across-wafer variation is more accurate and efficient than the random field based spatial variation model. The current release includes source code, user manual, and sample input files.

By: Lerong Cheng, advised by Prof. Puneet Gupta

Publications

    [1] R. Puri, N. Charudhattan, S. Saha, S. Rangarajan, R. Rao, and P. Gupta, “Design of deep sub-micron cmos circuit and design methodologies for high performance microprocessors,” in IEEE International Conference on VLSI Design, 2013.
    [Bibtex] 
    @conference{ITT17,
author = {R. Puri and N. Charudhattan and S. Saha and S. Rangarajan and R. Rao and P. Gupta},
booktitle = {{ IEEE International Conference on VLSI Design}},
keywords = {mad},
note = {Tutorial},
title = {Design of Deep Sub-Micron CMOS Circuit and Design Methodologies for High Performance Microprocessors},
year = {2013}
}

    [2] [PDF] N. Jin, “Modelling of guardband reduction on design area,” Department of Electrical Engineering, University of California Los Angeles 2012.
    [Bibtex] 
    @techreport{MSTR8,
author = {Jin, Ning},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {mad, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR8_paper.pdf},
title = {Modelling of Guardband Reduction on Design Area},
year = {2012}
}

    [3] P. Gupta, “Design-assisted semiconductor manufacturing,” in IEEE International Symposium on Quality Electronic Design, 2012.
    [Bibtex] 
    @conference{ITT15,
author = {Gupta, P.},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
keywords = {mad},
note = {Short tutorial},
title = {Design-Assisted Semiconductor Manufacturing},
year = {2012}
}

    [4] A. R. Neureuther, J. Rubinstein, M. Miller, Y. K. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T. -J. K. Liu, X. Sun, K. Jeong, P. and Gupta, A. A. Kagalwalla, R. S. Ghaida, and T. -B. Chan, “Collaborative research on emerging technologies and design,” in Proc. SPIE Photomask and Next-Generation Lithography Mask Technology, 2011.
    [Bibtex] 
    @inproceedings{IP7,
author = {A.R. Neureuther and J. Rubinstein and M. Miller and K. Yamazoeand E. Chin and C. Levy and L. Wang and N. Xu and C. Spanos and K. Qian and K. Poolla and J. Ghan and A. Subramanian and T.-J. K. Liu and X. Sun and K. Jeong and and P. Gupta and Kagalwalla, Abde Ali and Ghaida, R. S. and T.-B. Chan},
booktitle = {{Proc. SPIE Photomask and Next-Generation Lithography Mask Technology}},
category = {IP7},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/pmj11.pdf},
title = {Collaborative research on emerging technologies and design},
year = {2011}
}

    [5] P. Gupta, “Variability and reliability: will they get better or worse in future cmos technologies ?,” in IEEE Workshop on Design for Reliability and Variability, 2011.
    [Bibtex] 
    @conference{ITT14,
author = {Gupta, P.},
booktitle = {{IEEE Workshop on Design for Reliability and Variability}},
keywords = {mad},
note = {Panel Discussion},
title = { Variability and Reliability: Will they Get Better or Worse in Future CMOS Technologies ?},
year = {2011}
}

    [6] P. Gupta, “Designing for uncertainty: addressing process variations and aging issues in vlsi designs,” in IEEE International Symposium on VLSI Design, Automation and Test, 2011.
    [Bibtex] 
    @conference{ITT13,
author = {Gupta, P.},
booktitle = {{IEEE International Symposium on VLSI Design, Automation and Test}},
keywords = {mad, hsi},
note = {Tutorial},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/vlsidat_11.pdf},
title = {Designing for Uncertainty: Addressing Process Variations and Aging Issues in VLSI Designs},
year = {2011}
}

    [7] [PDF] J. Cong, P. Gupta, and J. Lee, “Evaluating Statistical Power Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, iss. 11, p. 1750–1762, 2010.
    [Bibtex] 
    @article{J12,
author = {Cong, J. and Gupta, P. and Lee, John},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {sizing, mad},
month = {Nov},
number = {11},
pages = {1750--1762},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J12_paper.pdf},
title = {{Evaluating Statistical Power Optimization}},
volume = {29},
year = {2010}
}

    [8] [PDF] J. Lee and P. Gupta, “Incremental Gate Sizing for Late Process Changes,” in Proc. IEEE International Conference on Computer Design, 2010.
    [Bibtex] 
    @inproceedings{C51,
author = {Lee, John and Gupta, Puneet},
booktitle = {{Proc. IEEE International Conference on Computer Design}},
category = {C51},
keywords = {sizing, mad},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C51_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C51_slides.pdf},
title = {{I}ncremental {G}ate {S}izing for {L}ate {P}rocess {C}hanges},
year = {2010}
}

    [9] [PDF] T. -B. Chan and P. Gupta, “On Electrical Modeling of Imperfect Diffusion Patterning,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010.
    [Bibtex] 
    @inproceedings{C45,
author = {Chan, T.-B. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C45},
keywords = {dats, mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C45_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C45_slides.pdf},
title = {On {E}lectrical {M}odeling of {I}mperfect {D}iffusion {P}atterning},
year = {2010}
}

    [10] [PDF] L. Cheng, P. Gupta, and L. He, “On Confidence in Characterization and Application of Variation Models,” in Proc. Asia and South Pacific Design Automation Conference, 2010.
    [Bibtex] 
    @inproceedings{C47,
author = {Cheng, L. and Gupta, P. and He, L.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C47},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C47_paper.pdf},
title = {On {C}onfidence in {C}haracterization and {A}pplication of {V}ariation {M}odels},
year = {2010}
}

    [11] [PDF] T. -B. Chan, R. S. Ghaida, and P. Gupta, “Electrical Modeling of Lithographic Imperfections,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010.
    [Bibtex] 
    @inproceedings{IP6,
author = {Chan, T.-B. and Ghaida, R. S. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {IP6},
keywords = {mad},
note = {Embedded Tutorial},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP6_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP6_slides.pdf},
title = {{E}lectrical {M}odeling of {L}ithographic {I}mperfections},
year = {2010}
}

    [12] [PDF] L. Cheng, P. Gupta, C. J. Spanos, K. Qian, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2010.
    [Bibtex] 
    @article{J14,
author = {Cheng, L. and Gupta, P. and Spanos, C. J. and Qian, K. and He, L.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J14_paper.pdf},
title = {{P}hysically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},
year = {2010}
}

    [13] [PDF] P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, “Electrical Assessment of Lithographic Gate Line-End Patterning,” spieJ, 2010.
    [Bibtex] 
    @article{J11,
author = {Gupta, P. and Jeong, K. and Kahng, A.B. and Park, C.-H.},
journal = {{spieJ}},
keywords = {mad, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J11_paper.pdf},
title = {Electrical {A}ssessment of {L}ithographic {G}ate {L}ine-{E}nd {P}atterning},
year = {2010}
}

    [14] [PDF] D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” Department of Electrical Engineering, University of California Los Angeles 2010.
    [Bibtex] 
    @techreport{MSTR2,
author = {Reinhard, Dominic},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {mad. msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR2_paper.pdf},
title = {{On Comparing Conventional and Electrically Driven OPC Techniques}},
year = {2010}
}

    [15] P. Gupta, “Modeling performance impact of variability,” in NSF/SRC The International Variability Characterization Workshop, 2010.
    [Bibtex] 
    @conference{ITT11,
author = {Gupta, P.},
booktitle = {{NSF/SRC The International Variability Characterization Workshop}},
keywords = {mad},
note = {Invited Talk},
title = {Modeling Performance Impact of Variability},
year = {2010}
}

    [16] [PDF] J. Cong, P. Gupta, and J. Lee, “On the Futlity of Statistical Power Optimization,” in Proc. Asia and South Pacific Design Automation Conference, 2009.
    [Bibtex] 
    @inproceedings{C38,
author = {Cong, J. and Gupta, P. and Lee, John},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C38},
keywords = {sizing, mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C38_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C38_slides.pdf},
title = {On the {F}utlity of {S}tatistical {P}ower {O}ptimization},
year = {2009}
}

    [17] [PDF] L. Cheng, P. Gupta, and L. He, “Accounting for Non-linear Dependence Using Function Driven Component Analysis,” in Proc. Asia and South Pacific Design Automation Conference, 2009.
    [Bibtex] 
    @inproceedings{C39,
author = {Cheng, L. and Gupta, P. and He, L.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C39},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C39_paper.pdf},
title = {Accounting for {N}on-linear {D}ependence {U}sing {F}unction {D}riven {C}omponent {A}nalysis},
year = {2009}
}

    [18] [PDF] L. Cheng, P. Gupta, and L. He, “Efficient Additive Statistical Leakage Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2009.
    [Bibtex] 
    @article{J9,
author = {Cheng, L. and Gupta, P. and He, L.},
category = {J9},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J9_paper.pdf},
title = {Efficient {A}dditive {S}tatistical {L}eakage {E}stimation},
year = {2009}
}

    [19] L. Cheng, P. Gupta, K. Qian, C. Spanos, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2009.
    [Bibtex] 
    @inproceedings{C43,
author = {Cheng, L. and Gupta, P. and Qian, K. and Spanos, C. and He, L.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C43},
keywords = {mad},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C43_paper.pdf},
title = {Physically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},
year = {2009}
}

    [20] P. Gupta, “Design for ultra-low-k1 patterning and manufacturing,” in IEEE International Conference on Microelectronic Teststructures (ICMTS), 2009.
    [Bibtex] 
    @conference{ITT10a,
author = {Gupta, P.},
booktitle = {{IEEE International Conference on Microelectronic Teststructures (ICMTS)}},
keywords = {mad},
note = {Tutorial},
title = { Design for Ultra-low-k1 Patterning and Manufacturing},
year = {2009}
}

    [21] P. Gupta, “Revisiting variation models and their reliability,” in IEEE/ACM Workshop on Variability Modeling and Characterization, 2009.
    [Bibtex] 
    @conference{ITT10,
author = {Gupta, P.},
booktitle = {{IEEE/ACM Workshop on Variability Modeling and Characterization}},
keywords = {mad},
note = {Invited talk},
title = {Revisiting Variation Models and Their Reliability},
year = {2009}
}

    [22] [PDF] P. Gupta and A. B. Kahng, “Bounded Lifetime Integrated Circuits,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2008.
    [Bibtex] 
    @inproceedings{C37,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C37},
keywords = {mad},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C37_paper.pdf},
title = {Bounded {L}ifetime {I}ntegrated {C}ircuits},
year = {2008}
}

    [23] [PDF] P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, “Electrical Metrics for Lithographic Line-End Tapering,” in SPIE Photomask and NGL Mask Technology, 2008.
    [Bibtex] 
    @inproceedings{C36,
author = {Gupta, P. and Jeong, K. and Kahng, A. B. and Park, C.-H},
booktitle = {{SPIE Photomask and NGL Mask Technology}},
category = {C36},
keywords = {mad, dats},
month = {April},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C36_paper.pdf},
title = {Electrical {M}etrics for {L}ithographic {L}ine-{E}nd {T}apering},
year = {2008}
}

    [24] [PDF] P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, “Shaping Gate Channels for Improved Devices,” in SPIE Advanced Lithography Symposium, 2008.
    [Bibtex] 
    @inproceedings{C35,
author = {Gupta, P. and Kahng, A. B. and Shah, S. and Sylvester, D.},
booktitle = {{SPIE Advanced Lithography Symposium}},
category = {C35},
keywords = {dats, mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C35_paper.pdf},
title = {Shaping {G}ate {C}hannels for {I}mproved {D}evices},
year = {2008}
}

    [25] [PDF] P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Investigation of Diffusion Rounding for Post-Lithography Analysis,” in Proc. Asia and South Pacific Design Automation Conference, 2008.
    [Bibtex] 
    @inproceedings{C34,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S. and Sylvester, D.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C34},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C34_paper.pdf},
title = {Investigation of {D}iffusion {R}ounding for {P}ost-{L}ithography {A}nalysis},
year = {2008}
}

    [26] P. Gupta and C. Wu, “Lithography and Memories: From Shapes to Electrical,” in IEEE VLSI Test Symposium, 2008.
    [Bibtex] 
    @conference{ITT6,
author = {Gupta, P. and Wu, C.},
booktitle = {{IEEE VLSI Test Symposium}},
category = {ITT6},
keywords = {mad},
title = {Lithography and {M}emories: {F}rom {S}hapes to {E}lectrical},
year = {2008}
}

    [27] D. Chidambarrao, P. Gupta, P. Elakkumanan, L. Liebmann, D. Marculescu, and N. Tamarapalli, “DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2008.
    [Bibtex] 
    @conference{ITT7,
author = {Chidambarrao, D. and Gupta, P. and Elakkumanan, P. and Liebmann, L. and Marculescu, D. and Tamarapalli, N.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {ITT7},
keywords = {mad},
note = {Full-day Tutorial},
title = {{DFM} {R}evisited: {A} {C}omprehensive {A}nalysis of {V}ariability at all {L}evels of {A}bstraction},
year = {2008}
}

    [28] P. Gupta, “The Electrical Design Manufacturing Interface,” in Electronic Design Processes Workshop, 2008.
    [Bibtex] 
    @conference{ITT5,
author = {Gupta, P.},
booktitle = {{Electronic Design Processes Workshop}},
category = {ITT5},
keywords = {mad, dats},
title = {The {E}lectrical {D}esign {M}anufacturing {I}nterface},
year = {2008}
}

    [29] P. Gupta, “Challenges at 45nm and Beyond,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2008.
    [Bibtex] 
    @conference{ITT8,
author = {Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {ITT8},
keywords = {mad, dats},
note = {Panel Discussion},
title = {Challenges at 45nm and {B}eyond},
year = {2008}
}

    [30] [PDF] P. Gupta, A. B. Kahng, and C. -H. Park, “Detailed Placement for Enhanced Control of Resist and Etch CDs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2007.
    [Bibtex] 
    @article{J7,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H.},
category = {J7},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
month = {December},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J7_paper.pdf},
title = {Detailed {P}lacement for {E}nhanced {C}ontrol of {R}esist and {E}tch {CD}s},
year = {2007}
}

    [31] [PDF] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2007.
    [Bibtex] 
    @article{J6,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},
category = {J6},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J6_paper.pdf},
title = {Self-{C}ompensating {D}esign for {R}eduction of {T}iming and {L}eakage {S}ensitivity to {S}ystematic {P}attern {D}ependent {V}ariation},
year = {2007}
}

    [32] [PDF] P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, “Line End Shortening is not Always a Failure,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2007.
    [Bibtex] 
    @inproceedings{C33,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C2},
keywords = {mad, dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C33_paper.pdf},
title = {Line {E}nd {S}hortening is not {A}lways a {F}ailure},
year = {2007}
}

    [33] P. Gupta and R. Puri, “Impact of Variability On VLSI Circuits,” in SPIE Advanced Lithography Symposium, 2007.
    [Bibtex] 
    @conference{ITT4,
author = {Gupta, P. and Puri, R.},
booktitle = {{SPIE Advanced Lithography Symposium}},
category = {ITT4},
keywords = {mad},
note = {Short Course},
title = {Impact Of {V}ariability {O}n {VLSI} {C}ircuits},
year = {2007}
}

    [34] [PDF] P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, “Gate-Length Biasing for Runtime Leakage Control,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2006.
    [Bibtex] 
    @article{J4,
author = {Gupta, P. and Kahng, A. B. and Sharma, P. and Sylvester, D.},
category = {J4},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {sizing, mad},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J4_paper.pdf},
title = {Gate-{L}ength {B}iasing for {R}untime {L}eakage {C}ontrol},
year = {2006}
}

    [35] [PDF] P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah, and P. Sharma, “Lithography Simulation-Based Full-Chip Design Analyses,” in SPIE Microlithography, 2006.
    [Bibtex] 
    @inproceedings{C28,
author = {Gupta, P. and Kahng, A. B. and Nakagawa, S. and Shah, S. and Sharma, P.},
booktitle = {{SPIE Microlithography}},
category = {C28},
keywords = {mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C28_paper.pdf},
title = {Lithography {S}imulation-{B}ased {F}ull-{C}hip {D}esign {A}nalyses},
year = {2006}
}

    [36] [PDF] P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis,” in SPIE Microlithography, 2006.
    [Bibtex] 
    @inproceedings{C29,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S. and Sylvester, D.},
booktitle = {{SPIE Microlithography}},
category = {C29},
keywords = {mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C2999999999_paper.pdf},
title = {Modeling of {N}on-{U}niform {D}evice {G}eometries for {P}ost-{L}ithography {C}ircuit {A}nalysis},
year = {2006}
}

    [37] [PDF] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,” in SPIE Microlithography, 2006.
    [Bibtex] 
    @inproceedings{C31,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},
booktitle = {{SPIE Microlithography}},
category = {C31},
keywords = {mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C31_paper.pdf},
title = {Self-{C}ompensating {D}esign for {R}eduction of {T}iming and {L}eakage {S}ensitivity to {S}ystematic {P}attern {D}ependent {V}ariation},
year = {2006}
}

    [38] [PDF] P. Gupta and A. B. Kahng, “Efficient Design and Analysis of Robust Power Distribution Meshes,” in Proc. IEEE/ACM International Conference on VLSI Design, 2006.
    [Bibtex] 
    @inproceedings{C27,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C27},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C27_paper.pdf},
title = {Efficient {D}esign and {A}nalysis of {R}obust {P}ower {D}istribution {M}eshes},
year = {2006}
}

    [39] [PDF] P. Gupta, A. B. Kahng, S. V. Muddu, and N. S., “Modeling Edge Placement Error Distribution in Standard Cell Library,” in SPIE Microlithography, 2006.
    [Bibtex] 
    @inproceedings{C30,
author = {Gupta, P. and Kahng, A. B. and Muddu, S.V. and Nakagawa S.},
booktitle = {{SPIE Microlithography}},
category = {C30},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C30_paper.pdf},
title = {Modeling {E}dge {P}lacement {E}rror {D}istribution in {S}tandard {C}ell {L}ibrary},
year = {2006}
}

    [40] [PDF] P. Gupta, A. B. Kahng, and C. -H. Park, “Enhanced Resist and Etch CD Control by Design Perturbation,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2005.
    [Bibtex] 
    @inproceedings{C24,
author = {Gupta, P. and Kahng, A. B. and C.-H. Park},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
category = {C24},
keywords = {mad},
month = {October},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C24_paper.pdf},
title = {Enhanced {R}esist and {E}tch {CD} {C}ontrol by {D}esign {P}erturbation},
year = {2005}
}

    [41] [PDF] P. Gupta, A. B. Kahng, O. S. Nakagawa, and K. Samadi, “Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing,” in Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf., 2005.
    [Bibtex] 
    @inproceedings{IP4,
author = {Gupta, P. and Kahng, A. B. and Nakagawa, O.S. and Samadi, K.},
booktitle = {{Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf.}},
category = {IP4},
keywords = {mad},
month = {October},
note = {Invited Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP4_paper.pdf},
title = {Closing the {L}oop in {I}nterconnect {A}nalyses and {O}ptimization: {CMP} {F}ill, {L}ithography and {T}iming},
year = {2005}
}

    [42] [PDF] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Focus Variation,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2005.
    [Bibtex] 
    @inproceedings{C23,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D. },
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C23},
keywords = {mad},
month = {June},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C23_paper.pdf},
title = {Self-{C}ompensating {D}esign for {F}ocus {V}ariation},
year = {2005}
}

    [43] [PDF] P. Gupta, A. B. Kahng, and C. -H. Park, “Manufacturing-Aware Design Methodology for Assist Feature Correctness,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2005.
    [Bibtex] 
    @inproceedings{C20,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H.},
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C20},
keywords = {mad},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C20_paper.pdf},
title = {Manufacturing-{A}ware {D}esign {M}ethodology for {A}ssist {F}eature {C}orrectness},
year = {2005}
}

    [44] [PDF] P. Gupta, F. -L. Heng, and J. -F. Lee, “Toward Through-Process Layout Quality Metrics,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2005.
    [Bibtex] 
    @inproceedings{C21,
author = {Gupta, P. and Heng, F.-L. and Lee, J.-F. },
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C21},
keywords = {mad},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C21_paper.pdf},
title = {Toward {T}hrough-{P}rocess {L}ayout {Q}uality {M}etrics},
year = {2005}
}

    [45] [PDF] P. Gupta, A. B. Kahng, and C. -H. Park, “Detailed Placement for Improved Depth of Focus and CD Control,” in Proc. Asia and South Pacific Design Automation Conference, 2005.
    [Bibtex] 
    @inproceedings{C19,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C19},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C19_paper.pdf},
title = {Detailed {P}lacement for {I}mproved {D}epth of {F}ocus and {CD} {C}ontrol},
year = {2005}
}

    [46] P. Gupta, “DFM Fundamentals,” in WesCon, 2005.
    [Bibtex] 
    @conference{ITT3,
author = {Gupta, P.},
booktitle = {{WesCon}},
category = {ITT3},
keywords = {mad},
note = {Short Tutorial},
title = {{DFM} {F}undamentals},
year = {2005}
}

    [47] P. Gupta and A. B. Kahng, “CMP and DFM,” in CMP-MIC, 2005.
    [Bibtex] 
    @conference{ITT2,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{CMP-MIC}},
category = {ITT2},
keywords = {mad},
note = {Short Tutorial},
title = {{CMP} and {DFM}},
year = {2005}
}

    [48] [PDF] P. Gupta, A. B. Kahng, P. Sharma, and D. D. Sylvester, “Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Reduction,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2004.
    [Bibtex] 
    @inproceedings{C15,
author = {Gupta, P. and Kahng, A. B. and Sharma, P. and D. Sylvester, D.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C5},
keywords = {sizing, mad},
month = {July},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C15_paper.pdf},
title = {Selective {G}ate-{L}ength {B}iasing for {C}ost-{E}ffective {R}untime {L}eakage {R}eduction},
year = {2004}
}

    [49] [PDF] P. Gupta and F. -L. Heng, “Toward a Systematic-Variation Aware Timing Methodology,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2004.
    [Bibtex] 
    @inproceedings{C14,
author = {Gupta, P. and Heng, F.-L.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C14},
keywords = {mad},
month = {July},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C14_paper.pdf},
title = {Toward a {S}ystematic-{V}ariation {A}ware {T}iming {M}ethodology},
year = {2004}
}

    [50] [PDF] P. Gupta, F. -L. Heng, R. L. Gordon, K. Lai, and J. Lee, “Taming Focus Variation in VLSI Design,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2004.
    [Bibtex] 
    @inproceedings{C12,
author = {Gupta, P. and Heng, F.-L. and Gordon, R.L. and Lai, K. and Lee, J. },
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C12},
keywords = {mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C12_paper.pdf},
title = {Taming {F}ocus {V}ariation in {VLSI} {D}esign},
year = {2004}
}

    [51] [PDF] P. Gupta and A. B. Kahng, “Manufacturing-Aware Physical Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2003.
    [Bibtex] 
    @inproceedings{IP1b,
author = {Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {IP1b},
keywords = {mad},
month = {November},
note = {Embedded Tutorial},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP1b_paper.pdf},
title = {Manufacturing-{A}ware {P}hysical {D}esign},
year = {2003}
}

    [52] [PDF] Y. Chen, P. Gupta, and A. B. Kahng, “Performance-Impact Limited Area Fill Synthesis,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2003.
    [Bibtex] 
    @inproceedings{C6,
author = {Chen, Y. and Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C6},
keywords = {mad},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C6_paper.pdf},
title = {Performance-{I}mpact {L}imited {A}rea {F}ill {S}ynthesis},
year = {2003}
}

    [53] [PDF] Y. Chen, P. Gupta, and A. B. Kahng, “Performance-Impact Limited Dummy Fill Insertion,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2003, pp. 857-862.
    [Bibtex] 
    @inproceedings{C3,
author = {Chen, Y. and Gupta, P. and Kahng, A. B.},
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C3},
keywords = {mad},
month = {February},
pages = {857-862},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C3_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C3_slides.pdf},
title = {Performance-{I}mpact {L}imited {D}ummy {F}ill {I}nsertion},
year = {2003}
}

    [54] [PDF] Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI,” in IEEE ASIC/SoC Conference, 2002, pp. 411-415.
    [Bibtex] 
    @inproceedings{C1,
author = {Cao, Y. and Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{IEEE ASIC/SoC Conference}},
category = {C1},
keywords = {mad},
month = {September},
pages = {411-415},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C1_paper.pdf},
title = {Design {S}ensitivities to {V}ariability: {E}xtrapolation and {A}ssessments in {N}anometer {VLSI}},
year = {2002}
}