Hardware-Software Interface in Presence of Variability

While a well-defined firm hardware-software in- terface enabled advances in software and hardware design methods, it is increasingly harder to sustain as the newer semiconductor technologies exhibit growing manufacturing variabil- ity across different instances of a chip, aging-related wear-out, and variability due to the operating environment. We are developing techniques to establish a bidirectional dataflow between the system/application layer and the physical/circuit implementation layer to en- able software to opportunistically take advantage of underdesigned hardware systems. The resulting Underdesigned and Opportunistic (UnO) computing machines monitor hardware power/performance and use instance-specific adaptation in software to relax variation-induced guard-bands in hardware design.

Circuit Performance Monitoring

Students: Liangzhen Lai

Circuit performance monitors are essential for systems with hardware and software adaptation to reduce the design margin. This project aims at developing accurate and inexpensive performance monitoring methodologies. Design-dependent ring oscillator (DDRO) is a replica monitoring methodology, which designs multiple smart canary structures that can reliably predict achievable chip frequency but with margins for local variations. Early silicon results indicate that DDROs can reduce delay monitoring error by 35% compared to conventional ring oscillators. To further improve the prediction (albeit at a higher overhead), we propose SlackProbein situ slack monitors which can match local variations as well at overheads much smaller than monitoring all sequential elements. SlackProbe reduces the number of monitors required by over 15X with 5% additional delay margin in several commercial processor benchmarks.

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Hardware Variability-Aware Duty Cycling for Embedded Sensors

Instance and temperature-dependent power variation has a direct impact on quality of sensing for battery powered, long running sensing applications. We measure and characterize active and leakage power for an ARM Cortex M3 processor, and show that across a temperature range of 20–60◦C there is 10% variation in active power, and 14x variation in leakage power. We introduce variability aware duty cycling methods and a duty cycle abstraction for TinyOS that allows ap- plications to explicitly specify lifetime and minimum duty cycle requirements for individual tasks, and dynamically adjusts duty cycle rates so that overall quality of service is maximized in the presence of power variability. We show that variability-aware duty cycling yields a 3–22x improve- ment in total active time over schedules based on worst- case estimations of power, with an average improvement of 6.4x across a wide variety of deployment scenarios based on collected temperature traces. Conversely, datasheet power specifications fail to meet required lifetimes by 7– 15%, with an average 37 days short of a required lifetime of one year. Finally, we show that a target localization application using variability-aware duty cycle yields a 50% improvement in quality of results over one based on worst- case estimations of power consumption.

A demo of variability-aware duty-cycling using our own testchip and testbed platform is shown in the following youtube video. Detailed description can be found in the technical report(link).

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AppAdapt: Leveraging Application Adaptativity to Compensate Hardware Variation

Students: Aashish Pant

Objective: In this project, we seek to build on the flexible hardware-software interface paradigm by proposing the notion of hardware instance guided software adaptation for performance constrained applications. where the actual hardware state guides application adaptation on a die specific basis. We show that, by adapting the application to the post manufacturing hardware characteristics (hardware signatures) across different die, it is possible to compensate for application quality losses that might otherwise be significant in presence of process variations. This in turn results in improved manufacturing yield, relaxed requirement for hardware over-design and better application quality.

This work is motivated by the fact that a plethora of modern applications are reconfigurable and adaptive, i.e. they are capable of operating in various configurations by adapting to certain input or environmental conditions in turn producing similar or different quality of service. Moreover, process variation is increasing and hence, the conventional methods of incorporating variation-resistant design techniques, post manufacturing hardware tuning or hardware over-design have become too expensive to use for practical reasons. We observe that it is easier and cheaper to implement adaptation at the software layer as compared to designing a robust and dependable hardware in the presence of manufacturing variations. Moreover, adaptation is much better informed of the die-specific variation scenario at the application software layer.

Please see the videos below for a comparison of hardware adaptive vs non-adaptive encoder. Use the player provided with a frame resolution of 352×288 (CIF).

• vidview.exe: VidView Player to play the raw .yuv video files (CIF 352×288 frame format)

• orig.yuv: Original Un-Encoded Mobile Video Sequence

• output_29_m15.yuv: Encoded Video on 20% over-designed hardware which is slower by 15%

• output_59_m10.yuv: Encoded Video on 20% over-designed hardware which is slower by 10%

• output_85_m5.enc: Encoded Video on 20% over-designed hardware which is slower by 5%

• output_87_0.yuv: Encoded Video on 20% over-designed hardware which is slower by 0%

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Variation Aware Binning of Multi-core Processors

Students: Aashish Pant

Objective: Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. In this project, our major focus is to leverage information obtained from a process variation model to evaluate the binning metrics more efficiently and accurately.

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Publications

[1] S. Pal, “Supervia: relieving routing congestion using double-height vias,” Department of Electrical Engineering, University of California Los Angeles 2017.
[Bibtex]

@techreport{MSTR13,
author = {Pal, Saptadeep},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR13_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR13_slides.pdf},
title = {Supervia: Relieving Routing Congestion using Double-height Vias},
year = {2017}
}


[2] V. Dokania, “Intrusive routing for improved standard cell pin access,” Department of Electrical Engineering, University of California Los Angeles 2017.
[Bibtex]

@techreport{MSTR12,
author = {Dokania, Vishesh },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR12_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR12_slides.pdf},
title = {Intrusive Routing for Improved Standard Cell Pin Access},
year = {2017}
}


[3] L. Lai and P. Gupta, “Hardware Reliability Margining for the Dark Silicon Era,” in Proc. Asia and South Pacific Design Automation Conference, 2016.
[Bibtex]

@inproceedings{C90,
author = {Lai, Liangzhen and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {hsi},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C90_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C90_slides.pptx},
title = {{H}ardware {R}eliability {M}argining for the {D}ark {S}ilicon {E}ra},
year = {2016}
}


[4] N. Lyu, “Leon3 processor variability emulator for delay variability impact on performance,” Department of Electrical Engineering, University of California Los Angeles 2016.
[Bibtex]

@techreport{MSTR11,
author = {Lyu, Nan},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR11_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR11_slides.pdf},
title = {Leon3 Processor Variability Emulator for Delay Variability Impact on Performance},
year = {2016}
}


[5] M. Gottscho, C. Schoeny, L. Dolecek, and P. Gupta, “Software-Defined Error-Correcting Codes,” in IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), 2016.
[Bibtex]

@conference{W13,
author = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {memres,hsi,ecc,memory,reliability,architecture,coding,systems,dram,caches},
note = {Best Paper Award},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_slides.pptx},
title = {{Software-Defined Error-Correcting Codes}},
year = {2016}
}


[6] L. Lai, V. Chandra, and P. Gupta, “Evaluating and Exploiting Impacts of Dynamic Power Management Schemes on System Reliability,” in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2015.
[Bibtex]

@inproceedings{C88,
author = {Lai, Liangzhen and Chandra, Vikas and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)}},
keywords = {hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C88_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C88_slides.pdf},
title = {{E}valuating and {E}xploiting {I}mpacts of {D}ynamic {P}ower {M}anagement {S}chemes on {S}ystem {R}eliability},
year = {2015}
}


[7] L. Lai, “Cross-layer approaches for monitoring, margining and mitigation of circuit variability,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2015.
[Bibtex]

@phdthesis{PHDTH5,
author = {Lai, Liangzhen},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH5_paper.pdf},
title = {Cross-Layer Approaches for Monitoring, Margining and Mitigation of Circuit Variability},
year = {2015}
}


[8] S. Wang, H. Hu, H. Zheng, and P. Gupta, “MEMRES: A Fast Memory System Reliability Simulator,” in IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), 2015.
[Bibtex]

@conference{W12,
author = {Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {hsi, MEMRES, memory faults},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W12_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W12_slides.pptx},
title = {{MEMRES: A Fast Memory System Reliability Simulator}},
year = {2015}
}


[9] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, iss. 8, pp. 1168-1179, 2014.
[Bibtex]

@article{J34,
author = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {hsi},
month = {Aug},
number = {8},
pages = {1168-1179},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J34_paper.pdf},
title = {{S}lack{P}robe: {A} {F}lexible and {E}fficient {I}n {S}itu {T}iming {S}lack {M}onitoring {M}ethodology},
volume = {33},
year = {2014}
}


[10] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “BTI-Gater: An Aging-Resilient Clock Gating Methodology,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, iss. 2, pp. 180-189, 2014.
[Bibtex]

@article{J32,
author = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},
journal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},
keywords = {hsi, NBTI},
month = {June},
number = {2},
pages = {180-189},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J32_paper.pdf},
title = {{B}{T}{I}-{G}ater: {A}n {A}ging-{R}esilient {C}lock {G}ating {M}ethodology},
volume = {4},
year = {2014}
}


[11] L. Lai and P. Gupta, “Accurate and inexpensive performance monitoring for variability-aware systems,” in Proc. Asia and South Pacific Design Automation Conference, 2014, pp. 467-473.
[Bibtex]

@inproceedings{IP13,
author = {Lai, Liangzhen and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {hsi},
month = {Jan},
pages = {467-473},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP13_paper.pdf},
title = {Accurate and inexpensive performance monitoring for variability-aware systems},
year = {2014}
}


[12] M. Gottscho, “ViPZonE: Exploiting DRAM Power Variability for Energy Savings in Linux x86-64,” Department of Electrical Engineering, University of California Los Angeles 2014.
[Bibtex]

@techreport{MSTR10,
author = {Gottscho, Mark},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR10_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR10_slides.pdf},
title = {{V}i{P}{Z}on{E}: {E}xploiting {DRAM} {P}ower {V}ariability for {E}nergy {S}avings in {L}inux x86-64},
year = {2014}
}


[13] Y. Agarwal, A. Bishop, T. Chan, M. Fotjik, P. Gupta, A. Kahng, L. Lai, P. Martin, M. Srivastava, D. Sylvester, L. Wanner, and B. Zhang, “Redcooper: hardware sensor enabled variability software testbed for lifetime energy constrained application,” 2014.
[Bibtex]

@techreport{TECHRP1,
author = {Agarwal, Yuvraj and Bishop, Alex and Chan, Tuck-Boon and Fotjik, Matt and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen and Martin, Paul and Srivastava, Mani and Sylvester, Dennis and Wanner, Lucas and Zhang, Bing},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/1c21g217},
title = {Redcooper: Hardware sensor enabled variability software testbed for lifetime energy constrained application},
year = {2014}
}


[14] L. Lai, C. Chang, and P. Gupta, “Exploring total power saving from high temperature of server operations,” 2014.
[Bibtex]

@techreport{TECHRP2,
author = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/5898p020},
title = {Exploring Total Power Saving from High Temperature of Server Operations},
year = {2014}
}


[15] L. Lai and P. Gupta, “A case study of logic delay fault behaviors on general-purpose embedded processor under voltage overscaling,” 2014.
[Bibtex]

@techreport{TECHRP3,
author = {Lai, Liangzhen and Gupta, Puneet},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/3967v8hw},
title = {A Case Study of Logic Delay Fault Behaviors on General-Purpose Embedded Processor Under Voltage Overscaling},
year = {2014}
}


[16] L. Lai, C. Chang, and P. Gupta, “Exploring total power saving from high temperature of server operations,” , 2014.
[Bibtex]

@article{TR1,
author = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},
keywords = {hsi},
paperurl = {http://escholarship.org/uc/item/5898p020},
title = {Exploring Total Power Saving from High Temperature of Server Operations},
year = {2014}
}


[17] A. Bhatia, “Varleon: fpga based processor variability emulator for variation aware software,” Department of Electrical Engineering, University of California Los Angeles 2014.
[Bibtex]

@techreport{MSTR9,
author = {Bhatia, Abishek},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR9_paper.pdf},
title = {VarLEON: FPGA Based Processor Variability Emulator for Variation Aware Software},
year = {2014}
}


[18] M. Namaki-Shoushtari, A. Rahimi, N. Dutt, P. Gupta, and R. K. Gupta, “ARGO: Aging-aware GPGPU register file allocation,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, 2013.
[Bibtex]

@inproceedings{C71,
author = {Namaki-Shoushtari, Majid and Rahimi, Abbas and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh K.},
booktitle = {{ACM International Conference on Hardware/Software Codesign and System Synthesis}},
keywords = {hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C71_paper.pdf},
title = {{A}{R}{G}{O}: {A}ging-aware {G}{P}{G}{P}{U} Register File Allocation},
year = {2013}
}


[19] L. Wanner, S. Elmalaki, L. Lai, P. Gupta, and M. Srivastava, “VarEMU: An Emulation Testbed for Variability-Aware Software,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, 2013.
[Bibtex]

@inproceedings{C70,
author = {Wanner, Lucas and Elmalaki, Salma and Lai, Liangzhen and Gupta, Puneet and Srivastava, Mani},
booktitle = {{ACM International Conference on Hardware/Software Codesign and System Synthesis}},
category = {C70},
keywords = {hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C70_paper.pdf},
title = {{V}ar{E}{M}{U}: {A}n {E}mulation {T}estbed for {V}ariability-{A}ware {S}oftware},
year = {2013}
}


[20] N. Dutt, P. Gupta, A. Nicolau, L. Bathen, and M. Gottscho, “Variability-Aware Memory Management for Nanoscale Computing,” in Proc. Asia and South Pacific Design Automation Conference, 2013.
[Bibtex]

@inproceedings{IP10,
author = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and Bathen, Luis and Gottscho, Mark},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {hsi, variability, memory, dram, uno},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP10_paper.pdf},
title = {{V}ariability-{A}ware {M}emory {M}anagement for {N}anoscale {C}omputing},
year = {2013}
}


[21] J. Henkel, L. Bauer, N. Dutt, P. Gupta, S. Nassif, M. Shafique, M. Tahoori, and N. Wehn, “Reliable on-chip systems in the nano-era: lessons learnt and future trends,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2013, p. 99:1–99:10.
[Bibtex]

@inproceedings{IP12,
author = {Henkel, J\"{o}rg and Bauer, Lars and Dutt, Nikil and Gupta, Puneet and Nassif, Sani and Shafique, Muhammad and Tahoori, Mehdi and Wehn, Norbert},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {hsi},
pages = {99:1--99:10},
title = {Reliable on-chip systems in the nano-era: lessons learnt and future trends},
year = {2013}
}


[22] T. Chan, P. Gupta, A. B. Kahng, and L. Lai, “Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors,” IEEE Transactions on Very Large Scale Integration Systems, 2013.
[Bibtex]

@article{J31,
author = {Chan, Tuck-Boon and Gupta, Puneet and Kahng, A. B. and Lai, Liangzhen},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi, DDRO},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J31_paper.pdf},
title = {{S}ynthesis and {A}nalysis of {D}esign-{D}ependent {R}ing {O}scillator ({D}{D}{R}{O}) {P}erformance {M}onitors},
year = {2013}
}


[23] L. Bathen, M. Gottscho, N. Dutt, P. Gupta, and A. Nicolau, “ViPZonE: OS-Level Memory Variability-Aware Physical Address Zoning for Energy Savings,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, 2012.
[Bibtex]

@inproceedings{C65,
author = {Bathen, Luis and Gottscho, Mark and Dutt, Nikil and Gupta, Puneet and Nicolau, Alex},
booktitle = {{ACM International Conference on Hardware/Software Codesign and System Synthesis}},
category = {C65},
keywords = {hsi, vipzone, os, variability, variability-aware, dram, memory, power, zone, zoning, allocation},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C65_paper.pdf},
title = {{V}i{P}{Z}on{E}: {O}{S}-{L}evel {M}emory {V}ariability-{A}ware {P}hysical {A}ddress {Z}oning for {E}nergy {S}avings},
year = {2012}
}


[24] L. A. D. Bathen, N. D. Dutt, A. Nicolau, and P. Gupta, “Vamv: variability-aware memory virtualization,” in DATE, 2012.
[Bibtex]

@inproceedings{C61,
author = {L.A.D. Bathen and N.D. Dutt and A. Nicolau and P. Gupta},
booktitle = {{DATE}},
keywords = {hsi},
month = {March},
note = {Best interactive presentation},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/BathenDNG12.pdf},
title = {VaMV: Variability-aware Memory Virtualization},
year = {2012}
}


[25] T. B. Chan, P. Gupta, A. Kahng, and L. Lai, “DDRO: a Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,” in ISQED, 2012.
[Bibtex]

@inproceedings{C60,
author = {Chan, Tuck Boon and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen},
booktitle = {{ISQED}},
category = {C60},
keywords = {hsi, DDRO},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C60_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C60_slides.pdf},
title = {{DDRO}: A {N}ovel {P}erformance {M}onitoring {M}ethodology {B}ased on {D}esign-{D}ependent {R}ing {O}scillators},
year = {2012}
}


[26] J. Dong, “High Level Battery Modeling Considering Discharge Rate and Temperature Effects,” Department of Electrical Engineering, University of California Los Angeles 2012.
[Bibtex]

@techreport{MSTR7,
author = {Dong, Jingyuan},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR7_paper.pdf},
title = {{High Level Battery Modeling Considering Discharge Rate and Temperature Effects}},
year = {2012}
}


[27] M. Gottscho, A. A. Kagalwalla, and P. Gupta, “Power Variability in Contemporary DRAMs,” IEEE Embedded Systems Letters, vol. 4, p. 37–40, 2012.
[Bibtex]

@article{J20,
author = {Gottscho, Mark and Kagalwalla, Abde Ali and Gupta, Puneet},
issue = {2},
journal = {{IEEE Embedded Systems Letters}},
keywords = {DRAM, DDR3, power, variability, hsi},
pages = {37--40},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J20_paper.pdf},
title = {{P}ower {V}ariability in {C}ontemporary {DRAM}s},
volume = {4},
year = {2012}
}


[28] P. Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. N. T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester, “Underdesigned and opportunistic computing in presence of hardware variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
[Bibtex]

@article{J26,
author = {Puneet Gupta and Yuvraj Agarwal and Lara Dolecek and Nikil Dutt and Rajesh K. Gupta and Rakesh Kumar and Subhasish Mitra and Alexandru Nicolauand Tajana Simunic Rosing and Mani B. Srivastava and Steven Swanson and Dennis Sylvester},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {hsi},
note = {Keynote Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/UnO_keynote.pdf},
title = {Underdesigned and Opportunistic Computing in Presence of Hardware Variability},
year = {2012}
}


[29] L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “Hardware Variability-Aware Duty Cycling for Embedded Sensors,” IEEE Transactions on Very Large Scale Integration Systems, 2012.
[Bibtex]

@article{J23,
author = {Lucas Wanner and Charwak Apte and Rahul Balani and Puneet Gupta and Mani Srivastava},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/j23.pdf},
title = {{H}ardware {V}ariability-{A}ware {D}uty {C}ycling for {E}mbedded {S}ensors},
year = {2012}
}


[30] P. Gupta, “Measuring and monitoring variability,” in IEEE International On-Line Test Symposium, 2012.
[Bibtex]

@conference{ITT16,
author = {Gupta, P.},
booktitle = {{IEEE International On-Line Test Symposium}},
keywords = {hsi},
note = {Invited Talk},
title = { Measuring and Monitoring Variability},
year = {2012}
}


[31] L. Wanner, R. Balani, S. Zahedi, C. Apte, P. Gupta, and M. Srivastava, “Variability Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems,” in Design, Automation, and Test in Europe (DATE), 2011.
[Bibtex]

@inproceedings{C56,
author = {Wanner, Lucas and Balani, Rahul and Zahedi, Sadaf and Apte, Charwak and Gupta, Puneet and Srivastava, Mani },
booktitle = {{Design, Automation, and Test in Europe (DATE)}},
category = {C56},
keywords = {variabilty-aware, embedded sensing, hsi},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C56_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C56_slides.pdf},
title = {{V}ariability {A}ware {D}uty {C}ycle {S}cheduling in {L}ong {R}unning {E}mbedded {S}ensing {S}ystems},
year = {2011}
}


[32] T. -B. Chan, J. Sartori, P. Gupta, and R. Kumar, “On the Efficacy of NBTI Mitigation Techniques,” in Design, Automation, and Test in Europe (DATE), 2011.
[Bibtex]

@inproceedings{C55,
author = {Chan, T.-B. and Sartori, John and Gupta, Puneet and Kumar, Rakesh},
booktitle = {{Design, Automation, and Test in Europe (DATE)}},
category = {C55},
keywords = {variabilty-aware, embedded sensing, hsi, ucla_rdmode},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C55_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C55_slides.pdf},
title = {{O}n the {E}fficacy of {NBTI} {M}itigation {T}echniques},
year = {2011}
}


[33] P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading Accuracy for Power with an Underdesigned Multiplier Architecture,” in Proc. IEEE/ACM International Conference on VLSI Design, 2011.
[Bibtex]

@inproceedings{C54,
author = {Kulkarni, Parag and Gupta, Puneet and Ercegovac, Milos},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C54},
keywords = {low power, hsi},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C54_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C54_slides.pdf},
title = {{T}rading {A}ccuracy for {P}ower with an {U}nderdesigned {M}ultiplier {A}rchitecture},
year = {2011}
}


[34] P. Kulkarni, P. Gupta, and M. D. Ercegovac, “Trading accuracy for power in a multiplier architecture,” Journal of Low Power Electronics, 2011.
[Bibtex]

@article{J16,
author = {Kulkarni, P. and Gupta, P. and Ercegovac, M.D.},
journal = {{Journal of Low Power Electronics}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/JOLPE_v3.pdf},
title = {Trading Accuracy for Power in a Multiplier Architecture},
year = {2011}
}


[35] C. Apte, “Power Consumption Variability in Embedded Processors,” Department of Electrical Engineering, University of California Los Angeles 2011.
[Bibtex]

@techreport{MSTR5,
author = {Apte, Charwak},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR5_paper.pdf},
title = {{Power Consumption Variability in Embedded
Processors}},
year = {2011}
}


[36] P. Kulkarni, “Trading Accuracy for Power with an Under-designed Multiplier Architecture,” Department of Electrical Engineering, University of California Los Angeles 2011.
[Bibtex]

@techreport{MSTR6,
author = {Kulkarni, Parag },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR6_paper.pdf},
title = {{Trading Accuracy for Power with an Under-designed
Multiplier Architecture}},
year = {2011}
}


[37] P. Gupta, “Designing for uncertainty: addressing process variations and aging issues in vlsi designs,” in IEEE International Symposium on VLSI Design, Automation and Test, 2011.
[Bibtex]

@conference{ITT13,
author = {Gupta, P.},
booktitle = {{IEEE International Symposium on VLSI Design, Automation and Test}},
keywords = {mad, hsi},
note = {Tutorial},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/vlsidat_11.pdf},
title = {Designing for Uncertainty: Addressing Process Variations and Aging Issues in VLSI Designs},
year = {2011}
}


[38] P. Gupta, “Underdesigned and opportunistic computing machines,” in Nanosystem Design and Variability Workshop, EPFL, 2011.
[Bibtex]

@conference{ITT12,
author = {Gupta, P.},
booktitle = {{Nanosystem Design and Variability Workshop, EPFL}},
keywords = {hsi},
note = {Invited Talk},
title = {Underdesigned and Opportunistic Computing Machines},
year = {2011}
}


[39] P. Gupta and R. Gupta, “Underdesigned and opportunistic computing,” in Proc. Asian Test Symposium, 2011.
[Bibtex]

@inproceedings{IP8,
author = {P. Gupta and R. Gupta},
booktitle = {{Proc. Asian Test Symposium}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/uno_ats_v4.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ats_11_v1.pdf},
title = {Underdesigned and Opportunistic Computing},
year = {2011}
}


[40] A. Pant, P. Gupta, and M. van der Schaar, “Appadapt: opportunistic application adaptation in presence of hardware variation,” IEEE Transactions on Very Large Scale Integration Systems, 2011.
[Bibtex]

@article{J17,
author = {Aashish Pant and Gupta, Puneet and Mihaela van der Schaar},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/VarAwareAdapt.pdf},
title = {AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation},
year = {2011}
}


[41] L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “A Case for Opportunistic Embedded Sensing In Presence of Hardware Power Varibility,” in HotPower’10, 2010.
[Bibtex]

@conference{C58,
author = {Wanner, Lucas and Apte, Charwak and Balani, Rahul and Gupta, Puneet and Srivastava, Mani},
booktitle = {{HotPower'10}},
category = {C58},
keywords = {embedded sensing, leakage power, duty cycling, hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C58_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C58_slides.pdf},
title = {{A} {C}ase for {O}pportunistic {E}mbedded {S}ensing {I}n {P}resence of {H}ardware {P}ower {V}aribility},
year = {2010}
}


[42] A. Pant, P. Gupta, and M. van der Schaar, “Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability,” in ACM Great Lakes Symposium on Very Large Scale Integration, 2010.
[Bibtex]

@inproceedings{C49,
author = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},
booktitle = {{ACM Great Lakes Symposium on Very Large Scale Integration}},
category = {C49},
keywords = {hsi},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C49_paper.pdf},
title = {{S}oftware {A}daptation in {Q}uality {S}ensitive {A}pplications to {D}eal with {H}ardware {V}ariability},
year = {2010}
}


[43] J. Sartori, A. Pant, R. Kumar, and P. Gupta, “Variation Aware Speed Binning of Multi-core Processors,” in IEEE International Symposium on Quality Electronic Design, 2010.
[Bibtex]

@inproceedings{C48,
author = {Sartori, John and Pant, Aashish and Kumar, Rakesh and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
category = {C48},
keywords = {hsi},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C48_paper.pdf},
title = {{V}ariation {A}ware {S}peed {B}inning of {M}ulti-core {P}rocessors},
year = {2010}
}


[44] A. Pant, P. Gupta, and M. van der Schaar, “Software Adaptation to Handle Manufacturing Variability and Relax Hardware Overdesign,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2009.
[Bibtex]

@conference{W2,
author = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W2},
keywords = {hsi-p1},
title = {{S}oftware {A}daptation to {H}andle {M}anufacturing {Variability} and {R}elax {H}ardware {O}verdesign},
year = {2009}
}


[45] J. Sartori, A. Pant, P. Gupta, and R. Kumar, “On Performance Binning of Multicore Processors,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2009.
[Bibtex]

@conference{W3,
author = {Sartori, John and Pant, Aashish and Gupta, Puneet and Kumar, Rakesh},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W3},
keywords = {hsi-p2},
title = {{O}n {P}erformance {B}inning of {M}ulticore {P}rocessors},
year = {2009}
}