Faculty (Principal Investigator)
Homepage: http://www.ee.ucla.edu/~puneet
Contact: puneet AT ee DOT ucla DOT edu
PhD Students
Publications
[1] H. Yang, N. Pesericoa, S. Li, B. F. Motlagh, J. S. Virdi, P. Gupta, V. J. Sorger, and C. W. Wong, “Enhancing and up-scaling of integrated photonic 4F convolution neural networks,” in Smart Photonic and Optoelectronic Integrated Circuits 2024, 2024, p. 1289003
[Bibtex] @conference{W27,
author = {Hangbo Yang and Nicola Pesericoa and Shurui Li and Benyamin Fallahi Motlagh and Jaskirat Singh Virdi and Puneet Gupta and Volker J. Sorger and Chee Wei Wong},
booktitle = {{Smart Photonic and Optoelectronic Integrated Circuits 2024}},
doi = {10.1117/12.2692958},
editor = {Sailing He and Laurent Vivien},
keywords = {Machine Learning, Convolution Neural Network, Integrated Photonics},
organization = {International Society for Optics and Photonics},
pages = {1289003},
publisher = {SPIE},
title = {{Enhancing and up-scaling of integrated photonic 4F convolution neural networks}},
url = {https://doi.org/10.1117/12.2692958},
volume = {12890},
year = {2024}
}
[Bibtex] @inproceedings{C125,
author = {Li, Shurui and Yang, Hangbo and Wong, Chee Wei and Sorger, Volker J. and Gupta, Puneet},
booktitle = {{IEEE/ACM International Symposium on Microarchitecture (MICRO)}},
doi = {https://doi.org/10.1145/3613424.3623798.},
keywords = {photonic neural network,deep learning, accelerator, photonics},
month = {October},
note = {},
pages = {13},
title = {{ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator}},
year = {2023}
}
[Bibtex] @inproceedings{C123,
author = {Li, Tianmu and Li, Shurui and Gupta, Puneet},
booktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},
doi = {},
keywords = {approximate computing, neural networks, training},
month = {March},
note = {},
pages = {6},
title = {{Training Neural Networks for Execution on Approximate Hardware}},
year = {2023}
}
[Bibtex] @inproceedings{C122,
author = {Li, Shurui and Yang, Hangbo and Wong, Chee Wei and Sorger, Volker J. and Gupta, Puneet},
booktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},
doi = {},
keywords = {photonics, neural network, accelerator},
month = {February},
note = {},
pages = {12},
title = {{PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator}},
year = {2023}
}
[Bibtex] @article{J71,
author = {Hu, Zibo and Li, Shurui and Schwartz, Russel and Solyanik-Gorgone, Maria and Miscuglio, Mario and Gupta, Puneet and Sorger, Volker},
journal = {{Laser \& Photonics Reviews}},
month = {October},
publisher = {{Wiley}},
title = {{High-Throughput Multichannel Parallelized Diffraction Convolutional Neural Network Accelerator}},
year = {2022}
}
[Bibtex] @inproceedings{C119,
author = {Li, Shurui and Gupta, Puneet},
booktitle = {{Conference on Machine Learning and Systems (MLSys)}},
doi = {},
keywords = {mledge},
month = {August},
note = {},
pages = {10},
title = {{Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors}},
year = {2022}
}
[Bibtex] @conference{IT29,
author = {Li, Shurui and Gupta, Puneet},
booktitle = {{SPIE Photonics West Conference (AI and Optical Data Sciences)}},
keywords = {photonics, optical neural network},
month = {February},
title = {{4F Optical Neural Network Acceleration: An Architectural Perspective}},
year = {2022}
}
[Bibtex] @inproceedings{IP18,
author = {Li, Shurui and Gupta, Puneet},
booktitle = {{{SPIE 12019, AI and Optical Data Sciences III}}},
keywords = {photonics},
title = {{4F optical neural network acceleration: an architecture perspective}},
year = {2022}
}
[Bibtex] @inproceedings{C113,
author = {Li, Shurui and Romaszkan, Wojciech and Graening, Alexander and Gupta, Puneet},
booktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},
doi = {},
keywords = {mledge, quantization, systolic array},
month = {March},
note = {},
pages = {},
title = {{SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration}},
year = {2021}
}
[Bibtex] @conference{W18,
author = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and George, Jonathan K. and Capanna, Roberto and Dalir, Hamed and Bardet, Philippe M. and Gupta, Puneet and Sorger, Volker J.},
booktitle = {{Conference on Lasers and Electro-Optics (CLEO)}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://ieeexplore.ieee.org/abstract/document/9572872},
title = {{Massively-parallel Amplitude-only Fourier Optical Convolutional Neural Network}},
year = {2021}
}
[Bibtex] @conference{W19,
author = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and Gupta, Puneet and Dalir, Hamed and Sorger, Volker J.},
booktitle = {{Signal Processing in Photonic Communications}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://opg.optica.org/abstract.cfm?uri=SPPCom-2021-SpM5C.2},
title = {{Fourier Optical Convolutional Neural Network Accelerator}},
year = {2021}
}
[Bibtex] @conference{W20,
author = {Hu, Zibo and Solyanik-Gorgone, Maria and Li, Shurui and Gupta, Puneet and Sorger, Volker J.},
booktitle = {{Frontiers in Optics}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://opg.optica.org/abstract.cfm?uri=fio-2021-FTh4C.5},
title = {{High Throughput Multi-kernel Fourier Optic Classifier}},
year = {2021}
}
[Bibtex] @article{J67,
author = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and George, Jonathan and Capanna, Roberto and Bardet, Philippe and Gupta, Puneet and Sorger, Volker},
journal = {{Optica}},
publisher = {{OSA}},
title = {{Massively parallel amplitude-only Fourier neural network}},
year = {2020}
}
[Bibtex] @conference{W16,
author = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and Gu, Jiaqi and Babakhani, Aydin and Gupta, Puneet and Wong, Chee-Wei and Pan, David and Bank, Seth and Dalir, Hamed and Sorger, Volker J.},
booktitle = {{CLEO: Applications and Technology}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://opg.optica.org/abstract.cfm?uri=cleo_at-2020-JF3A.4},
title = {{Million-channel Parallelism Fourier-optic Convolutional Filter and Neural Network Processor}},
year = {2020}
}
[Bibtex] @conference{W17,
author = {Hu, Zibo and Miscuglio, Mario and Li, Shurui and George, Jonathan K. and Gupta, Puneet and Sorger, Volker J.},
booktitle = {{Frontiers in Optics}},
keywords = {photonics, CNN, accelerator, Fourier, neural network},
paperurl = {https://opg.optica.org/abstract.cfm?uri=FiO-2020-FM7D.3},
title = {{Electro-Optical Hybrid Fouirer Neural Network with Amplitude-Only Modulation}},
year = {2020}
}
Publications
[1] W. Romaszkan, J. Yang, A. Graening, V. Jacob, J. Sen, S. Pamarti, and P. Gupta, “SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras,” in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024, p. 12
[Bibtex] @inproceedings{C127,
author = {Romaszkan, Wojciech and Yang, Jiyue and Graening, Alexander and Jacob, Vinod and Sen, Jishnu and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
doi = {},
keywords = {},
month = {September},
pages = {12},
title = {{SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras}},
year = {2024}
}
[Bibtex] @inproceedings{C128,
author = {Yang, Jiyue and Graening, Alexander and Romaszkan, Wojciech and Jacob, Vinod K. and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)}},
doi = {},
keywords = {},
month = {June},
pages = {2},
title = {{A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera}},
year = {2024}
}
[Bibtex] @inproceedings{IP19,
author = {Niemier, Michael and Enciso, Zephan and Sharifi, Mohammed Mehdi and Hu, Xiaobo Sharon and O'Conner, Ian and Graening, Alexander and Sharma, Ravit and Gupta, Puneet and Castrillon, Jeronimo and Lima, J.P.C. and Afroze, Nashrah and Khan, Asif and Ryckaert, Julien},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {},
keywords = {chiplets,wsi},
month = {March},
note = {},
pages = {10},
title = {{Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers}},
year = {2024}
}
[Bibtex] @inproceedings{C124,
author = {Graening, Alexander and Pal, Saptadeep and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
doi = {},
keywords = {chiplets,wsi},
month = {July},
note = {},
pages = {6},
title = {{Chiplets: How Small is too Small?}},
year = {2023}
}
[Bibtex] @conference{W22,
author = {Yang, Jiyue and Romaszkan, Wojciech and Graening, Alexander and Jacob, Vinod Kurian and Li, Tianmu and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, event-based camera, accelerator},
title = {{A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications}},
year = {2023}
}
[Bibtex] @conference{W21,
author = {Graening, Alexander and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, event-based camera, accelerator},
title = {{Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing}},
year = {2022}
}
[Bibtex] @inproceedings{C113,
author = {Li, Shurui and Romaszkan, Wojciech and Graening, Alexander and Gupta, Puneet},
booktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},
doi = {},
keywords = {mledge, quantization, systolic array},
month = {March},
note = {},
pages = {},
title = {{SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration}},
year = {2021}
}
Publications
Publications
[1] M. Niemier, Z. Enciso, M. M. Sharifi, X. S. Hu, I. O’Conner, A. Graening, R. Sharma, P. Gupta, J. Castrillon, J. P. C. Lima, N. Afroze, A. Khan, and J. Ryckaert, “Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers,” in IEEE/ACM Design, Automation and Test in Europe, 2024, p. 10
[Bibtex] @inproceedings{IP19,
author = {Niemier, Michael and Enciso, Zephan and Sharifi, Mohammed Mehdi and Hu, Xiaobo Sharon and O'Conner, Ian and Graening, Alexander and Sharma, Ravit and Gupta, Puneet and Castrillon, Jeronimo and Lima, J.P.C. and Afroze, Nashrah and Khan, Asif and Ryckaert, Julien},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {},
keywords = {chiplets,wsi},
month = {March},
note = {},
pages = {10},
title = {{Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers}},
year = {2024}
}
Publications
M.S.
Alumni
Ph.D.
Publications
[1] E. Glukhov, T. Li, V. Gupta, and P. Gupta, “Learned approximate computing: algorithm hardware co-optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
[Bibtex] @article{J79,
author = {Egor Glukhov and Tianmu Li and Vaibhav Gupta and Puneet Gupta},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
title = {Learned Approximate Computing: Algorithm Hardware Co-optimization},
year = {2024}
}
[Bibtex] @article{J74,
author = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
month = {June},
publisher = {{IEEE}},
title = {{REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration}},
year = {2023}
}
[Bibtex] @inproceedings{C123,
author = {Li, Tianmu and Li, Shurui and Gupta, Puneet},
booktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},
doi = {},
keywords = {approximate computing, neural networks, training},
month = {March},
note = {},
pages = {6},
title = {{Training Neural Networks for Execution on Approximate Hardware}},
year = {2023}
}
[Bibtex] @conference{W23,
author = {Li, Tianmu and Romaszkan, Wojciech and Pal, Soumitra and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, CNN, neural networks},
title = {{REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration}},
year = {2023}
}
[Bibtex] @conference{W22,
author = {Yang, Jiyue and Romaszkan, Wojciech and Graening, Alexander and Jacob, Vinod Kurian and Li, Tianmu and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, event-based camera, accelerator},
title = {{A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications}},
year = {2023}
}
[Bibtex] @inproceedings{C121,
author = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{IEEE Asian Solid-State Circuits Conference}},
doi = {},
keywords = {mledge},
month = {November},
note = {},
pages = {2},
title = {{A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor}},
year = {2022}
}
[Bibtex] @inproceedings{C120,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
doi = {},
keywords = {mledge},
month = {October},
note = {Best paper nomination},
pages = {12},
title = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},
year = {2022}
}
[Bibtex] @article{J72,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
doi = {},
keywords = {mledge},
month = {October},
note = {Best paper nomination},
pages = {12},
title = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},
year = {2022}
}
[Bibtex] @article{J70,
author = {Romaszkan, Wojciech and Li, Tianmu and Garg, Rahul and Yang, Jiyue and Pamarti, Sudhakar and Gupta, Puneet},
journal = {{IEEE Solid State Circuits Letters}},
keywords = {mledge},
month = {August},
publisher = {{IEEE}},
title = {{ A 4.4-75 TOPS/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator}},
year = {2022}
}
[Bibtex] @inproceedings{C117,
author = {Gupta, Vaibhav and Li, Tianmu and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {},
keywords = {},
month = {March},
note = {},
pages = {4},
title = {{LAC: Learned Approximate Computing}},
year = {2022}
}
[Bibtex] @conference{W25,
author = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, CNN, neural networks, accelerator},
title = {{A 1.84-7.96TOPS/W 65nm DAC/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply}},
year = {2022}
}
[Bibtex] @article{J69,
author = {Alam, Irina and Li, Tianmu and Brock, Sean and Gupta, Puneet},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
publisher = {{IEEE}},
title = {{DRDebug: Automated Design Rule Debugging}},
year = {2022}
}
[Bibtex] @inproceedings{C112,
author = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {},
keywords = {mledge},
month = {February},
note = {},
pages = {},
title = {{GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks}},
year = {2021}
}
[Bibtex] @conference{W24,
author = {Romaszkan, Wojciech and Li, Tianmu and Yang, Jiyue and Lee, Albert and Wu, Di and Wang, Kang and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, CNN, neural networks},
title = {{Machine Learning at the Edge Using Spintronic Stochastic Computing}},
year = {2021}
}
[Bibtex] @inproceedings{C109,
author = {Romaszkan, Wojciech and Li, Tianmu and Melton, Tristan and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {10.23919/DATE48585.2020.9116289},
keywords = {mledge},
month = {March},
note = {Best paper nomination},
pages = {768-773},
title = {{ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing}},
year = {2020}
}
[Bibtex] @article{J63,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
journal = {{ACM Transactions on Embedded Computing Systems (TECS)}},
keywords = {mledge, 3pxnet},
month = {November},
publisher = {ACM},
title = {{3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning}},
year = {2019}
}
[Bibtex] @inproceedings{C95,
author = {Wang, Shaodi and Pal, Saptadeep and Li, Tianmu and Pan, Andrew and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Chui, Chi On and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
keywords = {mledge,Negative differential resistance, Magnetic tunnel junction, stochastic computing, stochastic bitstream generator, non-volatile computing},
month = {March},
note = {Best paper nomination},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C95_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C95_slides.pdf},
title = {{H}ybrid {VC-MTJ/CMOS} {N}on-volatile {S}tochastic {L}ogic for {E}fficient {C}omputing},
year = {2017}
}
Publications
[1] W. Romaszkan, J. Yang, A. Graening, V. Jacob, J. Sen, S. Pamarti, and P. Gupta, “SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras,” in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024, p. 12
[Bibtex] @inproceedings{C127,
author = {Romaszkan, Wojciech and Yang, Jiyue and Graening, Alexander and Jacob, Vinod and Sen, Jishnu and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
doi = {},
keywords = {},
month = {September},
pages = {12},
title = {{SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras}},
year = {2024}
}
[Bibtex] @inproceedings{C128,
author = {Yang, Jiyue and Graening, Alexander and Romaszkan, Wojciech and Jacob, Vinod K. and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)}},
doi = {},
keywords = {},
month = {June},
pages = {2},
title = {{A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera}},
year = {2024}
}
[Bibtex] @article{J74,
author = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
month = {June},
publisher = {{IEEE}},
title = {{REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration}},
year = {2023}
}
[Bibtex] @conference{W22,
author = {Yang, Jiyue and Romaszkan, Wojciech and Graening, Alexander and Jacob, Vinod Kurian and Li, Tianmu and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, event-based camera, accelerator},
title = {{A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications}},
year = {2023}
}
[Bibtex] @conference{W23,
author = {Li, Tianmu and Romaszkan, Wojciech and Pal, Soumitra and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, CNN, neural networks},
title = {{REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration}},
year = {2023}
}
[Bibtex] @inproceedings{C121,
author = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{IEEE Asian Solid-State Circuits Conference}},
doi = {},
keywords = {mledge},
month = {November},
note = {},
pages = {2},
title = {{A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor}},
year = {2022}
}
[Bibtex] @inproceedings{C120,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
doi = {},
keywords = {mledge},
month = {October},
note = {Best paper nomination},
pages = {12},
title = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},
year = {2022}
}
[Bibtex] @article{J72,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
doi = {},
keywords = {mledge},
month = {October},
note = {Best paper nomination},
pages = {12},
title = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},
year = {2022}
}
[Bibtex] @article{J70,
author = {Romaszkan, Wojciech and Li, Tianmu and Garg, Rahul and Yang, Jiyue and Pamarti, Sudhakar and Gupta, Puneet},
journal = {{IEEE Solid State Circuits Letters}},
keywords = {mledge},
month = {August},
publisher = {{IEEE}},
title = {{ A 4.4-75 TOPS/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator}},
year = {2022}
}
[Bibtex] @conference{W21,
author = {Graening, Alexander and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, event-based camera, accelerator},
title = {{Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing}},
year = {2022}
}
[Bibtex] @conference{W25,
author = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, CNN, neural networks, accelerator},
title = {{A 1.84-7.96TOPS/W 65nm DAC/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply}},
year = {2022}
}
[Bibtex] @inproceedings{C113,
author = {Li, Shurui and Romaszkan, Wojciech and Graening, Alexander and Gupta, Puneet},
booktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},
doi = {},
keywords = {mledge, quantization, systolic array},
month = {March},
note = {},
pages = {},
title = {{SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration}},
year = {2021}
}
[Bibtex] @inproceedings{C112,
author = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {},
keywords = {mledge},
month = {February},
note = {},
pages = {},
title = {{GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks}},
year = {2021}
}
[Bibtex] @conference{W24,
author = {Romaszkan, Wojciech and Li, Tianmu and Yang, Jiyue and Lee, Albert and Wu, Di and Wang, Kang and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{Government Microcircuit Applications and Critical Technolocy Conference (GOMACTech)}},
keywords = {stochastic computing, CNN, neural networks},
title = {{Machine Learning at the Edge Using Spintronic Stochastic Computing}},
year = {2021}
}
[Bibtex] @inproceedings{C109,
author = {Romaszkan, Wojciech and Li, Tianmu and Melton, Tristan and Pamarti, Sudhakar and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
doi = {10.23919/DATE48585.2020.9116289},
keywords = {mledge},
month = {March},
note = {Best paper nomination},
pages = {768-773},
title = {{ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing}},
year = {2020}
}
[Bibtex] @article{J63,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
journal = {{ACM Transactions on Embedded Computing Systems (TECS)}},
keywords = {mledge, 3pxnet},
month = {November},
publisher = {ACM},
title = {{3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning}},
year = {2019}
}
Contact: saptadeep@ucla.edu
Research interests: Design Methodologies and Architectures for System Integration on Next Generation Interconnects, Development of Silicon Interconnect Fabric, Stochastic Computing, Technology Optimization
Industry experience: Nvidia
Last known coordinates: Stealth Mode Startup
PhD Thesis:
- [1] S. Pal, “Scale-out packageless processing,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021.
[Bibtex]
@phdthesis{PHDTH11,
author = {Pal, Saptadeep},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {},
month = {November},
title = {Scale-Out Packageless Processing},
year = {2021}
}
Publications
[1] S. Pal, A. Mallik, and P. Gupta, “System technology co-optimization for advanced integration,” Nature Reviews Electrical Engineering, 2024.
[Bibtex] @article{J80,
author = {Pal, S. and Mallik, A. and Gupta, P},
doi = {10.1038/s44287-024-00078-x},
journal = {{Nature Reviews Electrical Engineering}},
title = {System technology co-optimization for advanced integration},
year = {2024}
}
[Bibtex] @inproceedings{C124,
author = {Graening, Alexander and Pal, Saptadeep and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
doi = {},
keywords = {chiplets,wsi},
month = {July},
note = {},
pages = {6},
title = {{Chiplets: How Small is too Small?}},
year = {2023}
}
[Bibtex] @article{J77,
author = {Newsha Ardalani and Saptadeep Pal and Puneet Gupta},
doi = {10.1145/3635867},
journal = {{ACM Transactions on Design Automation of Electronic Systems}},
title = {DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems},
year = {2023}
}
[Bibtex] @inproceedings{C116,
author = {Pal, Saptadeep and Liu, Jingyang and Alam, Irina and Cebry, Nicholas and Suhail, Haris and Bu, Shi and Iyer, Subramanian S. and Pamarti, Sudhakar and Kumar, Rakesh and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
doi = {},
keywords = {wsi},
month = {December},
note = {},
pages = {},
title = {{Designing a 2048-Chiplet, 14336-Core Waferscale Processor}},
year = {2021}
}
[Bibtex] @phdthesis{PHDTH11,
author = {Pal, Saptadeep},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {},
month = {November},
title = {Scale-Out Packageless Processing},
year = {2021}
}
[Bibtex] @inproceedings{C114,
author = {Pal, Saptadeep and Sahoo, Krutikesh and Alam, Irina and Suhail, Haris and Kumar, Rakesh and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},
booktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},
doi = {},
keywords = {wsi},
month = {June},
note = {},
pages = {},
title = {{I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor}},
year = {2021}
}
[Bibtex] @inproceedings{C111,
address = {New York, NY, USA},
author = {Pal, Saptadeep and Gupta, Puneet},
booktitle = {{System-Level Interconnect - Problems and Pathfinding Workshop}},
keywords = {wsi},
location = {San Diego, California},
month = {November},
numpages = {8},
publisher = {ACM},
series = {SLIP '20},
title = {{Pathfinding for 2.5D Interconnect Technologies}},
year = {2020}
}
[Bibtex] @article{J66,
author = {Pal, Saptadeep and Petrisko, Daniel and Kumar, Rakesh and Gupta, Puneet},
doi = {https://ieeexplore.ieee.org/document/8998304},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {{2.5-D integration, chiplet assembly, micro-architectural design space exploration (DSE), multichiplet optimization, wsi}},
publisher = {{IEEE}},
title = {{Design Space Exploration for Chiplet Assembly Based Processors}},
year = {2020}
}
[Bibtex] @inproceedings{C108,
acmid = {3357533},
address = {New York, NY, USA},
author = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},
booktitle = {{Proceedings of the International Symposium on Memory Systems}},
doi = {10.1145/3357526.3357533},
isbn = {978-1-4503-7206-0},
keywords = {memres},
location = {Washington, District of Columbia},
month = {September},
numpages = {16},
pages = {85--100},
publisher = {ACM},
series = {MEMSYS '19},
title = {{Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},
url = {http://doi.acm.org/10.1145/3357526.3357533},
year = {2019}
}
[Bibtex] @article{J61,
author = {Pal, Saptadeep and Ebrahimi, Eiman and Zulfiqar, Arslan and Fu, Yaosheng and Zhang, Victor and Migacz, Szymon and Nellans, David and Gupta, Puneet},
journal = {{{IEEE Micro}}},
month = {September},
publisher = {IEEE},
title = {{Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training}},
year = {2019}
}
[Bibtex] @inproceedings{C107,
author = {Pal, Saptadeep and Petrisko, Daniel and Tomei, Matthew and Iyer, Subramanian S. and Gupta, Puneet and Kumar, Rakesh},
booktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},
doi = {10.1109/HPCA.2019.00042},
issn = {1530-0897},
keywords = {wsi},
month = {February},
pages = {250-263},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C106_paper.pdf},
title = {{Architecting Waferscale Processors - A GPU Case Study}},
year = {2019}
}
[Bibtex] @inproceedings{C100,
author = {Pal, Saptadeep and Petrisko, Daniel and Bajwa, Adeel and Iyer, Subramanian S. and Kumar, Rakesh and Gupta, Puneet},
booktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},
keywords = {wsi},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C100_paper.pdf},
title = {{A Case for Packageless Processors}},
year = {2018}
}
[Bibtex] @conference{W15,
author = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {memres,compression,ecc,memory,reliability,architecture,coding,systems,stt_ram},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W15_paper.pdf},
title = {{Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},
year = {2018}
}
[Bibtex] @inproceedings{C96,
author = {Jangam, SivaChandra and Pal, Saptadeep and Bajwa, Adeel and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},
booktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},
keywords = {Silicon Interconnect Fabric; Thermal Compression Bonding; Fine Pitch Interconnect, SuperCHIPS, wsi},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C96_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C96_slides.pdf},
title = {{L}atency, {B}andwidth and {P}ower {B}enefits of the {S}uper{CHIPS} {I}ntegration {S}cheme},
year = {2017}
}
[Bibtex] @inproceedings{C95,
author = {Wang, Shaodi and Pal, Saptadeep and Li, Tianmu and Pan, Andrew and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Chui, Chi On and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
keywords = {mledge,Negative differential resistance, Magnetic tunnel junction, stochastic computing, stochastic bitstream generator, non-volatile computing},
month = {March},
note = {Best paper nomination},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C95_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C95_slides.pdf},
title = {{H}ybrid {VC-MTJ/CMOS} {N}on-volatile {S}tochastic {L}ogic for {E}fficient {C}omputing},
year = {2017}
}
[Bibtex] @inproceedings{IP17,
author = {Pal, Saptadeep and Iyer, Subramanian S. and Gupta, Puneet},
booktitle = {{IEEE International Conference on Rebooting Computing}},
keywords = {wsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP17_paper.pdf},
title = {Advanced Packaging and Heterogeneous Integration to Reboot Computing},
year = {2017}
}
[Bibtex] @techreport{MSTR13,
author = {Pal, Saptadeep},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR13_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR13_slides.pdf},
title = {Supervia: Relieving Routing Congestion using Double-height Vias},
year = {2017}
}
Dr. Irina Alam
Research interests: Opportunistic memory architecture for power and performance benefits, Exploring efficient memory error resilience techniques
Industry experience: Micron, Google
Last known coordinates: Apple
PhD Thesis:
- [1] I. Alam, “Lightweight opportunistic memory resilience,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021.
[Bibtex]
@phdthesis{PHDTH10,
author = {Alam, Irina},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {},
month = {August},
title = {Lightweight Opportunistic Memory Resilience},
year = {2021}
}
Publications
[1] I. Alam and P. Gupta, “Achieving dram-like pcm by trading off capacity for latency,” IEEE Transactions on Computers, 2024.
[Bibtex] @article{J78,
author = {Irina Alam and Puneet Gupta},
journal = {{IEEE Transactions on Computers}},
title = {Achieving DRAM-like PCM By Trading Off Capacity For Latency},
year = {2024}
}
[Bibtex] @article{J76,
author = {Lee, Albert and Alam, Irina and Yang, Jiyue and Wu, Di and Pamarti, Sudhakar and Gupta, Puneet and Wang, Kang L.},
doi = {10.1109/TED.2022.3228831},
journal = {{IEEE Transactions on Electron Devices}},
number = {2},
pages = {478-484},
title = {Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory},
volume = {70},
year = {2023}
}
[Bibtex] @inproceedings{C118,
author = {Alam, Irina and Gupta, Puneet},
booktitle = {{IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)}},
doi = {},
keywords = {},
month = {June},
note = {},
pages = {13},
title = {{COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors}},
year = {2022}
}
[Bibtex] @article{J69,
author = {Alam, Irina and Li, Tianmu and Brock, Sean and Gupta, Puneet},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
publisher = {{IEEE}},
title = {{DRDebug: Automated Design Rule Debugging}},
year = {2022}
}
[Bibtex] @inproceedings{C116,
author = {Pal, Saptadeep and Liu, Jingyang and Alam, Irina and Cebry, Nicholas and Suhail, Haris and Bu, Shi and Iyer, Subramanian S. and Pamarti, Sudhakar and Kumar, Rakesh and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
doi = {},
keywords = {wsi},
month = {December},
note = {},
pages = {},
title = {{Designing a 2048-Chiplet, 14336-Core Waferscale Processor}},
year = {2021}
}
[Bibtex] @phdthesis{PHDTH10,
author = {Alam, Irina},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {},
month = {August},
title = {Lightweight Opportunistic Memory Resilience},
year = {2021}
}
[Bibtex] @inproceedings{C114,
author = {Pal, Saptadeep and Sahoo, Krutikesh and Alam, Irina and Suhail, Haris and Kumar, Rakesh and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},
booktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},
doi = {},
keywords = {wsi},
month = {June},
note = {},
pages = {},
title = {{I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor}},
year = {2021}
}
[Bibtex] @inproceedings{C110,
address = {New York, NY, USA},
author = {Alam, Irina and Gupta, Puneet},
booktitle = {{Proceedings of the International Symposium on Memory Systems}},
keywords = {memres},
location = {Washington, District of Columbia},
month = {September},
numpages = {13},
publisher = {ACM},
series = {MEMSYS '20},
title = {{SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge}},
year = {2020}
}
[Bibtex] @incollection{B3,
author = {Alam, Irina and Dolecek, Lara and Gupta, Puneet},
booktitle = {{Dependable Embedded Systems}},
publisher = {Springer},
title = {Lightweight Software-Defined Error Correction for Memories},
year = {2020}
}
[Bibtex] @article{J62,
author = {Schoeny, Clayton and Sala, Frederic and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},
journal = {{IEEE Transactions on Information Theory}},
keywords = {memres},
month = {October},
title = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},
year = {2019}
}
[Bibtex] @inproceedings{C108,
acmid = {3357533},
address = {New York, NY, USA},
author = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},
booktitle = {{Proceedings of the International Symposium on Memory Systems}},
doi = {10.1145/3357526.3357533},
isbn = {978-1-4503-7206-0},
keywords = {memres},
location = {Washington, District of Columbia},
month = {September},
numpages = {16},
pages = {85--100},
publisher = {ACM},
series = {MEMSYS '19},
title = {{Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},
url = {http://doi.acm.org/10.1145/3357526.3357533},
year = {2019}
}
[Bibtex] @inproceedings{C106,
author = {Schoeny, Clayton and Alam, Irina and Gottscho, Mark and Gupta, Puneet and Dolecek, Lara},
booktitle = {{IEEE Information Theory Workshop (ITW)}},
keywords = {memres},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C108_paper.pdf},
title = {{Error Correction and Detection for Computing Memories Using System Side Information}},
year = {2018}
}
[Bibtex] @inproceedings{C104,
author = {Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)}},
keywords = {memres},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C104_paper.pdf},
title = {{Parity++: Lightweight Error Correction for Last Level Caches}},
year = {2018}
}
[Bibtex] @conference{W14,
author = {Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {memres,parity,ecc,memory,reliability,architecture,coding,systems,caches},
note = {Best of SELSE},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W14_paper.pdf},
title = {{Parity++: Lightweight Error Correction for Last Level Caches}},
year = {2018}
}
[Bibtex] @conference{W15,
author = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {memres,compression,ecc,memory,reliability,architecture,coding,systems,stt_ram},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W15_paper.pdf},
title = {{Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},
year = {2018}
}
[Bibtex] @techreport{MSTH4,
author = {Alam, Irina},
institution = {Department of Electrical and Computer Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH4_paper.pdf},
title = {Lightweight Fault Tolerance in SRAM Based On-Chip Memories},
year = {2018}
}
[Bibtex] @inproceedings{C101,
author = {Schoeny, Clayton and Sala, Fredric and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},
booktitle = {{IEEE Information Theory Workshop (ITW)}},
keywords = {memres},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C101_paper.pdf},
title = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},
year = {2017}
}
[Bibtex] @article{J54,
author = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
journal = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},
keywords = {memres},
month = {October},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J54_paper.pdf},
title = {{Low-Cost Memory Fault Tolerance for IoT Devices}},
volume = {},
year = {2017}
}
[Bibtex] @article{C98,
author = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},
keywords = {memres},
month = {October},
note = {Best paper award},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J54_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C98_slides.pptx},
title = {{Low-Cost Memory Fault Tolerance for IoT Devices}},
volume = {},
year = {2017}
}
Dr. Wei-Che Wang
Research interests: Development of computational techniques and models for exploring and optimizing semiconductor technologies.
Last known coordinates: Nvidia
PhD Thesis:
- [1] W. Wang, “Hardware-enabled design for security (dfs) solutions,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2018.
[Bibtex]
@phdthesis{PHDTH9,
author = {Wang, Wei-Che},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH8_paper.pdf},
title = {Hardware-Enabled Design for Security (DFS) Solutions},
year = {2018}
}
Publications
[1] W. Wang, Y. Wu, and P. Gupta, “Reverse Engineering for 2.5D Split Manufactured ICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
[Bibtex] @article{J64,
author = {Wang, Wei-Che and Wu, Yizhang and Gupta, Puneet},
doi = {https://doi.org/10.1109/TCAD.2019.2957359},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
publisher = {{IEEE}},
title = {{Reverse Engineering for 2.5D Split Manufactured ICs}},
year = {2020}
}
[Bibtex] @article{J60,
author = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Diggavi, Suhas and Gupta, Puneet},
journal = {{{IEEE Transactions on Information Forensics and Security}}},
month = {May},
publisher = {IEEE},
title = {{SLATE: A Secure Lightweight Entity Authentication Hardware Primitive}},
year = {2019}
}
[Bibtex] @article{J57,
author = {Wang, Wei-Che and Zhao, Charles and Gupta, Puneet},
issue = {},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
month = {},
title = {{Assessing Layout Density Benefits of Vertical Channel Devices}},
volume = {},
year = {2018}
}
[Bibtex] @phdthesis{PHDTH9,
author = {Wang, Wei-Che},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH8_paper.pdf},
title = {Hardware-Enabled Design for Security (DFS) Solutions},
year = {2018}
}
[Bibtex] @article{J56,
author = {Wang, Wei-Che and Yona, Yair and Diggavi, Suhas and Gupta, Puneet},
journal = {{IEEE Transactions on Information Forensics and Security (TIFS)}},
month = {November},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J56_paper.pdf},
title = {{Design and Analysis of Stability-Guaranteed PUFs}},
volume = {},
year = {2017}
}
[Bibtex] @inproceedings{C99,
author = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Hung, Szu-Yao and Diggavi, Suhas and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST)}},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C99_paper.pdf},
title = {{Implementation of Stable PUFs Using Gate Oxide Breakdown}},
year = {2017}
}
[Bibtex] @inproceedings{C94,
author = {Wang, Wei-Che and Yona, Yair and Diggavi, Suhas and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Hardware Oriented Security and Trust (HOST)}},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C94_paper.pdf},
title = {{LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity}},
year = {2016}
}
[Bibtex] @article{J41,
author = {Wang, Wei-Che and Gupta, Puneet},
issue = {},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J41_paper.pdf},
title = {{Efficient Layout Generation and Design Evaluation of Vertical Channel Devices}},
volume = {},
year = {2016}
}
[Bibtex] @inproceedings{C81,
author = {Wang, Wei-Che and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C81},
keywords = {dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C81_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C81_slides.pdf},
title = {{E}fficient {L}ayout {G}eneration and {E}valuation of {V}ertical {C}hannel {D}evices},
year = {2014}
}
Dr. Yasmine Badr
Contact: ybadr AT ucla DOT edu
Research interests: Algorithms and Computational methods for Design and Technology Co-optimization
Last known coordinates: Meta
PhD Thesis:
- [1] Y. Badr, “Co-optimization of restrictive patterning technologies and design,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.
[Bibtex]
@phdthesis{PHDTH8,
author = {Badr, Yasmine},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH8_paper.pdf},
title = {Co-optimization of Restrictive Patterning Technologies and Design},
year = {2017}
}
Publications
[1] A. Deng, Y. Badr, and P. Gupta, “Dynamic programming approach to adaptive slicing for optimization under a global volumetric error constraint,” in SPIE Laser 3D Manufacturing V, 2018
[Bibtex] @inproceedings{C102,
author = {Deng, Andrew and Badr, Yasmine and Gupta, Puneet},
booktitle = {{SPIE Laser 3D Manufacturing V}},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C102_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C102_slides.pptx},
title = {Dynamic programming approach to adaptive slicing for optimization under a global volumetric error constraint},
year = {2018}
}
[Bibtex] @inproceedings{C97,
author = {Badr, Yasmine and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C97_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C97_slides.pdf},
title = {{T}echnology {P}ath-finding for {D}irected {S}elf-assembly for {V}ia {L}ayers"},
year = {2017}
}
[Bibtex] @article{J52,
author = {Badr, Yasmine and Gupta, Puneet},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J52_paper.pdf},
title = {Technology path-finding framework for directed-self assembly for via layers},
year = {2017}
}
[Bibtex] @phdthesis{PHDTH8,
author = {Badr, Yasmine},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH8_paper.pdf},
title = {Co-optimization of Restrictive Patterning Technologies and Design},
year = {2017}
}
[Bibtex] @article{J48,
author = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},
category = {J48},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J48_paper.pdf},
title = {{M}ask {A}ssignment and {D}SA {G}rouping for {DSA-MP} {H}ybrid {L}ithography for sub-7nm {C}ontact/{V}ia {H}oles},
year = {2016}
}
[Bibtex] @article{J45,
author = {Zhu, Liheng and Badr, Yasmine and Wang, Shaodi and Iyer, Subramanian and Gupta, Puneet},
category = {J45},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J45_paper.pdf},
title = {Assessing {B}enefits of a {B}uried {I}nterconnect {L}ayer in {D}igital {D}esigns},
year = {2016}
}
[Bibtex] @inproceedings{C86,
author = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C86_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C86_slides.pdf},
title = { {M}ask {A}ssignment and {S}ynthesis of {DSA}-{MP} {H}ybrid {L}ithography for sub-7nm {C}ontacts/{V}ias},
year = {2015}
}
[Bibtex] @inproceedings{C85,
author = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C85_paper.pdf},
title = { {I}ncorporating {DSA} in {m}ultipatterning {s}emiconductor {m}anufacturing {t}echnologies},
year = {2015}
}
[Bibtex] @inproceedings{C78,
author = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C78_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C78_slides.pdf},
title = {{L}ayout {P}attern-driven {D}esign {R}ule {E}valuation},
year = {2014}
}
[Bibtex] @inproceedings{C74,
author = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,dre},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_slides.pdf},
title = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},
year = {2014}
}
[Bibtex] @inproceedings{IP16,
author = { Ghaida, Rani S. and Badr, Yasmine and Gupta, Puneet},
booktitle = {{Proc. IEEE International Conference on Computer Design}},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP16_paper.pdf},
title = {Pattern-restricted design at 10nm and beyond},
year = {2014}
}
[Bibtex] @article{J36,
author = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J36_paper.pdf},
title = {Layout Pattern-driven Design Rule Evaluation},
year = {2014}
}
Dr. Mark Gottscho
Contact: mgottscho@ucla.edu
Research interests: Opportunistic memory architectures and systems in presence of variability.
Last known coordinates: SambaNova Systems
PhD Thesis:
- [1] M. W. Gottscho, “Opportunistic memory systems in presence of hardware variability,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.
[Bibtex]
@phdthesis{PHDTH7,
author = {Gottscho, Mark William},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {computer architecture, memory systems, variation-aware, hardware/software interface, reliability, error-correcting codes, caches, scratchpads, SRAM, DRAM, supercomputers, IoT, embedded systems, electronic design auomation, CAD, EDA, operating systems, Linux, tools, benchmarks, resiliency, approximate computing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH7_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH7_slides.pdf},
title = {Opportunistic Memory Systems in Presence of Hardware Variability},
year = {2017}
}
Publications
[1] C. Schoeny, F. Sala, M. Gottscho, I. Alam, P. Gupta, and L. Dolecek, “Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories,” IEEE Transactions on Information Theory, 2019.
[Bibtex] @article{J62,
author = {Schoeny, Clayton and Sala, Frederic and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},
journal = {{IEEE Transactions on Information Theory}},
keywords = {memres},
month = {October},
title = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},
year = {2019}
}
[Bibtex] @inproceedings{C106,
author = {Schoeny, Clayton and Alam, Irina and Gottscho, Mark and Gupta, Puneet and Dolecek, Lara},
booktitle = {{IEEE Information Theory Workshop (ITW)}},
keywords = {memres},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C108_paper.pdf},
title = {{Error Correction and Detection for Computing Memories Using System Side Information}},
year = {2018}
}
[Bibtex] @inproceedings{C101,
author = {Schoeny, Clayton and Sala, Fredric and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},
booktitle = {{IEEE Information Theory Workshop (ITW)}},
keywords = {memres},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C101_paper.pdf},
title = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},
year = {2017}
}
[Bibtex] @article{J54,
author = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
journal = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},
keywords = {memres},
month = {October},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J54_paper.pdf},
title = {{Low-Cost Memory Fault Tolerance for IoT Devices}},
volume = {},
year = {2017}
}
[Bibtex] @article{C98,
author = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},
keywords = {memres},
month = {October},
note = {Best paper award},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J54_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C98_slides.pptx},
title = {{Low-Cost Memory Fault Tolerance for IoT Devices}},
volume = {},
year = {2017}
}
[Bibtex] @phdthesis{PHDTH7,
author = {Gottscho, Mark William},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {computer architecture, memory systems, variation-aware, hardware/software interface, reliability, error-correcting codes, caches, scratchpads, SRAM, DRAM, supercomputers, IoT, embedded systems, electronic design auomation, CAD, EDA, operating systems, Linux, tools, benchmarks, resiliency, approximate computing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH7_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH7_slides.pdf},
title = {Opportunistic Memory Systems in Presence of Hardware Variability},
year = {2017}
}
[Bibtex] @article{J46,
author = {Gottscho, Mark and Shoaib, Mohammed and Govindan, Sriram and Sharma, Bikash and Wang, Di and Gupta, Puneet},
issue = {},
journal = {{IEEE Computer Architecture Letters (CAL)}},
keywords = {memres},
month = {August},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J46_paper.pdf},
title = {{Measuring the Impact of Memory Errors on Application Performance}},
volume = {},
year = {2016}
}
[Bibtex] @conference{C93,
author = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)}},
keywords = {ecc,memory,reliability,architecture,coding,systems,dram,caches,memres},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_slides.pptx},
title = {{Software-Defined Error-Correcting Codes}},
year = {2016}
}
[Bibtex] @inproceedings{C91,
author = {Gottscho, Mark and Govindan, Sriram and Sharma, Bikash and Shoaib, Mohammed and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)}},
keywords = {},
month = {April},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C91_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C91_slides.pdf},
title = {{X}-{M}em: {A} {C}ross-{P}latform and {E}xtensible {M}emory {C}haracterization {T}ool for the {C}loud},
year = {2016}
}
[Bibtex] @inproceedings{C89,
author = {Zhang, Qixiang and Lai, Liangzhen and Gottscho, Mark and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C89_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C89_slides.pptx},
title = {{M}ulti-{S}tory {P}ower {D}istribution {N}etworks for {GPU}s},
year = {2016}
}
[Bibtex] @conference{W13,
author = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {memres,hsi,ecc,memory,reliability,architecture,coding,systems,dram,caches},
note = {Best Paper Award},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W13_slides.pptx},
title = {{Software-Defined Error-Correcting Codes}},
year = {2016}
}
[Bibtex] @article{J39,
author = {Gottscho, Mark and BanaiyanMofrad, Abbas and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},
issue = {3},
journal = {{ACM Transactions on Architecture and Code Optimization (TACO)}},
month = {August},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J39_paper.pdf},
title = {{DPCS}: {D}ynamic {P}ower/{C}apacity {S}caling for {SRAM} {C}aches in the {N}anoscale {E}ra},
volume = {12},
year = {2015}
}
[Bibtex] @article{J38,
author = {Wanner, Lucas and Lai, Liangzhen and Rahimi, Abbas and Gottscho, Mark and Mercati, Pietro and Huang, Chu-Hsiang and Sala, Frederic and Agarwal, Yuvraj and Dolecek, Lara and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh and Jhala, Ranjit and Kumar, Rakesh and Lerner, Sorin and Mitra Subhasish and Nicolau, Alexandru and Rosing, Tajana Simunic and Srivastava, Mani B. and Swanson, Steve and Sylvester, Dennis and Zhou, Yuanyuan},
issue = {3},
journal = {{De Gruyter Information Technology (it)}},
month = {June},
pages = {181-198},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J38_paper.pdf},
title = {{NSF} {E}xpedition on {V}ariability-{A}ware {S}oftware: {R}ecent {R}esults and {C}ontributions},
volume = {57},
year = {2015}
}
[Bibtex] @article{J33,
author = {Gottscho, Mark and Bathen, Luis A. D. and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},
issue = {5},
journal = {{IEEE Transactions on Computers}},
keywords = {DRAM, variability, energy-aware systems, main memory, allocation/deallocation strategies, operating systems},
month = {May},
pages = {1483--1496},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J33_paper.pdf},
title = {{V}i{P}{Z}on{E}: {H}ardware {P}ower {V}ariability-{A}ware {V}irtual {M}emory {M}anagement for {E}nergy {S}avings},
volume = {64},
year = {2015}
}
[Bibtex] @inproceedings{C82,
author = {Elmalaki, Salma and Gottscho, Mark and Gupta, Puneet and Srivastava, Mani},
booktitle = {{USENIX Workshop on Power-Aware Computing and Systems (HotPower)}},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C82_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C82_slides.pdf},
title = {{A} {C}ase for {B}attery {C}harging-{A}ware {P}ower {M}anagement and {D}eferrable {T}ask {S}cheduling in {S}martphones},
year = {2014}
}
[Bibtex] @inproceedings{IP14,
author = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and BanaiyanMofrad, Abbas and Gottscho, Mark and Shoushtari, Majid},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP14_paper.pdf},
title = {{M}ulti-{L}ayer {M}emory {R}esiliency},
year = {2014}
}
[Bibtex] @inproceedings{C79,
author = {Gottscho, Mark and Banaiyan, Mofrad, Abbas and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {memres},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C79_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C79_slides.pdf},
title = {{P}ower / {C}apacity {S}caling: {E}nergy {S}avings {W}ith {S}imple {F}ault-{T}olerant {C}aches},
year = {2014}
}
[Bibtex] @techreport{MSTR10,
author = {Gottscho, Mark},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR10_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR10_slides.pdf},
title = {{V}i{P}{Z}on{E}: {E}xploiting {DRAM} {P}ower {V}ariability for {E}nergy {S}avings in {L}inux x86-64},
year = {2014}
}
[Bibtex] @inproceedings{IP10,
author = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and Bathen, Luis and Gottscho, Mark},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {hsi, variability, memory, dram, uno},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP10_paper.pdf},
title = {{V}ariability-{A}ware {M}emory {M}anagement for {N}anoscale {C}omputing},
year = {2013}
}
[Bibtex] @inproceedings{C65,
author = {Bathen, Luis and Gottscho, Mark and Dutt, Nikil and Gupta, Puneet and Nicolau, Alex},
booktitle = {{ACM International Conference on Hardware/Software Codesign and System Synthesis}},
category = {C65},
keywords = {hsi, vipzone, os, variability, variability-aware, dram, memory, power, zone, zoning, allocation},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C65_paper.pdf},
title = {{V}i{P}{Z}on{E}: {O}{S}-{L}evel {M}emory {V}ariability-{A}ware {P}hysical {A}ddress {Z}oning for {E}nergy {S}avings},
year = {2012}
}
[Bibtex] @article{J20,
author = {Gottscho, Mark and Kagalwalla, Abde Ali and Gupta, Puneet},
issue = {2},
journal = {{IEEE Embedded Systems Letters}},
keywords = {DRAM, DDR3, power, variability, hsi},
pages = {37--40},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J20_paper.pdf},
title = {{P}ower {V}ariability in {C}ontemporary {DRAM}s},
volume = {4},
year = {2012}
}
[Bibtex] @techreport{UG5,
author = {Gottscho, Mark},
institution = {University of California, Los Angeles},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/UG2_paper.pdf},
title = {Analyzing Power Variability of DDR3 Dual Inline Memory Modules},
year = {2011}
}
Dr. Shaodi Wang
Contact: shaodiwang AT g DOT ucla DOT edu
Research interests: Design for manufacturing modeling, novel device modeling and circuit analysis.
Last known coordinates:
PhD Thesis:
- [1] S. Wang, “Design, evaluation and co-optimization of emerging devices and circuits,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.
[Bibtex]
@phdthesis{PHDTH6,
author = {Wang, Shaodi},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {emerging technology, emerging device, emerging memory, MRAM, TFET, negative differential resistance, optimization, evaluation, stochastic computing, non-volatile memory, memory reliability},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH6_paper.pdf},
title = {Design, Evaluation and Co-optimization of Emerging Devices and Circuits},
year = {2017}
}
Publications
[1] P. Gupta, A. Pan, and S. Wang, Memory write and read assistance using negative differential resistance devices, 2020.
[Bibtex] @misc{P18,
author = {P. Gupta and A. Pan and S. Wang},
howpublished = {U.S. Patent No. 10,832,752},
title = {Memory write and read assistance using negative differential resistance devices},
year = {2020}
}
[Bibtex] @article{J59,
author = {Wang, Shaodi and Lee, Hochul and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Gupta, Puneet},
journal = {{Transactions on Emerging Topics in Computing}},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J59_paper.pdf},
title = {{Adaptive MRAM Write and Read with MTJ Variation Monitor}},
year = {2018}
}
[Bibtex] @article{J58,
author = {H. Lee and A. Lee and S. Wang and F. Ebrahimi and P. Gupta and P.K. Amiri and K.L. Wang},
journal = {{IEEE Transactions on Magnetics}},
title = {{Analysis and Compact Modeling of Magnetic Tunner Junctions Using Voltage-Controlled Magnetic Anisotropy}},
year = {2018}
}
[Bibtex] @inproceedings{C95,
author = {Wang, Shaodi and Pal, Saptadeep and Li, Tianmu and Pan, Andrew and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Chui, Chi On and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
keywords = {mledge,Negative differential resistance, Magnetic tunnel junction, stochastic computing, stochastic bitstream generator, non-volatile computing},
month = {March},
note = {Best paper nomination},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C95_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C95_slides.pdf},
title = {{H}ybrid {VC-MTJ/CMOS} {N}on-volatile {S}tochastic {L}ogic for {E}fficient {C}omputing},
year = {2017}
}
[Bibtex] @article{J51,
author = {Lee, Hochul and Lee, Albert and Wang, Shaodi and Ebrahimi, Farbod and Gupta, Puneet and Amiri, P. Khalili and Wang, Kang L.},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {},
month = {March},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J51_paper.pdf},
title = {{A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory}},
volume = {},
year = {2017}
}
[Bibtex] @phdthesis{PHDTH6,
author = {Wang, Shaodi},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {emerging technology, emerging device, emerging memory, MRAM, TFET, negative differential resistance, optimization, evaluation, stochastic computing, non-volatile memory, memory reliability},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH6_paper.pdf},
title = {Design, Evaluation and Co-optimization of Emerging Devices and Circuits},
year = {2017}
}
[Bibtex] @article{J49,
author = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
issue = {1},
journal = {{IEEE Transactions on Electronic Devices}},
keywords = {Negative differential resistance, Magnetic tunnel junction, Magnetic random access memory, MRAM, read, write termination},
month = {1},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J49_paper.pdf},
title = {{Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operation}},
volume = {64},
year = {2017}
}
[Bibtex] @article{J50,
author = {Grezes, Cecile and Lee, Hochul and Lee, Albert and Wang, Shaodi and Ebrahimi, Farbod and Li, Xiang and Wong, Kin and Hu, Qi and Gupta, Puneet and Amiri, P. Khalili and Wang, Kang L.},
journal = {{IEEE Magnetic Letters}},
keywords = {},
month = {},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J50_paper.pdf},
title = {{Write Error Rate and Read Disturbance in Electric-Field-Controlled MRAM}},
volume = {8},
year = {2017}
}
[Bibtex] @article{J55,
author = {Wang, Shaodi and Pan, Andrew and Grezes, Cecile and Amiri, Pedram and Chui, Chi On and Gupta, Puneet},
journal = {{IEEE Transactions on Electronic Devices}},
keywords = {Negative differential resistance, Magnetic tunnel junction, Magnetic random access memory, MRAM, read, write termination},
month = {8},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J55_paper.pdf},
title = {{Leveraging NMOS Negative Differential Resistance
for Low Power, High Reliability Magnetic Memory}},
volume = {PP},
year = {2017}
}
[Bibtex] @article{J47,
author = { Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},
issue = {4},
journal = {{IEEE Transactions on Reliability}},
keywords = {Memory fault, memory reliability, simulator, reliability management, memory page retirement, sparing, memory mirroring, STT-RAM, MRAM, write error, retention error},
month = {October},
pages = {1783-1797},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J47_paper.pdf},
title = {{MEMRES}: {A} {F}ast {M}emory {S}ystem {R}eliability {S}imulator},
volume = {65},
year = {2016}
}
[Bibtex] @article{J42,
author = {Wang, Shaodi and Lee, Hochul and Ebrahimi, Farbod and Amiri, P. Khalili and Wang, Kang L. and Gupta, Puneet},
journal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},
keywords = {STT-RAM, MeRAM, MTJ, process variation, write error rate, MTJ Model},
month = {June},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J42_paper.pdf},
title = {{C}omparative {E}valuation of {S}pin-{T}ransfer-{T}orque and {M}agnetoelectric {R}andom {A}ccess {M}emory},
volume = {},
year = {2016}
}
[Bibtex] @inproceedings{C92,
author = {Wang, Shaodi and Lee, Hochul and Grezes, Cecile and Khalili, Pedram and Wang, Kang L. and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {MRAM},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C92_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C92_slides.pdf},
title = { {MTJ} {V}ariation {M}onitor-assisted {A}daptive {MRAM} {W}rite},
year = {2016}
}
[Bibtex] @article{J45,
author = {Zhu, Liheng and Badr, Yasmine and Wang, Shaodi and Iyer, Subramanian and Gupta, Puneet},
category = {J45},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J45_paper.pdf},
title = {Assessing {B}enefits of a {B}uried {I}nterconnect {L}ayer in {D}igital {D}esigns},
year = {2016}
}
[Bibtex] @article{J40,
author = {Leung, Greg and Wang, Shaodi and Pan, Andrew and Gupta, Puneet and Chui, Chi On},
issue = {},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J40_paper.pdf},
title = {{A}n {E}valuation {F}ramework for {N}anotransfer {P}rinting {B}ased {F}eature-{L}evel {H}eterogeneous {I}ntegration in {VLSI} {C}ircuits},
volume = {},
year = {2016}
}
[Bibtex] @article{J43,
author = { Lee, Hochul and Grezes, Cecile and Wang, Shaodi and Amiri, P. Khalili and Gupta, Puneet and Wang, Kang L.},
journal = {{IEEE Magnetics Letters}},
keywords = {MeRAM, MTJ, read disturbance, source line sensing, sensing scheme},
month = {},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J43_paper.pdf},
title = {A {S}ource {L}ine {S}ensing ({SLS}) {S}cheme in {M}agnetoelectric {R}andom {A}ccess {M}emory ({MeRAM}) for {R}educing {R}ead {D}isturbance and {I}mproving {S}ensing {M}argin},
volume = {7},
year = {2016}
}
[Bibtex] @conference{W12,
author = {Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},
booktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},
keywords = {hsi, MEMRES, memory faults},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W12_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W12_slides.pptx},
title = {{MEMRES: A Fast Memory System Reliability Simulator}},
year = {2015}
}
[Bibtex] @article{J37,
author = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {Emerging device, evaluator, proceed },
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J37_paper.pdf},
title = {PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices},
year = {2015}
}
[Bibtex] @inproceedings{C75,
author = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,proceed},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C75_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C75_slides.pptx},
title = {{PROCEED:} A {P}areto {O}ptimization-based {C}ircuit-level {E}valuator for {E}merging {D}evices},
year = {2014}
}
[Bibtex] @article{J29,
author = {Wang, Shaodi and Leung, Greg and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
journal = {{IEEE Transactions on Electronic Devices}},
keywords = {variability},
month = {July },
number = {7},
pages = {2186 - 2193},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J29_paper.pdf},
title = {{E}valuation of {D}igital {C}ircuit-{L}evel {V}ariability in {I}nversion-{M}ode and {J}unctionless {F}inFET {T}echnologies},
volume = {60},
year = {2013}
}
Dr. Liangzhen Lai
Contact: liangzhen AT ucla DOT edu
Last known coordinates: Facebook
PhD Thesis:
- [1] L. Lai, “Cross-layer approaches for monitoring, margining and mitigation of circuit variability,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2015.
[Bibtex]
@phdthesis{PHDTH5,
author = {Lai, Liangzhen},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH5_paper.pdf},
title = {Cross-Layer Approaches for Monitoring, Margining and Mitigation of Circuit Variability},
year = {2015}
}
Publications
[1] L. Lai and P. Gupta, “System-level Dynamic Variation Margining in Presence of Monitoring and Actuation,” IEEE Embedded System Letters, 2017.
[Bibtex] @article{J53,
author = {Lai, Liangzhen and Gupta, Puneet},
journal = {{IEEE Embedded System Letters}},
keywords = {Monitoring, Temperature measurement, Temperature sensors, Actuators, Power system dynamics, Aging, Clocks},
month = {June},
number = {},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J53_paper.pdf},
title = {{System-level Dynamic Variation Margining in Presence of Monitoring and Actuation}},
volume = {},
year = {2017}
}
[Bibtex] @inproceedings{C89,
author = {Zhang, Qixiang and Lai, Liangzhen and Gottscho, Mark and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C89_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C89_slides.pptx},
title = {{M}ulti-{S}tory {P}ower {D}istribution {N}etworks for {GPU}s},
year = {2016}
}
[Bibtex] @inproceedings{C90,
author = {Lai, Liangzhen and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {hsi},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C90_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C90_slides.pptx},
title = {{H}ardware {R}eliability {M}argining for the {D}ark {S}ilicon {E}ra},
year = {2016}
}
[Bibtex] @inproceedings{C88,
author = {Lai, Liangzhen and Chandra, Vikas and Gupta, Puneet},
booktitle = {{ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)}},
keywords = {hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C88_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C88_slides.pdf},
title = {{E}valuating and {E}xploiting {I}mpacts of {D}ynamic {P}ower {M}anagement {S}chemes on {S}ystem {R}eliability},
year = {2015}
}
[Bibtex] @article{J38,
author = {Wanner, Lucas and Lai, Liangzhen and Rahimi, Abbas and Gottscho, Mark and Mercati, Pietro and Huang, Chu-Hsiang and Sala, Frederic and Agarwal, Yuvraj and Dolecek, Lara and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh and Jhala, Ranjit and Kumar, Rakesh and Lerner, Sorin and Mitra Subhasish and Nicolau, Alexandru and Rosing, Tajana Simunic and Srivastava, Mani B. and Swanson, Steve and Sylvester, Dennis and Zhou, Yuanyuan},
issue = {3},
journal = {{De Gruyter Information Technology (it)}},
month = {June},
pages = {181-198},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J38_paper.pdf},
title = {{NSF} {E}xpedition on {V}ariability-{A}ware {S}oftware: {R}ecent {R}esults and {C}ontributions},
volume = {57},
year = {2015}
}
[Bibtex] @phdthesis{PHDTH5,
author = {Lai, Liangzhen},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH5_paper.pdf},
title = {Cross-Layer Approaches for Monitoring, Margining and Mitigation of Circuit Variability},
year = {2015}
}
[Bibtex] @article{J34,
author = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {hsi},
month = {Aug},
number = {8},
pages = {1168-1179},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J34_paper.pdf},
title = {{S}lack{P}robe: {A} {F}lexible and {E}fficient {I}n {S}itu {T}iming {S}lack {M}onitoring {M}ethodology},
volume = {33},
year = {2014}
}
[Bibtex] @article{J32,
author = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},
journal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},
keywords = {hsi, NBTI},
month = {June},
number = {2},
pages = {180-189},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J32_paper.pdf},
title = {{B}{T}{I}-{G}ater: {A}n {A}ging-{R}esilient {C}lock {G}ating {M}ethodology},
volume = {4},
year = {2014}
}
[Bibtex] @inproceedings{IP13,
author = {Lai, Liangzhen and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {hsi},
month = {Jan},
pages = {467-473},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP13_paper.pdf},
title = {Accurate and inexpensive performance monitoring for variability-aware systems},
year = {2014}
}
[Bibtex] @techreport{TECHRP3,
author = {Lai, Liangzhen and Gupta, Puneet},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/3967v8hw},
title = {A Case Study of Logic Delay Fault Behaviors on General-Purpose Embedded Processor Under Voltage Overscaling},
year = {2014}
}
[Bibtex] @techreport{TECHRP2,
author = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/5898p020},
title = {Exploring Total Power Saving from High Temperature of Server Operations},
year = {2014}
}
[Bibtex] @techreport{TECHRP1,
author = {Agarwal, Yuvraj and Bishop, Alex and Chan, Tuck-Boon and Fotjik, Matt and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen and Martin, Paul and Srivastava, Mani and Sylvester, Dennis and Wanner, Lucas and Zhang, Bing},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/1c21g217},
title = {Redcooper: Hardware sensor enabled variability software testbed for lifetime energy constrained application},
year = {2014}
}
[Bibtex] @article{TR1,
author = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},
keywords = {hsi},
paperurl = {http://escholarship.org/uc/item/5898p020},
title = {Exploring Total Power Saving from High Temperature of Server Operations},
year = {2014}
}
[Bibtex] @inproceedings{C70,
author = {Wanner, Lucas and Elmalaki, Salma and Lai, Liangzhen and Gupta, Puneet and Srivastava, Mani},
booktitle = {{ACM International Conference on Hardware/Software Codesign and System Synthesis}},
category = {C70},
keywords = {hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C70_paper.pdf},
title = {{V}ar{E}{M}{U}: {A}n {E}mulation {T}estbed for {V}ariability-{A}ware {S}oftware},
year = {2013}
}
[Bibtex] @inproceedings{C68,
author = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
catetory = {C68},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C68_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C68_slides.pdf},
title = {{S}lack{P}robe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology},
year = {2013}
}
[Bibtex] @article{J31,
author = {Chan, Tuck-Boon and Gupta, Puneet and Kahng, A. B. and Lai, Liangzhen},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi, DDRO},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J31_paper.pdf},
title = {{S}ynthesis and {A}nalysis of {D}esign-{D}ependent {R}ing {O}scillator ({D}{D}{R}{O}) {P}erformance {M}onitors},
year = {2013}
}
[Bibtex] @article{J22,
author = {Leung, Greg and Lai, Liangzhen and Gupta, Puneet and Chui, Chi On},
journal = {{IEEE Transactions on Electronic Devices}},
keywords = {variability},
month = {aug. },
number = {8},
pages = {2057 -2063},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J22_paper.pdf},
title = {{D}evice- and {C}ircuit-{L}evel {V}ariability {C}aused
by {L}ine {E}dge {R}oughness for {S}ub-32nm {F}inFET {T}echnologies},
volume = {59},
year = {2012}
}
[Bibtex] @inproceedings{C60,
author = {Chan, Tuck Boon and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen},
booktitle = {{ISQED}},
category = {C60},
keywords = {hsi, DDRO},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C60_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C60_slides.pdf},
title = {{DDRO}: A {N}ovel {P}erformance {M}onitoring {M}ethodology {B}ased on {D}esign-{D}ependent {R}ing {O}scillators},
year = {2012}
}
Dr. Abde Ali Kagalwalla
Contact: abdeali AT ucla DOT edu
Research interests: Computer-Aided Design of VLSI Systems, Design-for-Manufacturability, Layout Optimization, Lithography
Last known coordinates: Intel
Phd Thesis:
- [1] A. A. Kagalwalla, “Computational methods for design-assisted mask flows,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2014.
[Bibtex]
@phdthesis{PHDTH4,
author = {Kagalwalla, Abde Ali},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH4_paper.pdf},
title = {Computational Methods for Design-Assisted Mask Flows},
year = {2014}
}
Publications
[1] T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, and A. B. Kahng, “Benchmarking of Mask Fracturing Heuristics,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016
[Bibtex] @inproceedings{J44,
author = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. },
booktitle = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
category = {J44},
keywords = {dats},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J44_paper.pdf},
title = {Benchmarking of {M}ask {F}racturing {H}euristics},
year = {2016}
}
[Bibtex] @inproceedings{C87,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C87_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C87_slides.pptx},
title = { {E}ffective {M}odel-{B}ased {M}ask {F}racturing for {M}ask {C}ost {R}eduction},
year = {2015}
}
[Bibtex] @inproceedings{C80,
author = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. and Sahouria, Emile},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C80},
keywords = {dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C80_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C80_slides.pdf},
title = {Benchmarking of {M}ask {F}racturing {H}euristics},
year = {2014}
}
[Bibtex] @inproceedings{C77,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C77_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C77_slides.pdf},
title = {{C}omprehensive {D}efect {A}voidance {F}ramework for {M}itigating {EUV} {M}ask {D}efects},
year = {2014}
}
[Bibtex] @inproceedings{C73,
author = {Kagalwalla, Abde Ali and Lam, Michael and Adam, Kostas and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C73_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C73_slides.pdf},
title = {{EUV-CDA}: {P}attern {S}hift {A}ware {C}ritical {D}ensity {A}nalysis for {EUV} {M}ask {L}ayouts},
year = {2014}
}
[Bibtex] @phdthesis{PHDTH4,
author = {Kagalwalla, Abde Ali},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH4_paper.pdf},
title = {Computational Methods for Design-Assisted Mask Flows},
year = {2014}
}
[Bibtex] @article{J35,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
doi = {10.1117/1.JMM.13.4.043005},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
number = {4},
pages = {043005},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J35_paper.pdf},
title = {Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects},
volume = {13},
year = {2014}
}
[Bibtex] @article{J28,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
issue = {1},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J28_paper.pdf},
title = {{Design-Aware Defect-Avoidance Floorplanning of EUV Masks}},
volume = {26},
year = {2013}
}
[Bibtex] @inproceedings{C62,
author = {Kagalwalla, Abde Ali and Muddu, Swamy and Capodieci, Luigi and Zelnik, Coby and Gupta, Puneet },
booktitle = {{SPIE Advanced Lithography}},
category = {C62},
keywords = {Design Rules, DOE, dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C62_paper.pdf},
title = {{D}esign-of-{E}xperiments {B}ased {D}esign {R}ule {O}ptimization},
year = {2012}
}
[Bibtex] @article{J18,
author = {Kagalwalla, Abde Ali and Puneet Gupta and Progler, Chris and McDonald, Steve},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J18_paper.pdf},
title = {Design-{A}ware {M}ask {I}nspection},
year = {2012}
}
[Bibtex] @article{J20,
author = {Gottscho, Mark and Kagalwalla, Abde Ali and Gupta, Puneet},
issue = {2},
journal = {{IEEE Embedded Systems Letters}},
keywords = {DRAM, DDR3, power, variability, hsi},
pages = {37--40},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J20_paper.pdf},
title = {{P}ower {V}ariability in {C}ontemporary {DRAM}s},
volume = {4},
year = {2012}
}
[Bibtex] @inproceedings{C57,
author = {Kagalwalla, Abde Ali and Gupta, Puneet and Hur, Duck-Hyung and Park, Chul-Hong },
booktitle = {{SPIE Advanced Lithography}},
category = {C57},
keywords = {EUV, floorplanning, dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C57_paper.pdf},
title = {{D}efect-aware {R}eticle {F}loorplanning for {EUV} {M}asks},
year = {2011}
}
[Bibtex] @article{J15,
author = {Chan, T.B. and Kagalwalla, Abde Ali and Gupta, P. },
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J15_paper.pdf},
title = {{M}easurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},
year = {2011}
}
[Bibtex] @inproceedings{IP7,
author = {A.R. Neureuther and J. Rubinstein and M. Miller and K. Yamazoeand E. Chin and C. Levy and L. Wang and N. Xu and C. Spanos and K. Qian and K. Poolla and J. Ghan and A. Subramanian and T.-J. K. Liu and X. Sun and K. Jeong and and P. Gupta and Kagalwalla, Abde Ali and Ghaida, R. S. and T.-B. Chan},
booktitle = {{Proc. SPIE Photomask and Next-Generation Lithography Mask Technology}},
category = {IP7},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/pmj11.pdf},
title = {Collaborative research on emerging technologies and design},
year = {2011}
}
[Bibtex] @techreport{MSTH2,
author = {Kagalwalla, Abde Ali},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH2_paper.pdf},
title = {Design-Aware Mask Manufacturing},
year = {2011}
}
[Bibtex] @inproceedings{C52,
author = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C52},
keywords = {mask manufacturing, inspection, dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C52_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C52_slides.pdf},
title = {{D}esign-aware {M}ask {I}nspection},
year = {2010}
}
[Bibtex] @inproceedings{C46,
author = {Chan, T.-B. and Kagalwalla, Abde Ali and Gupta, P.},
booktitle = {{Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration}},
category = {C46},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C46_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C46_slides.pdf},
title = {Measurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},
year = {2010}
}
[Bibtex] @conference{W6,
author = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W6},
keywords = {dats},
title = {{D}esign-aware {M}ask {I}nspection},
year = {2010}
}
Dr. Rani S. Ghaida
Contact: ranighaida AT ucla DOT edu
Last known coordinates: Xilinx
Phd Thesis:
- [1] R. S. Ghaida, “Design enablement and design-centric assessment of future semiconductor technologies,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012.
[Bibtex]
@phdthesis{PHDTH3,
author = {Ghaida, R. S.},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH3_paper.pdf},
title = {Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies},
year = {2012}
}
Publications
[1] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, 2014
[Bibtex] @inproceedings{C74,
author = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,dre},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_slides.pdf},
title = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},
year = {2014}
}
[Bibtex] @inproceedings{IP16,
author = { Ghaida, Rani S. and Badr, Yasmine and Gupta, Puneet},
booktitle = {{Proc. IEEE International Conference on Computer Design}},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP16_paper.pdf},
title = {Pattern-restricted design at 10nm and beyond},
year = {2014}
}
[Bibtex] @article{J30,
author = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {variability},
month = {August },
number = {3},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J30_paper.pdf},
title = {Framework for exploring the interaction between design rules and overlay control},
volume = {12},
year = {2013}
}
[Bibtex] @inproceedings{C69,
author = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography}},
category = {C69},
keywords = {overlay, design rules, dre, alignment},
month = {Feburary},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C69_paper.pdf},
title = {A {F}ramework for {E}xploring the {I}nteraction between {D}esign {R}ules and {O}verlay {C}ontrol},
year = {2013}
}
[Bibtex] @inproceedings{IP11,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/mp_and_design_date13.pdf},
title = {Role of Design in Multiple Patterning: Technology
Development, Design Enablement and Process Control},
year = {2013}
}
[Bibtex] @inproceedings{C64,
author = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C64},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_slides.pdf},
title = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},
year = {2012}
}
[Bibtex] @inproceedings{IP9,
author = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},
booktitle = {{Intl. Conf. on IC Design and Technology}},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ip9_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ip9_slides.pdf},
title = {O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction},
year = {2012}
}
[Bibtex] @inproceedings{C63,
author = {Ghaida, R. S. and Agarwal, K. and Liebmann, L. and Nassif, S. R. and Gupta, P.},
booktitle = {{SPIE Advanced Lithography}},
category = {C63},
keywords = {triple patterning, double patterning, dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C63_paper.pdf},
title = {{A} {N}ovel {M}ethodology for {T}riple/{M}ultiple-{P}atterning {L}ayout {D}ecomposition},
year = {2012}
}
[Bibtex] @conference{W11,
author = {Ghaida, R. S. and Gupta, M. and Gupta, P.},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W11},
keywords = {dats, dre, design rules, overlay, alignment, process, multiple-patterning, lithography},
title = {A Framework for Exploring the Interaction Between Design Rules and Overlay Control},
year = {2012}
}
[Bibtex] @article{J19,
author = {Ghaida, R. S. and Gupta, P.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {design rules, technology assessment, dre, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J19_paper.pdf},
title = {{DRE}: a {F}ramework for {E}arly {C}o-{E}valuation of {D}esign {R}ules, {T}echnology {C}hoices, and {L}ayout {M}ethodologies},
year = {2012}
}
[Bibtex] @phdthesis{PHDTH3,
author = {Ghaida, R. S.},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH3_paper.pdf},
title = {Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies},
year = {2012}
}
[Bibtex] @article{J27,
author = {Ghaida, R. S. and Agarwal, K. B. and Nassif, S. R. and Yuan, X. and Liebmann, L. W. and Gupta, P.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi, multiple-patterning},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J27_paper.pdf},
title = {{L}ayout {D}ecomposition and {L}egalization for {D}ouble-{P}atterning {T}echnology},
year = {2012}
}
[Bibtex] @inproceedings{C59,
author = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C59},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C59_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C59_slides.pdf},
title = {A {F}ramework for {D}ouble {P}atterning-{E}nabled {D}esign},
year = {2011}
}
[Bibtex] @inproceedings{IP7,
author = {A.R. Neureuther and J. Rubinstein and M. Miller and K. Yamazoeand E. Chin and C. Levy and L. Wang and N. Xu and C. Spanos and K. Qian and K. Poolla and J. Ghan and A. Subramanian and T.-J. K. Liu and X. Sun and K. Jeong and and P. Gupta and Kagalwalla, Abde Ali and Ghaida, R. S. and T.-B. Chan},
booktitle = {{Proc. SPIE Photomask and Next-Generation Lithography Mask Technology}},
category = {IP7},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/pmj11.pdf},
title = {Collaborative research on emerging technologies and design},
year = {2011}
}
[Bibtex] @inproceedings{IP6,
author = {Chan, T.-B. and Ghaida, R. S. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {IP6},
keywords = {mad},
note = {Embedded Tutorial},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP6_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP6_slides.pdf},
title = {{E}lectrical {M}odeling of {L}ithographic {I}mperfections},
year = {2010}
}
[Bibtex] @article{J13,
author = {Ghaida, R. S. and Torres, G. and Gupta, P.},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {double patterning, stdpl, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J13_paper.pdf},
title = {{S}ingle-{M}ask {D}ouble-{P}atterning {L}ithography for {R}educed {C}ost and {I}mproved {O}verlay {C}ontrol},
year = {2010}
}
[Bibtex] @article{J10,
author = {Ghaida, R. S. and Gupta, P.},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {double patterning, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J10_paper.pdf},
title = {Within-{L}ayer {O}verlay {I}mpact for {D}esign in {M}etal {D}ouble {P}atterning},
year = {2010}
}
[Bibtex] @inproceedings{C44,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C44},
keywords = {dats, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C44_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C44_slides.pdf},
title = {A {F}ramework for {E}arly and {S}ystematic {E}valuation of {D}esign {R}ules},
year = {2009}
}
[Bibtex] @inproceedings{C41,
author = {Ghaida, R. S. and Torres, G. and Gupta, P.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
keywords = {dats},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C41_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C41_slides.pdf},
title = {Single-{M}ask {D}ouble-{P}atterning {L}ithography},
year = {2009}
}
[Bibtex] @inproceedings{C40,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {double patterning, test pattern, dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C40_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C40_slides.pdf},
title = {Design-{O}verlay {I}nteractions in {M}etal {D}ouble {P}atterning},
year = {2009}
}
[Bibtex] @conference{W1,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{SRC TECHCON'09}},
category = {W1},
keywords = {dats},
month = {},
pages = {},
title = {A {F}ramework for {S}ystematic {E}valuation and {E}xploration of {D}esign {R}ules},
year = {2009}
}
Dr. John Lee
Contact: lee at ee dot ucla
Last known coordinates: KPMG
Phd Thesis:
- [1] J. Lee, “Implications of modern semiconductor technologies on gate sizing,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012.
[Bibtex]
@phdthesis{PHDTH2,
author = {Lee, John},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH2_paper.pdf},
title = {Implications of Modern Semiconductor Technologies on Gate Sizing},
year = {2012}
}
Publications
[1] J. Lee and P. Gupta, “Impact of range and precision in technology on cell-based design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012
[Bibtex] @inproceedings{C67,
author = {Lee, John and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C67},
keywords = {sizing},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C67_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C67_slides.pdf},
title = {Impact of Range and Precision in Technology on Cell-Based Design},
year = {2012}
}
[Bibtex] @inproceedings{C66,
author = {Lee, John and Gupta, Puneet and Pikus, Fedor},
booktitle = {{Proc. IEEE Computer Society Annual Symposium on VLSI}},
category = {C66},
keywords = {variability-aware},
month = {August},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C66_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C66_slides.pdf},
title = {Parametric Hierarchy Recovery in Layout Extracted Netlists},
year = {2012}
}
[Bibtex] @book{B2,
author = {Lee, J. and Gupta, P.},
isbn = {978-1-60198-542-2},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/B2_paper.pdf},
publisher = {Now Publishers},
title = {Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment},
year = {2012}
}
[Bibtex] @article{J24,
author = {John Lee and Puneet Gupta},
journal = {{ACM Transactions on Design Automation of Electronic Systems}},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J24_paper.pdf},
title = {{ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes}},
year = {2012}
}
[Bibtex] @article{J25,
author = {Santiago Mok and John Lee and Puneet Gupta},
journal = {{ACM Transactions on Design Automation of Electronic Systems}},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J25_paper.pdf},
title = {Discrete Sizing for Leakage Power Optimization in Physical Design: A Comparative Study},
year = {2012}
}
[Bibtex] @phdthesis{PHDTH2,
author = {Lee, John},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH2_paper.pdf},
title = {Implications of Modern Semiconductor Technologies on Gate Sizing},
year = {2012}
}
[Bibtex] @conference{W10,
author = {Lee, John and Gupta, Puneet},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W10},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W10_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W10_slides.pdf},
title = {Parametric Hierarchy Recovery for Layout Extracted Netlists},
year = {2011}
}
[Bibtex] @article{J12,
author = {Cong, J. and Gupta, P. and Lee, John},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {sizing, mad},
month = {Nov},
number = {11},
pages = {1750--1762},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J12_paper.pdf},
title = {{Evaluating Statistical Power Optimization}},
volume = {29},
year = {2010}
}
[Bibtex] @inproceedings{C51,
author = {Lee, John and Gupta, Puneet},
booktitle = {{Proc. IEEE International Conference on Computer Design}},
category = {C51},
keywords = {sizing, mad},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C51_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C51_slides.pdf},
title = {{I}ncremental {G}ate {S}izing for {L}ate {P}rocess {C}hanges},
year = {2010}
}
[Bibtex] @conference{W7,
author = {Lee, John and Gupta, Puneet},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W7},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W7_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W7_slides.pdf},
title = {Incremental Gate Sizing for Late Process Changes},
year = {2010}
}
[Bibtex] @inproceedings{C38,
author = {Cong, J. and Gupta, P. and Lee, John},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C38},
keywords = {sizing, mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C38_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C38_slides.pdf},
title = {On the {F}utlity of {S}tatistical {P}ower {O}ptimization},
year = {2009}
}
[Bibtex] @inproceedings{C21,
author = {Gupta, P. and Heng, F.-L. and Lee, J.-F. },
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C21},
keywords = {mad},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C21_paper.pdf},
title = {Toward {T}hrough-{P}rocess {L}ayout {Q}uality {M}etrics},
year = {2005}
}
[Bibtex] @inproceedings{C12,
author = {Gupta, P. and Heng, F.-L. and Gordon, R.L. and Lai, K. and Lee, J. },
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C12},
keywords = {mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C12_paper.pdf},
title = {Taming {F}ocus {V}ariation in {VLSI} {D}esign},
year = {2004}
}
Dr. Lerong Cheng
Contact: lerong AT ucla DOT edu
Last known coordinates: Google
Phd Thesis:
- [1] L. Cheng, “Statistical analysis and optimization for timing and power of vlsi circuits,” PhD Thesis, 2010.
[Bibtex]
@phdthesis{PHDTH1,
author = {Cheng, Lerong},
category = {PT1},
keywords = {stat},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH1_paper.pdf},
school = {Department of Electrical Engineering, University of California Los Angeles },
title = {Statistical Analysis and Optimization for Timing and Power of VLSI Circuits},
year = {2010}
}
Publications
[1] T. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,” IEEE Transactions on Semiconductor Manufacturing, 2012.
[Bibtex] @article{J21,
author = {Chan, Tuck-Boon and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {Process monitoring, wafer pruning, variability},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J21_paper.pdf},
title = {{D}esign {D}ependent {P}rocess {M}onitoring for {W}afer {M}anufacturing and {T}est {C}ost {R}eduction},
year = {2012}
}
[Bibtex] @inproceedings{C53,
author = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C53},
keywords = {process variation, process monitoring, dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_slides.pdf},
title = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},
year = {2010}
}
[Bibtex] @inproceedings{C47,
author = {Cheng, L. and Gupta, P. and He, L.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C47},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C47_paper.pdf},
title = {On {C}onfidence in {C}haracterization and {A}pplication of {V}ariation {M}odels},
year = {2010}
}
[Bibtex] @article{J14,
author = {Cheng, L. and Gupta, P. and Spanos, C. J. and Qian, K. and He, L.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J14_paper.pdf},
title = {{P}hysically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},
year = {2010}
}
[Bibtex] @phdthesis{PHDTH1,
author = {Cheng, Lerong},
category = {PT1},
keywords = {stat},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH1_paper.pdf},
school = {Department of Electrical Engineering, University of California Los Angeles },
title = {Statistical Analysis and Optimization for Timing and Power of VLSI Circuits},
year = {2010}
}
[Bibtex] @conference{W5,
author = {Cheng, L. and Gupta, Puneet},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W5},
keywords = {stat},
title = {{A Levelized Variation Modeling Scheme}},
year = {2010}
}
[Bibtex] @conference{W9,
author = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
booktitle = {{SRC TECHCON'10}},
category = {W9},
keywords = {stat},
title = {{D}esign {Dependent} {P}rocess {M}onitoring},
year = {2010}
}
[Bibtex] @inproceedings{C39,
author = {Cheng, L. and Gupta, P. and He, L.},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
category = {C39},
keywords = {mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C39_paper.pdf},
title = {Accounting for {N}on-linear {D}ependence {U}sing {F}unction {D}riven {C}omponent {A}nalysis},
year = {2009}
}
[Bibtex] @inproceedings{C43,
author = {Cheng, L. and Gupta, P. and Qian, K. and Spanos, C. and He, L.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C43},
keywords = {mad},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C43_paper.pdf},
title = {Physically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},
year = {2009}
}
[Bibtex] @article{J9,
author = {Cheng, L. and Gupta, P. and He, L.},
category = {J9},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {mad},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J9_paper.pdf},
title = {Efficient {A}dditive {S}tatistical {L}eakage {E}stimation},
year = {2009}
}
M.S.
Yizhang Wu
Contact: wuyizhang AT ucla DOT edu
Last known coordinates: Micron
MS Thesis:
- [1] Y. Wu, “Pin assignment for 2.5d dielet assembly,” Department of Electrical and Computer Engineering, University of California Los Angeles 2019.
[Bibtex]
@techreport{MSTH6,
author = {Wu, Yizhang},
institution = {Department of Electrical and Computer Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH6_paper.pdf},
title = {Pin Assignment for 2.5D Dielet Assembly},
year = {2019}
}
Publications
[1] W. Wang, Y. Wu, and P. Gupta, “Reverse Engineering for 2.5D Split Manufactured ICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
[Bibtex] @article{J64,
author = {Wang, Wei-Che and Wu, Yizhang and Gupta, Puneet},
doi = {https://doi.org/10.1109/TCAD.2019.2957359},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
publisher = {{IEEE}},
title = {{Reverse Engineering for 2.5D Split Manufactured ICs}},
year = {2020}
}
[Bibtex] @article{J60,
author = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Diggavi, Suhas and Gupta, Puneet},
journal = {{{IEEE Transactions on Information Forensics and Security}}},
month = {May},
publisher = {IEEE},
title = {{SLATE: A Secure Lightweight Entity Authentication Hardware Primitive}},
year = {2019}
}
[Bibtex] @techreport{MSTH6,
author = {Wu, Yizhang},
institution = {Department of Electrical and Computer Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH6_paper.pdf},
title = {Pin Assignment for 2.5D Dielet Assembly},
year = {2019}
}
[Bibtex] @inproceedings{C99,
author = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Hung, Szu-Yao and Diggavi, Suhas and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST)}},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C99_paper.pdf},
title = {{Implementation of Stable PUFs Using Gate Oxide Breakdown}},
year = {2017}
}
Yoo-Jin Chae
Contact: yoojinchae AT ucla DOT edu
Last known coordinates: Google
MS Thesis:
- [1] Y. Chae, “Defect avoidance for extreme ultraviolet mask defects using intentional pattern deformation,” Department of Electrical and Computer Engineering, University of California Los Angeles 2018.
[Bibtex]
@techreport{MSTH5,
author = {Chae, Yoo-Jin},
institution = {Department of Electrical and Computer Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH5_paper.pdf},
title = {Defect Avoidance for Extreme Ultraviolet Mask Defects using Intentional Pattern Deformation},
year = {2018}
}
Vishesh Dokania
Contact: vdokania AT ucla DOT edu
Last known coordinates: Cadence
MS Report:
- [1] V. Dokania, “Intrusive routing for improved standard cell pin access,” Department of Electrical Engineering, University of California Los Angeles 2017.
[Bibtex]
@techreport{MSTR12,
author = {Dokania, Vishesh },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR12_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR12_slides.pdf},
title = {Intrusive Routing for Improved Standard Cell Pin Access},
year = {2017}
}
Nan Lyu
Contact:
Last known coordinates: Huawei
MS Report:
- [1] N. Lyu, “Leon3 processor variability emulator for delay variability impact on performance,” Department of Electrical Engineering, University of California Los Angeles 2016.
[Bibtex]
@techreport{MSTR11,
author = {Lyu, Nan},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR11_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR11_slides.pdf},
title = {Leon3 Processor Variability Emulator for Delay Variability Impact on Performance},
year = {2016}
}
Abishek Bhatia
Contact:
Last known coordinates: Xilinx
MS Report:
- [1] A. Bhatia, “Varleon: fpga based processor variability emulator for variation aware software,” Department of Electrical Engineering, University of California Los Angeles 2014.
[Bibtex]
@techreport{MSTR9,
author = {Bhatia, Abishek},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR9_paper.pdf},
title = {VarLEON: FPGA Based Processor Variability Emulator for Variation Aware Software},
year = {2014}
}
Mukul Gupta
Contact: mukulg AT ucla DOT edu
Last known coordinates: Qualcomm
Publications
[1] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, 2014
[Bibtex] @inproceedings{C74,
author = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,dre},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_slides.pdf},
title = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},
year = {2014}
}
[Bibtex] @article{J30,
author = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {variability},
month = {August },
number = {3},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J30_paper.pdf},
title = {Framework for exploring the interaction between design rules and overlay control},
volume = {12},
year = {2013}
}
[Bibtex] @inproceedings{C69,
author = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography}},
category = {C69},
keywords = {overlay, design rules, dre, alignment},
month = {Feburary},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C69_paper.pdf},
title = {A {F}ramework for {E}xploring the {I}nteraction between {D}esign {R}ules and {O}verlay {C}ontrol},
year = {2013}
}
[Bibtex] @conference{W11,
author = {Ghaida, R. S. and Gupta, M. and Gupta, P.},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W11},
keywords = {dats, dre, design rules, overlay, alignment, process, multiple-patterning, lithography},
title = {A Framework for Exploring the Interaction Between Design Rules and Overlay Control},
year = {2012}
}
Tanaya Sahu
Contact: tanayasahu AT ucla DOT edu
Last known coordinates: Intel
Publications
[1] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, “A methodology for the early exploration of design rules for multiple-patterning technologies,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012
[Bibtex] @inproceedings{C64,
author = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C64},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_slides.pdf},
title = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},
year = {2012}
}
Chia-Hao Chang
Contact: changchiahao AT ucla DOT edu
Last known coordinates:
Publications
[1] L. Lai, C. Chang, and P. Gupta, “Exploring total power saving from high temperature of server operations,” 2014.
[Bibtex] @techreport{TECHRP2,
author = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/5898p020},
title = {Exploring Total Power Saving from High Temperature of Server Operations},
year = {2014}
}
[Bibtex] @article{TR1,
author = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},
keywords = {hsi},
paperurl = {http://escholarship.org/uc/item/5898p020},
title = {Exploring Total Power Saving from High Temperature of Server Operations},
year = {2014}
}
Ankur Sharma
Contact: ankursharma AT ucla DOT edu
Last known coordinates:
MS Thesis:
- [1] A. Sharma, “Understanding software application behaviour in presence of permanent and intermittent hardware faults,” Department of Electrical Engineering, University of California Los Angeles 2013.
[Bibtex]
@techreport{MSTH3,
author = {Sharma, Ankur},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH3_paper.pdf},
title = {Understanding Software Application Behaviour in Presence of Permanent and Intermittent Hardware Faults},
year = {2013}
}
Publications
[1] A. Sharma, J. Sloan, L. F. Wanner, S. H. Elmalaki, M. B. Srivastava, and P. Gupta, “Towards Analyzing and Improving Robustness of Software Applications to Intermittent and Permanent Faults in Hardware,” in Proc. IEEE International Conference on Computer Design, 2013
[Bibtex] @inproceedings{C72,
author = {Sharma, Ankur and Sloan, Joseph and Wanner, Lucas F. and Elmalaki, Salma H. and Srivastava, Mani B. and Gupta, Puneet},
booktitle = {{Proc. IEEE International Conference on Computer Design}},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C72_paper.pdf},
title = {{T}owards {A}nalyzing and {I}mproving {R}obustness of {S}oftware {A}pplications to {I}ntermittent and {P}ermanent {F}aults in {H}ardware},
year = {2013}
}
[Bibtex] @techreport{MSTH3,
author = {Sharma, Ankur},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH3_paper.pdf},
title = {Understanding Software Application Behaviour in Presence of Permanent and Intermittent Hardware Faults},
year = {2013}
}
Ning Jin
Contact:
Last known coordinates: LinkedIn
MS Report:
- [1] N. Jin, “Modelling of guardband reduction on design area,” Department of Electrical Engineering, University of California Los Angeles 2012.
[Bibtex]
@techreport{MSTR8,
author = {Jin, Ning},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {mad, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR8_paper.pdf},
title = {Modelling of Guardband Reduction on Design Area},
year = {2012}
}
Publications
[1] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, 2014
[Bibtex] @inproceedings{C74,
author = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,dre},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_slides.pdf},
title = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},
year = {2014}
}
[Bibtex] @techreport{MSTR8,
author = {Jin, Ning},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {mad, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR8_paper.pdf},
title = {Modelling of Guardband Reduction on Design Area},
year = {2012}
}
Jingyuan Dong
Contact:
Last known coordinates: Snapchat
MS Report:
- [1] J. Dong, “High Level Battery Modeling Considering Discharge Rate and Temperature Effects,” Department of Electrical Engineering, University of California Los Angeles 2012.
[Bibtex]
@techreport{MSTR7,
author = {Dong, Jingyuan},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR7_paper.pdf},
title = {{High Level Battery Modeling Considering Discharge Rate and Temperature Effects}},
year = {2012}
}
Parag Kulkarni
Contact: paragk AT ucla DOT edu
Last known coordinates: Google
MS Report:
- [1] P. Kulkarni, “Trading Accuracy for Power with an Under-designed Multiplier Architecture,” Department of Electrical Engineering, University of California Los Angeles 2011.
[Bibtex]
@techreport{MSTR6,
author = {Kulkarni, Parag },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR6_paper.pdf},
title = {{Trading Accuracy for Power with an Under-designed
Multiplier Architecture}},
year = {2011}
}
Publications
[1] P. Kulkarni, P. Gupta, and R. Beraha, “Minimizing Clock Domain Crossing in Network on Chip Interconnect,” in IEEE International Symposium on Quality Electronic Design, 2014
[Bibtex] @inproceedings{C76,
author = {Kulkarni, Parag and Gupta, Puneet and Beraha, Rudy},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
keywords = {dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C76_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C76_slides.pdf},
title = {{M}inimizing {C}lock {D}omain {C}rossing in {N}etwork on {C}hip {I}nterconnect},
year = {2014}
}
[Bibtex] @inproceedings{C64,
author = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C64},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_slides.pdf},
title = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},
year = {2012}
}
[Bibtex] @inproceedings{C54,
author = {Kulkarni, Parag and Gupta, Puneet and Ercegovac, Milos},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C54},
keywords = {low power, hsi},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C54_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C54_slides.pdf},
title = {{T}rading {A}ccuracy for {P}ower with an {U}nderdesigned {M}ultiplier {A}rchitecture},
year = {2011}
}
[Bibtex] @article{J16,
author = {Kulkarni, P. and Gupta, P. and Ercegovac, M.D.},
journal = {{Journal of Low Power Electronics}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/JOLPE_v3.pdf},
title = {Trading Accuracy for Power in a Multiplier Architecture},
year = {2011}
}
[Bibtex] @techreport{MSTR6,
author = {Kulkarni, Parag },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR6_paper.pdf},
title = {{Trading Accuracy for Power with an Under-designed
Multiplier Architecture}},
year = {2011}
}
Charwak S Apte
Contact: charwak AT ee DOT ucla DOT edu
Last known coordinates: AMD
MS Report:
- [1] C. Apte, “Power Consumption Variability in Embedded Processors,” Department of Electrical Engineering, University of California Los Angeles 2011.
[Bibtex]
@techreport{MSTR5,
author = {Apte, Charwak},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR5_paper.pdf},
title = {{Power Consumption Variability in Embedded
Processors}},
year = {2011}
}
Publications
[1] L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “Hardware Variability-Aware Duty Cycling for Embedded Sensors,” IEEE Transactions on Very Large Scale Integration Systems, 2012.
[Bibtex] @article{J23,
author = {Lucas Wanner and Charwak Apte and Rahul Balani and Puneet Gupta and Mani Srivastava},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/j23.pdf},
title = {{H}ardware {V}ariability-{A}ware {D}uty {C}ycling for {E}mbedded {S}ensors},
year = {2012}
}
[Bibtex] @inproceedings{C56,
author = {Wanner, Lucas and Balani, Rahul and Zahedi, Sadaf and Apte, Charwak and Gupta, Puneet and Srivastava, Mani },
booktitle = {{Design, Automation, and Test in Europe (DATE)}},
category = {C56},
keywords = {variabilty-aware, embedded sensing, hsi},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C56_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C56_slides.pdf},
title = {{V}ariability {A}ware {D}uty {C}ycle {S}cheduling in {L}ong {R}unning {E}mbedded {S}ensing {S}ystems},
year = {2011}
}
[Bibtex] @techreport{MSTR5,
author = {Apte, Charwak},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {hsi, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR5_paper.pdf},
title = {{Power Consumption Variability in Embedded
Processors}},
year = {2011}
}
[Bibtex] @conference{C58,
author = {Wanner, Lucas and Apte, Charwak and Balani, Rahul and Gupta, Puneet and Srivastava, Mani},
booktitle = {{HotPower'10}},
category = {C58},
keywords = {embedded sensing, leakage power, duty cycling, hsi},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C58_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C58_slides.pdf},
title = {{A} {C}ase for {O}pportunistic {E}mbedded {S}ensing {I}n {P}resence of {H}ardware {P}ower {V}aribility},
year = {2010}
}
Santiago Mok
Contact: smok AT ee DOT ucla DOT edu
Last known coordinates: Intel
MS Report:
- [1] S. Mok, “Post-Layout Sizing for Leakage Power Optimization: A Comparative Study,” Department of Electrical Engineering, University of California Los Angeles 2011.
[Bibtex]
@techreport{MSTR4,
author = {Mok, Santiago},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR4_paper.pdf},
title = {{Post-Layout Sizing for Leakage Power Optimization: A Comparative Study}},
year = {2011}
}
Publications
[1] S. Mok, J. Lee, and P. Gupta, “Discrete sizing for leakage power optimization in physical design: a comparative study,” ACM Transactions on Design Automation of Electronic Systems, 2012.
[Bibtex] @article{J25,
author = {Santiago Mok and John Lee and Puneet Gupta},
journal = {{ACM Transactions on Design Automation of Electronic Systems}},
keywords = {sizing},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J25_paper.pdf},
title = {Discrete Sizing for Leakage Power Optimization in Physical Design: A Comparative Study},
year = {2012}
}
[Bibtex] @techreport{MSTR4,
author = {Mok, Santiago},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR4_paper.pdf},
title = {{Post-Layout Sizing for Leakage Power Optimization: A Comparative Study}},
year = {2011}
}
[Bibtex] @techreport{UG6,
author = {Mok, Santiago},
institution = {University of California, Los Angeles},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/UG6_paper.pdf},
title = {{Propagation Delay Approximation Considering Effective Capacitance and Slew Degradation}},
year = {2009}
}
Aashish Pant
Contact: apant AT ucla DOT edu
Last known coordinates: Facebook
MS Thesis:
- [1] A. Pant, “Hardware-software interface in the presence of hardware manufacturing variations,” Department of Electrical Engineering, University of California Los Angeles 2010.
[Bibtex]
@techreport{MSTH1,
author = {Pant, Aashish },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH1_paper.pdf},
title = {Hardware-Software Interface in the Presence of Hardware Manufacturing Variations},
year = {2010}
}
Publications
[1] T. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,” IEEE Transactions on Semiconductor Manufacturing, 2012.
[Bibtex] @article{J21,
author = {Chan, Tuck-Boon and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {Process monitoring, wafer pruning, variability},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J21_paper.pdf},
title = {{D}esign {D}ependent {P}rocess {M}onitoring for {W}afer {M}anufacturing and {T}est {C}ost {R}eduction},
year = {2012}
}
[Bibtex] @article{J17,
author = {Aashish Pant and Gupta, Puneet and Mihaela van der Schaar},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/VarAwareAdapt.pdf},
title = {AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation},
year = {2011}
}
[Bibtex] @inproceedings{C53,
author = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C53},
keywords = {process variation, process monitoring, dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_slides.pdf},
title = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},
year = {2010}
}
[Bibtex] @inproceedings{C49,
author = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},
booktitle = {{ACM Great Lakes Symposium on Very Large Scale Integration}},
category = {C49},
keywords = {hsi},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C49_paper.pdf},
title = {{S}oftware {A}daptation in {Q}uality {S}ensitive {A}pplications to {D}eal with {H}ardware {V}ariability},
year = {2010}
}
[Bibtex] @inproceedings{C48,
author = {Sartori, John and Pant, Aashish and Kumar, Rakesh and Gupta, Puneet},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
category = {C48},
keywords = {hsi},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C48_paper.pdf},
title = {{V}ariation {A}ware {S}peed {B}inning of {M}ulti-core {P}rocessors},
year = {2010}
}
[Bibtex] @techreport{MSTH1,
author = {Pant, Aashish },
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {thesis},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTH1_paper.pdf},
title = {Hardware-Software Interface in the Presence of Hardware Manufacturing Variations},
year = {2010}
}
[Bibtex] @conference{W9,
author = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
booktitle = {{SRC TECHCON'10}},
category = {W9},
keywords = {stat},
title = {{D}esign {Dependent} {P}rocess {M}onitoring},
year = {2010}
}
[Bibtex] @conference{W2,
author = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W2},
keywords = {hsi-p1},
title = {{S}oftware {A}daptation to {H}andle {M}anufacturing {Variability} and {R}elax {H}ardware {O}verdesign},
year = {2009}
}
[Bibtex] @conference{W3,
author = {Sartori, John and Pant, Aashish and Gupta, Puneet and Kumar, Rakesh},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W3},
keywords = {hsi-p2},
title = {{O}n {P}erformance {B}inning of {M}ulticore {P}rocessors},
year = {2009}
}
Tuck Boon Chan
Contact: tuckie AT ucla DOT edu
Last known coordinates: Qualcomm
Publications
[1] T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, and A. B. Kahng, “Benchmarking of Mask Fracturing Heuristics,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016
[Bibtex] @inproceedings{J44,
author = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. },
booktitle = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
category = {J44},
keywords = {dats},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J44_paper.pdf},
title = {Benchmarking of {M}ask {F}racturing {H}euristics},
year = {2016}
}
[Bibtex] @inproceedings{C80,
author = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. and Sahouria, Emile},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C80},
keywords = {dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C80_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C80_slides.pdf},
title = {Benchmarking of {M}ask {F}racturing {H}euristics},
year = {2014}
}
[Bibtex] @techreport{TECHRP1,
author = {Agarwal, Yuvraj and Bishop, Alex and Chan, Tuck-Boon and Fotjik, Matt and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen and Martin, Paul and Srivastava, Mani and Sylvester, Dennis and Wanner, Lucas and Zhang, Bing},
keywords = {techreport, hsi},
paperurl = {http://www.escholarship.org/uc/item/1c21g217},
title = {Redcooper: Hardware sensor enabled variability software testbed for lifetime energy constrained application},
year = {2014}
}
[Bibtex] @article{J31,
author = {Chan, Tuck-Boon and Gupta, Puneet and Kahng, A. B. and Lai, Liangzhen},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {hsi, DDRO},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J31_paper.pdf},
title = {{S}ynthesis and {A}nalysis of {D}esign-{D}ependent {R}ing {O}scillator ({D}{D}{R}{O}) {P}erformance {M}onitors},
year = {2013}
}
[Bibtex] @inproceedings{C60,
author = {Chan, Tuck Boon and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen},
booktitle = {{ISQED}},
category = {C60},
keywords = {hsi, DDRO},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C60_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C60_slides.pdf},
title = {{DDRO}: A {N}ovel {P}erformance {M}onitoring {M}ethodology {B}ased on {D}esign-{D}ependent {R}ing {O}scillators},
year = {2012}
}
[Bibtex] @article{J21,
author = {Chan, Tuck-Boon and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {Process monitoring, wafer pruning, variability},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J21_paper.pdf},
title = {{D}esign {D}ependent {P}rocess {M}onitoring for {W}afer {M}anufacturing and {T}est {C}ost {R}eduction},
year = {2012}
}
[Bibtex] @inproceedings{C55,
author = {Chan, T.-B. and Sartori, John and Gupta, Puneet and Kumar, Rakesh},
booktitle = {{Design, Automation, and Test in Europe (DATE)}},
category = {C55},
keywords = {variabilty-aware, embedded sensing, hsi, ucla_rdmode},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C55_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C55_slides.pdf},
title = {{O}n the {E}fficacy of {NBTI} {M}itigation {T}echniques},
year = {2011}
}
[Bibtex] @article{J15,
author = {Chan, T.B. and Kagalwalla, Abde Ali and Gupta, P. },
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J15_paper.pdf},
title = {{M}easurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},
year = {2011}
}
[Bibtex] @inproceedings{C53,
author = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C53},
keywords = {process variation, process monitoring, dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_slides.pdf},
title = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},
year = {2010}
}
[Bibtex] @inproceedings{C46,
author = {Chan, T.-B. and Kagalwalla, Abde Ali and Gupta, P.},
booktitle = {{Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration}},
category = {C46},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C46_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C46_slides.pdf},
title = {Measurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},
year = {2010}
}
[Bibtex] @inproceedings{C45,
author = {Chan, T.-B. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C45},
keywords = {dats, mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C45_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C45_slides.pdf},
title = {On {E}lectrical {M}odeling of {I}mperfect {D}iffusion {P}atterning},
year = {2010}
}
[Bibtex] @inproceedings{IP6,
author = {Chan, T.-B. and Ghaida, R. S. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {IP6},
keywords = {mad},
note = {Embedded Tutorial},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP6_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP6_slides.pdf},
title = {{E}lectrical {M}odeling of {L}ithographic {I}mperfections},
year = {2010}
}
[Bibtex] @conference{W9,
author = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
booktitle = {{SRC TECHCON'10}},
category = {W9},
keywords = {stat},
title = {{D}esign {Dependent} {P}rocess {M}onitoring},
year = {2010}
}
[Bibtex] @conference{W4,
author = {Chan, T.-B. and Gupta, Puneet and Balakrishnan, Varsha and Cao, Yu},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W4},
keywords = {dats},
title = {{E}xtended {B}urn-in for {R}educed {V}th {V}ariation},
year = {2009}
}
Kasibhatla Amarnath
Contact: amar AT ee DOT ucla DOT edu
Last known coordinates: Intel
MS Thesis:
- [1] A. Kasibhatla, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” Department of Electrical Engineering, University of California Los Angeles 2010.
[Bibtex]
@techreport{MSTR3,
author = {Kasibhatla, Amarnath},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR3_paper.pdf},
title = {{Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics}},
year = {2010}
}
Publications
[1] P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2010
[Bibtex] @inproceedings{C50,
author = {Gupta, Puneet and Kahng, Andrew and Kasibhatla, Amarnath and Sharma, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C50},
keywords = {sizing, eyecharts},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C50_paper.pdf},
title = {{E}yecharts: {C}onstructive {B}enchmarking of {G}ate {S}izing {H}euristics},
year = {2010}
}
[Bibtex] @techreport{MSTR3,
author = {Kasibhatla, Amarnath},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR3_paper.pdf},
title = {{Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics}},
year = {2010}
}
Dominic Reinhard
Contact: dominicr AT ucla DOT edu
Last known coordinates: Western Digital
MS Report:
- [1] D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” Department of Electrical Engineering, University of California Los Angeles 2010.
[Bibtex]
@techreport{MSTR2,
author = {Reinhard, Dominic},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {mad. msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR2_paper.pdf},
title = {{On Comparing Conventional and Electrically Driven OPC Techniques}},
year = {2010}
}
Publications
[1] D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” Department of Electrical Engineering, University of California Los Angeles 2010.
[Bibtex] @techreport{MSTR2,
author = {Reinhard, Dominic},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {mad. msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR2_paper.pdf},
title = {{On Comparing Conventional and Electrically Driven OPC Techniques}},
year = {2010}
}
[Bibtex] @inproceedings{C42,
author = {Gupta, P. and Reinhard, D.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
category = {C42},
keywords = {dats},
month = {},
title = {On {C}omparing {C}onventional and {E}lectrically {D}riven {OPC} {T}echniques},
year = {2009}
}
Viswakiran Popuri
Contact: viswa AT ee DOT ucla DOT edu
Last known coordinates: Aquantia
MS Report:
- [1] V. Popuri, “Bias-driven Robust Analog Circuit Sizing Scheme,” Department of Electrical Engineering, University of California Los Angeles 2009.
[Bibtex]
@techreport{MSTR1,
author = {Popuri, Viswakiran},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR1_paper.pdf},
title = {{Bias-driven Robust Analog Circuit Sizing Scheme}},
year = {2009}
}
Publications
[1] V. Popuri, P. Gupta, and S. Pamarti, “Bias-Driven Robust Analog Circuit Sizing Scheme,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010
[Bibtex] @conference{W8,
author = {Popuri, V. and Gupta, P. and Pamarti, S.},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W8},
keywords = {dats},
title = {{Bias-Driven Robust Analog Circuit Sizing Scheme}},
year = {2010}
}
[Bibtex] @techreport{MSTR1,
author = {Popuri, Viswakiran},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {sizing, msreport},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/MSTR1_paper.pdf},
title = {{Bias-driven Robust Analog Circuit Sizing Scheme}},
year = {2009}
}