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Design-Assisted Technology Scaling

The semiconductor industry is likely to see several rad- ical changes in the fabrication and device technologies in the next decade. Each of these technologies requires enormous research investment before they can see any adoption. Con- ventional “after-the-fact” changes to design methodologies and tools to what technology offers lead to wasted research investment, delayed adoption and underutilization of technology as well as more design overhead. Therefore, early assessment of design restrictions imposed by, and design advantages of technological choices is absolutely essential. In addition to building such co-evaluation frameworks, we have pioneered several techniques to enable silicon manufacturing guided by design and also explore design-enablement of future patterning options.

A Framework for Early and Systematic Evaluation and Exploration of Design Rules

Students: Rani S. Ghaida, Abde Ali Kagalwalla

Objective: A framework for co-evaluation and exploration of design rules and technology decisions at cell and chip levels. By using first order models of variability and manufacturability and layout topology/congestion-based area estimation, our framework can evaluate big decisions before exact process and design technologies are known.

UCLA_DRE is a tool written in C++ for evaluating and exploring design rules (DRs) and layout styles at cell level in standard-cell based designs.

The tool takes a transistor netlist, design rules, and estimates of process control parameters as input and evaluates cell-area, manufacturability, and variability of the entire design. It also displays evaluation results and layout information of every cell in the design separately. The latest release can be downloaded here (LICENSE).

A Framework for Evaluating Device Variability Impact on Circuits

Students: Liangzhen Lai, Shaodi Wang

Objective: A framework for evaluating the impact of device-level variability on circuit-level performance. An evaluation flow is implemented to automatically take device-level performance figures (i.e. Ion, Ioff, DIBL, SS etc.) variations as input, and generate corresponding variation data on circuit-level performance (i.e. leakage power, delay etc.). The framework is applied to line edge roughness (LER) induced variability on double-gate finfet. The sample data can be downloaded here:

  • LER_circuit_data.xlsx: LER_circuit_data.xlsx

Publications

    [1] P. Gupta, “Design Technology Co-Optimization for EUV (Keynote Talk),” in IEEE International Workshop on Advanced Patterning Solutions, 2022.
    [Bibtex] 
    @conference{ITT30,
author = {Gupta, Puneet},
booktitle = {{IEEE International Workshop on Advanced Patterning Solutions}},
keywords = {dats},
title = {{Design Technology Co-Optimization for EUV (Keynote Talk)}},
year = {2022}
}

    [2] [PDF] Y. Badr and P. Gupta, “Technology Path-finding for Directed Self-assembly for Via Layers”,” in SPIE Advanced Lithography Symposium, 2017.
    [Bibtex] 
    @inproceedings{C97,
author = {Badr, Yasmine and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C97_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C97_slides.pdf},
title = {{T}echnology {P}ath-finding for {D}irected {S}elf-assembly for {V}ia {L}ayers"},
year = {2017}
}

    [3] P. Gupta and J. A. Torres, “Understanding design-patterning interactions for euv and dsa,” in SPIE Advanced Lithography Symposium, 2017.
    [Bibtex] 
    @conference{ITT27,
author = {P. Gupta and J.A. Torres},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
note = {Short Course},
title = {Understanding Design-Patterning Interactions for EUV and DSA},
year = {2017}
}

    [4] P. Gupta, “Design technology co-optimization for disruptive patterning schemes,” in China Semiconductor Technology International Conference (CSTIC), 2017.
    [Bibtex] 
    @conference{ITT26,
author = {P. Gupta},
booktitle = {{China Semiconductor Technology International Conference (CSTIC)}},
keywords = {dats},
title = {Design Technology Co-optimization for Disruptive Patterning Schemes},
year = {2017}
}

    [5] [PDF] Y. Badr, “Co-optimization of restrictive patterning technologies and design,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.
    [Bibtex] 
    @phdthesis{PHDTH8,
author = {Badr, Yasmine},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH8_paper.pdf},
title = {Co-optimization of Restrictive Patterning Technologies and Design},
year = {2017}
}

    [6] [PDF] Y. Badr and P. Gupta, “Technology path-finding framework for directed-self assembly for via layers,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2017.
    [Bibtex] 
    @article{J52,
author = {Badr, Yasmine and Gupta, Puneet},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J52_paper.pdf},
title = {Technology path-finding framework for directed-self assembly for via layers},
year = {2017}
}

    [7] [PDF] Y. Badr, A. Torres, and P. Gupta, “Mask Assignment and Dsa Grouping for DSA-MP Hybrid Lithography for sub-7nm Contact/Via Holes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.
    [Bibtex] 
    @article{J48,
author = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},
category = {J48},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J48_paper.pdf},
title = {{M}ask {A}ssignment and {D}SA {G}rouping for {DSA-MP} {H}ybrid {L}ithography for sub-7nm {C}ontact/{V}ia {H}oles},
year = {2016}
}

    [8] [PDF] L. Zhu, Y. Badr, S. Wang, S. Iyer, and P. Gupta, “Assessing Benefits of a Buried Interconnect Layer in Digital Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.
    [Bibtex] 
    @article{J45,
author = {Zhu, Liheng and Badr, Yasmine and Wang, Shaodi and Iyer, Subramanian and Gupta, Puneet},
category = {J45},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
month = {May},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J45_paper.pdf},
title = {Assessing {B}enefits of a {B}uried {I}nterconnect {L}ayer in {D}igital {D}esigns},
year = {2016}
}

    [9] P. Gupta and J. A. Torres, “Understanding design-patterning interactions for euv and dsa,” in SPIE Advanced Lithography Symposium, 2016.
    [Bibtex] 
    @conference{ITT20,
author = {P. Gupta and J.A. Torres},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
note = {Short Course},
title = {Understanding Design-Patterning Interactions for EUV and DSA},
year = {2016}
}

    [10] [PDF] T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, and A. B. Kahng, “Benchmarking of Mask Fracturing Heuristics,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.
    [Bibtex] 
    @inproceedings{J44,
author = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. },
booktitle = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
category = {J44},
keywords = {dats},
month = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J44_paper.pdf},
title = {Benchmarking of {M}ask {F}racturing {H}euristics},
year = {2016}
}

    [11] [PDF] Y. Badr, A. Torres, and P. Gupta, “Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts/Vias,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2015.
    [Bibtex] 
    @inproceedings{C86,
author = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C86_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C86_slides.pdf},
title = { {M}ask {A}ssignment and {S}ynthesis of {DSA}-{MP} {H}ybrid {L}ithography for sub-7nm {C}ontacts/{V}ias},
year = {2015}
}

    [12] [PDF] A. A. Kagalwalla and P. Gupta, “Effective Model-Based Mask Fracturing for Mask Cost Reduction,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2015.
    [Bibtex] 
    @inproceedings{C87,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C87_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C87_slides.pptx},
title = { {E}ffective {M}odel-{B}ased {M}ask {F}racturing for {M}ask {C}ost {R}eduction},
year = {2015}
}

    [13] [PDF] Y. Badr, A. Torres, and P. Gupta, “Incorporating DSA in multipatterning semiconductor manufacturing technologies,” in SPIE Advanced Lithography Symposium, 2015.
    [Bibtex] 
    @inproceedings{C85,
author = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C85_paper.pdf},
title = { {I}ncorporating {DSA} in {m}ultipatterning {s}emiconductor {m}anufacturing {t}echnologies},
year = {2015}
}

    [14] P. Gupta, A. Mallik, and J. A. Torres, “Patterning beyond multiple patterning,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2015.
    [Bibtex] 
    @conference{ITT19,
author = {P. Gupta and A. Mallik and J.A. Torres},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
keywords = {dats},
note = {Embedded tutorial},
title = {Patterning beyond multiple patterning},
year = {2015}
}

    [15] [PDF] W. Wang and P. Gupta, “Efficient Layout Generation and Evaluation of Vertical Channel Devices,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014.
    [Bibtex] 
    @inproceedings{C81,
author = {Wang, Wei-Che and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C81},
keywords = {dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C81_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C81_slides.pdf},
title = {{E}fficient {L}ayout {G}eneration and {E}valuation of {V}ertical {C}hannel {D}evices},
year = {2014}
}

    [16] [PDF] T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, A. B. Kahng, and E. Sahouria, “Benchmarking of Mask Fracturing Heuristics,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2014.
    [Bibtex] 
    @inproceedings{C80,
author = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. and Sahouria, Emile},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C80},
keywords = {dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C80_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C80_slides.pdf},
title = {Benchmarking of {M}ask {F}racturing {H}euristics},
year = {2014}
}

    [17] [PDF] Y. Badr, K. Ma, and P. Gupta, “Layout Pattern-driven Design Rule Evaluation,” in SPIE Advanced Lithography Symposium, 2014.
    [Bibtex] 
    @inproceedings{C78,
author = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C78_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C78_slides.pdf},
title = {{L}ayout {P}attern-driven {D}esign {R}ule {E}valuation},
year = {2014}
}

    [18] [PDF] P. Kulkarni, P. Gupta, and R. Beraha, “Minimizing Clock Domain Crossing in Network on Chip Interconnect,” in IEEE International Symposium on Quality Electronic Design, 2014.
    [Bibtex] 
    @inproceedings{C76,
author = {Kulkarni, Parag and Gupta, Puneet and Beraha, Rudy},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
keywords = {dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C76_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C76_slides.pdf},
title = {{M}inimizing {C}lock {D}omain {C}rossing in {N}etwork on {C}hip {I}nterconnect},
year = {2014}
}

    [19] [PDF] A. A. Kagalwalla and P. Gupta, “Comprehensive Defect Avoidance Framework for Mitigating EUV Mask Defects,” in SPIE Advanced Lithography Symposium, 2014.
    [Bibtex] 
    @inproceedings{C77,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C77_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C77_slides.pdf},
title = {{C}omprehensive {D}efect {A}voidance {F}ramework for {M}itigating {EUV} {M}ask {D}efects},
year = {2014}
}

    [20] [PDF] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, 2014.
    [Bibtex] 
    @inproceedings{C74,
author = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,dre},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_slides.pdf},
title = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},
year = {2014}
}

    [21] [PDF] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “PROCEED: a Pareto Optimization-based Circuit-level Evaluator for Emerging Devices,” in Proc. Asia and South Pacific Design Automation Conference, 2014.
    [Bibtex] 
    @inproceedings{C75,
author = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,proceed},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C75_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C75_slides.pptx},
title = {{PROCEED:} A {P}areto {O}ptimization-based {C}ircuit-level {E}valuator for {E}merging {D}evices},
year = {2014}
}

    [22] [PDF] [DOI] A. A. Kagalwalla and P. Gupta, “Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), vol. 13, iss. 4, p. 43005, 2014.
    [Bibtex] 
    @article{J35,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
doi = {10.1117/1.JMM.13.4.043005},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
number = {4},
pages = {043005},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J35_paper.pdf},
title = {Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects},
volume = {13},
year = {2014}
}

    [23] [PDF] A. A. Kagalwalla, “Computational methods for design-assisted mask flows,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2014.
    [Bibtex] 
    @phdthesis{PHDTH4,
author = {Kagalwalla, Abde Ali},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH4_paper.pdf},
title = {Computational Methods for Design-Assisted Mask Flows},
year = {2014}
}

    [24] [PDF] Y. Badr, K. Ma, and P. Gupta, “Layout pattern-driven design rule evaluation,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2014.
    [Bibtex] 
    @article{J36,
author = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J36_paper.pdf},
title = {Layout Pattern-driven Design Rule Evaluation},
year = {2014}
}

    [25] P. Gupta, A. Mallik, and J. A. Torres, “Design-patterning interactions,” in SPIE Advanced Lithography Symposium, 2013.
    [Bibtex] 
    @conference{ITT18,
author = {P. Gupta and A. Mallik and J.A. Torres},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {dats},
note = {Half-Day tutorial.},
title = {Design-Patterning Interactions},
year = {2013}
}

    [26] R. S. Ghaida and P. Gupta, “Role of design in multiple patterning: technology development, design enablement and process control,” in IEEE/ACM Design, Automation and Test in Europe, 2013.
    [Bibtex] 
    @inproceedings{IP11,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{IEEE/ACM Design, Automation and Test in Europe}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/mp_and_design_date13.pdf},
title = {Role of Design in Multiple Patterning: Technology
Development, Design Enablement and Process Control},
year = {2013}
}

    [27] [PDF] A. A. Kagalwalla and P. Gupta, “Design-Aware Defect-Avoidance Floorplanning of EUV Masks,” IEEE Transactions on Semiconductor Manufacturing, vol. 26, 2013.
    [Bibtex] 
    @article{J28,
author = {Kagalwalla, Abde Ali and Gupta, Puneet},
issue = {1},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J28_paper.pdf},
title = {{Design-Aware Defect-Avoidance Floorplanning of EUV Masks}},
volume = {26},
year = {2013}
}

    [28] [PDF] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, “A methodology for the early exploration of design rules for multiple-patterning technologies,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012.
    [Bibtex] 
    @inproceedings{C64,
author = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C64},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_slides.pdf},
title = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},
year = {2012}
}

    [29] [PDF] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,” in Intl. Conf. on IC Design and Technology, 2012.
    [Bibtex] 
    @inproceedings{IP9,
author = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},
booktitle = {{Intl. Conf. on IC Design and Technology}},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ip9_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ip9_slides.pdf},
title = {O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction},
year = {2012}
}

    [30] [PDF] R. S. Ghaida, K. Agarwal, L. Liebmann, S. R. Nassif, and P. Gupta, “A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition,” in SPIE Advanced Lithography, 2012.
    [Bibtex] 
    @inproceedings{C63,
author = {Ghaida, R. S. and Agarwal, K. and Liebmann, L. and Nassif, S. R. and Gupta, P.},
booktitle = {{SPIE Advanced Lithography}},
category = {C63},
keywords = {triple patterning, double patterning, dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C63_paper.pdf},
title = {{A} {N}ovel {M}ethodology for {T}riple/{M}ultiple-{P}atterning {L}ayout {D}ecomposition},
year = {2012}
}

    [31] [PDF] A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta, “Design-of-Experiments Based Design Rule Optimization,” in SPIE Advanced Lithography, 2012.
    [Bibtex] 
    @inproceedings{C62,
author = {Kagalwalla, Abde Ali and Muddu, Swamy and Capodieci, Luigi and Zelnik, Coby and Gupta, Puneet },
booktitle = {{SPIE Advanced Lithography}},
category = {C62},
keywords = {Design Rules, DOE, dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C62_paper.pdf},
title = {{D}esign-of-{E}xperiments {B}ased {D}esign {R}ule {O}ptimization},
year = {2012}
}

    [32] [PDF] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-Aware Mask Inspection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
    [Bibtex] 
    @article{J18,
author = {Kagalwalla, Abde Ali and Puneet Gupta and Progler, Chris and McDonald, Steve},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J18_paper.pdf},
title = {Design-{A}ware {M}ask {I}nspection},
year = {2012}
}

    [33] [PDF] R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
    [Bibtex] 
    @article{J19,
author = {Ghaida, R. S. and Gupta, P.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {design rules, technology assessment, dre, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J19_paper.pdf},
title = {{DRE}: a {F}ramework for {E}arly {C}o-{E}valuation of {D}esign {R}ules, {T}echnology {C}hoices, and {L}ayout {M}ethodologies},
year = {2012}
}

    [34] [PDF] R. S. Ghaida, “Design enablement and design-centric assessment of future semiconductor technologies,” PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012.
    [Bibtex] 
    @phdthesis{PHDTH3,
author = {Ghaida, R. S.},
institution = {Department of Electrical Engineering, University of California Los Angeles},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/PHDTH3_paper.pdf},
title = {Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies},
year = {2012}
}

    [35] [PDF] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, “Layout Decomposition and Legalization for Double-Patterning Technology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
    [Bibtex] 
    @article{J27,
author = {Ghaida, R. S. and Agarwal, K. B. and Nassif, S. R. and Yuan, X. and Liebmann, L. W. and Gupta, P.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi, multiple-patterning},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J27_paper.pdf},
title = {{L}ayout {D}ecomposition and {L}egalization for {D}ouble-{P}atterning {T}echnology},
year = {2012}
}

    [36] R. S. Ghaida, M. Gupta, and P. Gupta, “A framework for exploring the interaction between design rules and overlay control,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2012.
    [Bibtex] 
    @conference{W11,
author = {Ghaida, R. S. and Gupta, M. and Gupta, P.},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W11},
keywords = {dats, dre, design rules, overlay, alignment, process, multiple-patterning, lithography},
title = {A Framework for Exploring the Interaction Between Design Rules and Overlay Control},
year = {2012}
}

    [37] [PDF] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A Framework for Double Patterning-Enabled Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011.
    [Bibtex] 
    @inproceedings{C59,
author = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C59},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C59_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C59_slides.pdf},
title = {A {F}ramework for {D}ouble {P}atterning-{E}nabled {D}esign},
year = {2011}
}

    [38] [PDF] A. A. Kagalwalla, P. Gupta, D. Hur, and C. Park, “Defect-aware Reticle Floorplanning for EUV Masks,” in SPIE Advanced Lithography, 2011.
    [Bibtex] 
    @inproceedings{C57,
author = {Kagalwalla, Abde Ali and Gupta, Puneet and Hur, Duck-Hyung and Park, Chul-Hong },
booktitle = {{SPIE Advanced Lithography}},
category = {C57},
keywords = {EUV, floorplanning, dats},
month = {March},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C57_paper.pdf},
title = {{D}efect-aware {R}eticle {F}loorplanning for {EUV} {M}asks},
year = {2011}
}

    [39] [PDF] T. B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2011.
    [Bibtex] 
    @article{J15,
author = {Chan, T.B. and Kagalwalla, Abde Ali and Gupta, P. },
journal = {{SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3)}},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J15_paper.pdf},
title = {{M}easurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},
year = {2011}
}

    [40] [PDF] J. Lee and P. Gupta, “Parametric hierarchy recovery for layout extracted netlists,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2011.
    [Bibtex] 
    @conference{W10,
author = {Lee, John and Gupta, Puneet},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W10},
keywords = {dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W10_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/W10_slides.pdf},
title = {Parametric Hierarchy Recovery for Layout Extracted Netlists},
year = {2011}
}

    [41] [PDF] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware Mask Inspection,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010.
    [Bibtex] 
    @inproceedings{C52,
author = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C52},
keywords = {mask manufacturing, inspection, dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C52_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C52_slides.pdf},
title = {{D}esign-aware {M}ask {I}nspection},
year = {2010}
}

    [42] [PDF] T. -B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010.
    [Bibtex] 
    @inproceedings{C53,
author = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C53},
keywords = {process variation, process monitoring, dats},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C53_slides.pdf},
title = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},
year = {2010}
}

    [43] [PDF] T. -B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” in Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration, 2010.
    [Bibtex] 
    @inproceedings{C46,
author = {Chan, T.-B. and Kagalwalla, Abde Ali and Gupta, P.},
booktitle = {{Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration}},
category = {C46},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C46_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C46_slides.pdf},
title = {Measurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},
year = {2010}
}

    [44] [PDF] T. -B. Chan and P. Gupta, “On Electrical Modeling of Imperfect Diffusion Patterning,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010.
    [Bibtex] 
    @inproceedings{C45,
author = {Chan, T.-B. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on VLSI Design}},
category = {C45},
keywords = {dats, mad},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C45_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C45_slides.pdf},
title = {On {E}lectrical {M}odeling of {I}mperfect {D}iffusion {P}atterning},
year = {2010}
}

    [45] [PDF] P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, “Electrical Assessment of Lithographic Gate Line-End Patterning,” spieJ, 2010.
    [Bibtex] 
    @article{J11,
author = {Gupta, P. and Jeong, K. and Kahng, A.B. and Park, C.-H.},
journal = {{spieJ}},
keywords = {mad, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J11_paper.pdf},
title = {Electrical {A}ssessment of {L}ithographic {G}ate {L}ine-{E}nd {P}atterning},
year = {2010}
}

    [46] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware Mask Inspection,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010.
    [Bibtex] 
    @conference{W6,
author = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W6},
keywords = {dats},
title = {{D}esign-aware {M}ask {I}nspection},
year = {2010}
}

    [47] [PDF] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,” IEEE Transactions on Semiconductor Manufacturing, 2010.
    [Bibtex] 
    @article{J13,
author = {Ghaida, R. S. and Torres, G. and Gupta, P.},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {double patterning, stdpl, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J13_paper.pdf},
title = {{S}ingle-{M}ask {D}ouble-{P}atterning {L}ithography for {R}educed {C}ost and {I}mproved {O}verlay {C}ontrol},
year = {2010}
}

    [48] V. Popuri, P. Gupta, and S. Pamarti, “Bias-Driven Robust Analog Circuit Sizing Scheme,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010.
    [Bibtex] 
    @conference{W8,
author = {Popuri, V. and Gupta, P. and Pamarti, S.},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W8},
keywords = {dats},
title = {{Bias-Driven Robust Analog Circuit Sizing Scheme}},
year = {2010}
}

    [49] [PDF] R. S. Ghaida and P. Gupta, “Within-Layer Overlay Impact for Design in Metal Double Patterning,” IEEE Transactions on Semiconductor Manufacturing, 2010.
    [Bibtex] 
    @article{J10,
author = {Ghaida, R. S. and Gupta, P.},
journal = {{IEEE Transactions on Semiconductor Manufacturing}},
keywords = {double patterning, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J10_paper.pdf},
title = {Within-{L}ayer {O}verlay {I}mpact for {D}esign in {M}etal {D}ouble {P}atterning},
year = {2010}
}

    [50] [PDF] R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic Evaluation of Design Rules,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2009.
    [Bibtex] 
    @inproceedings{C44,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C44},
keywords = {dats, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C44_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C44_slides.pdf},
title = {A {F}ramework for {E}arly and {S}ystematic {E}valuation of {D}esign {R}ules},
year = {2009}
}

    [51] [PDF] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2009.
    [Bibtex] 
    @inproceedings{C41,
author = {Ghaida, R. S. and Torres, G. and Gupta, P.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
keywords = {dats},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C41_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C41_slides.pdf},
title = {Single-{M}ask {D}ouble-{P}atterning {L}ithography},
year = {2009}
}

    [52] [PDF] R. S. Ghaida and P. Gupta, “Design-Overlay Interactions in Metal Double Patterning,” in SPIE Advanced Lithography Symposium, 2009.
    [Bibtex] 
    @inproceedings{C40,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{SPIE Advanced Lithography Symposium}},
keywords = {double patterning, test pattern, dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C40_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C40_slides.pdf},
title = {Design-{O}verlay {I}nteractions in {M}etal {D}ouble {P}atterning},
year = {2009}
}

    [53] T. -B. Chan, P. Gupta, V. Balakrishnan, and Y. Cao, “Extended Burn-in for Reduced Vth Variation,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2009.
    [Bibtex] 
    @conference{W4,
author = {Chan, T.-B. and Gupta, Puneet and Balakrishnan, Varsha and Cao, Yu},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W4},
keywords = {dats},
title = {{E}xtended {B}urn-in for {R}educed {V}th {V}ariation},
year = {2009}
}

    [54] R. S. Ghaida and P. Gupta, “A Framework for Systematic Evaluation and Exploration of Design Rules,” in SRC TECHCON’09, 2009.
    [Bibtex] 
    @conference{W1,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{SRC TECHCON'09}},
category = {W1},
keywords = {dats},
month = {},
pages = {},
title = {A {F}ramework for {S}ystematic {E}valuation and {E}xploration of {D}esign {R}ules},
year = {2009}
}

    [55] P. Gupta and D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2009.
    [Bibtex] 
    @inproceedings{C42,
author = {Gupta, P. and Reinhard, D.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
category = {C42},
keywords = {dats},
month = {},
title = {On {C}omparing {C}onventional and {E}lectrically {D}riven {OPC} {T}echniques},
year = {2009}
}

    [56] [PDF] P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, “Electrical Metrics for Lithographic Line-End Tapering,” in SPIE Photomask and NGL Mask Technology, 2008.
    [Bibtex] 
    @inproceedings{C36,
author = {Gupta, P. and Jeong, K. and Kahng, A. B. and Park, C.-H},
booktitle = {{SPIE Photomask and NGL Mask Technology}},
category = {C36},
keywords = {mad, dats},
month = {April},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C36_paper.pdf},
title = {Electrical {M}etrics for {L}ithographic {L}ine-{E}nd {T}apering},
year = {2008}
}

    [57] [PDF] P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, “Shaping Gate Channels for Improved Devices,” in SPIE Advanced Lithography Symposium, 2008.
    [Bibtex] 
    @inproceedings{C35,
author = {Gupta, P. and Kahng, A. B. and Shah, S. and Sylvester, D.},
booktitle = {{SPIE Advanced Lithography Symposium}},
category = {C35},
keywords = {dats, mad},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C35_paper.pdf},
title = {Shaping {G}ate {C}hannels for {I}mproved {D}evices},
year = {2008}
}

    [58] P. Gupta, “Challenges at 45nm and Beyond,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2008.
    [Bibtex] 
    @conference{ITT8,
author = {Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {ITT8},
keywords = {mad, dats},
note = {Panel Discussion},
title = {Challenges at 45nm and {B}eyond},
year = {2008}
}

    [59] P. Gupta, “The Electrical Design Manufacturing Interface,” in Electronic Design Processes Workshop, 2008.
    [Bibtex] 
    @conference{ITT5,
author = {Gupta, P.},
booktitle = {{Electronic Design Processes Workshop}},
category = {ITT5},
keywords = {mad, dats},
title = {The {E}lectrical {D}esign {M}anufacturing {I}nterface},
year = {2008}
}

    [60] [PDF] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven Optical Proximity Correction for Mask Cost Reduction,” spieJ, 2007.
    [Bibtex] 
    @article{J8,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
category = {J8},
journal = {{spieJ}},
keywords = {dats},
month = {September},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J8_paper.pdf},
title = {Performance-{D}riven {O}ptical {P}roximity {C}orrection for {M}ask {C}ost {R}eduction},
year = {2007}
}

    [61] [PDF] P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, “Line End Shortening is not Always a Failure,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2007.
    [Bibtex] 
    @inproceedings{C33,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C2},
keywords = {mad, dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C33_paper.pdf},
title = {Line {E}nd {S}hortening is not {A}lways a {F}ailure},
year = {2007}
}

    [62] [PDF] P. Gupta, A. B. Kahng, C. -H. Park, K. Samadi, and X. Xu, “Wafer Topography-Aware Optical Proximity Correction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2006.
    [Bibtex] 
    @article{J5,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Samadi, K. and Xu, X.},
category = {J5},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats},
month = {April},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J5_paper.pdf},
title = {Wafer {T}opography-{A}ware {O}ptical {P}roximity {C}orrection},
year = {2006}
}

    [63] [PDF] P. Gupta, A. B. Kahng, S. Muddu, O. S. Nakagawa, and C. -H. Park, “Modeling OPC Complexity for Design for Manufacturability,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2005.
    [Bibtex] 
    @inproceedings{C25,
author = {Gupta, P. and Kahng, A. B. and Muddu,S. and Nakagawa, O.S. and Park, C.-H.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
category = {C25},
keywords = {dats},
month = {October},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C25_paper.pdf},
title = {Modeling {OPC} {C}omplexity for {D}esign for {M}anufacturability},
year = {2005}
}

    [64] [PDF] Y. Zhang, R. Gray, O. S. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and C. Progler, “Interaction and Balance of Mask Write Time and Design RET Strategies,” in SPIE Photomask and NGL Mask Technology, 2005.
    [Bibtex] 
    @inproceedings{C26,
author = {Zhang, Y. and Gray, R. and Nakagawa, O.S. and Gupta, P. and Kamberian, H. and Xiao, G. and Cottle, R. and Progler, C.},
booktitle = {{SPIE Photomask and NGL Mask Technology}},
category = {C26},
keywords = {dats},
month = {April},
pages = {},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C26_paper.pdf},
title = {Interaction and {B}alance of {M}ask {W}rite {T}ime and {D}esign {RET} {S}trategies},
year = {2005}
}

    [65] [PDF] P. Gupta, A. B. Kahng, and C. -H. Park, “Improving OPC Quality Via Interactions Within the Design-to-Manufacturing Flow,” in SPIE Photomask and NGL Mask Technology, 2005.
    [Bibtex] 
    @inproceedings{IP3,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H.},
booktitle = {{SPIE Photomask and NGL Mask Technology}},
category = {IP3},
keywords = {dats},
month = {April},
note = {Invited Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP3_paper.pdf},
title = {Improving {OPC} {Q}uality {V}ia {I}nteractions {W}ithin the {D}esign-to-{M}anufacturing {F}low},
year = {2005}
}

    [66] [PDF] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven OPC for Mask Cost Reduction,” in IEEE International Symposium on Quality Electronic Design, 2005, pp. 270-275.
    [Bibtex] 
    @inproceedings{C17,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{IEEE International Symposium on Quality Electronic Design}},
category = {C17},
keywords = {dats},
month = {March},
pages = {270-275},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C17_paper.pdf},
title = {Performance-{D}riven {OPC} for {M}ask {C}ost {R}eduction},
year = {2005}
}

    [67] [PDF] P. Gupta, A. B. Kahng, C. -H. Park, K. Samadi, and X. Xu, “Topography-Aware Optical Proximity Correction for Better DOF margin and CD Control,” in SPIE Photomask and NGL Mask Technology, 2005.
    [Bibtex] 
    @inproceedings{C22,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Samadi, K. and Xu, X. },
booktitle = {{SPIE Photomask and NGL Mask Technology}},
category = {C22},
keywords = {dats},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C22_paper.pdf},
title = {Topography-{A}ware {O}ptical {P}roximity {C}orrection for {B}etter {DOF} margin and {CD} {C}ontrol},
year = {2005}
}

    [68] [PDF] P. Gupta, A. B. Kahng, C. -H. Park, P. Sharma, D. Sylvester, and J. Yang, “Joining the Design and Mask Flows for Better and Cheaper Masks,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2004.
    [Bibtex] 
    @inproceedings{IP2,
author = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Sharma, P. and Sylvester, D. and Yang, J.},
booktitle = {{SPIE/BACUS Symposium on Photomask Technology and Management}},
category = {IP2},
keywords = {dats},
month = {September},
note = {Invited Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP2_paper.pdf},
title = {Joining the {D}esign and {M}ask {F}lows for {B}etter and {C}heaper {M}asks},
year = {2004}
}

    [69] [PDF] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward a Methodology for Manufacturability Driven Design Rule Exploration,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2004.
    [Bibtex] 
    @inproceedings{C16,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C16},
keywords = {dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C16_paper.pdf},
title = {Toward a {M}ethodology for {M}anufacturability {D}riven {D}esign {R}ule {E}xploration},
year = {2004}
}

    [70] [PDF] P. Gupta, F. -L. Heng, and M. Lavin, “Merits of Cellwise Model-Based OPC,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2004.
    [Bibtex] 
    @inproceedings{C11,
author = {Gupta, P. and Heng, F.-L. and Lavin, M. },
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {C11},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C11_paper.pdf},
title = {Merits of {C}ellwise {M}odel-{B}ased {OPC}},
year = {2004}
}

    [71] [PDF] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Investigation of Performance Metrics for Interconnect Stack Architectures,” in Proc. g SLIP, 2004.
    [Bibtex] 
    @inproceedings{C13,
author = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},
booktitle = {{Proc. g SLIP}},
category = {C13},
keywords = {dats},
month = {February},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C13_paper.pdf},
title = {Investigation of {P}erformance {M}etrics for {I}nterconnect {S}tack {A}rchitectures},
year = {2004}
}

    [72] [PDF] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2003.
    [Bibtex] 
    @inproceedings{C7,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C7},
keywords = {sizing, dats},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C7_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C7_slides.pdf},
title = {A {C}ost-{D}riven {L}ihographic {C}orrection {M}ethodology {B}ased on {O}ff-the-{S}helf {S}izing {T}ools},
year = {2003}
}

    [73] [PDF] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward Performance-Driven Reduction of the Cost of RET-based Lithography Control,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 2003.
    [Bibtex] 
    @inproceedings{IP1,
author = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},
booktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},
category = {IP1},
keywords = {dats},
month = {February},
note = {Invited Paper},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/IP1_paper.pdf},
title = {Toward {P}erformance-{D}riven {R}eduction of the {C}ost of {RET}-based {L}ithography {C}ontrol},
year = {2003}
}