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Download request form is located at the bottom of this page. Note that we have public source code repositories hosted at https://github.com/nanocad-lab. Research data is available upon request. For downloads of research data, please contact the authors of the relevant paper, or email Prof. Puneet Gupta directly.

3PXNet

3PXNet is a training (PyTorch) and inference (C) library for implementing highly compact binarized-sparse neural networks targeting edge devices.

You can find the libraries at:
https://github.com/nanocad-lab/3pxnet-training
https://github.com/nanocad-lab/3pxnet-inference

Publications
    [1] [PDF] W. Romaszkan, T. Li, and P. Gupta, “3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning,” ACM Transactions on Embedded Computing Systems (TECS), 2019.
    [Bibtex] 
    @article{J63,
author = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},
journal = {{ACM Transactions on Embedded Computing Systems (TECS)}},
keywords = {mledge, 3pxnet},
month = {November},
publisher = {ACM},
title = {{3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning}},
year = {2019}
}

UCLA_EUV CDA_

UCLA_EUV_CDA is a tool written in C++ for computing the mask yield of EUV layouts while accounting for EUV mask blank defect avoidance techniques like pattern sift and rotation.

EUV CDA

DSA_pathfind

DSA_pathfind is a framework for DSA technology path-finding, for via layers, to be used by the foundry as part of Design and Technology Co-optimization (DTCO). The framework optimally evaluates a DSA-based technology where an arbitrary lithography technique is used to print the guiding templates, possibly using many masks/exposures and provides a design-friendliness metric. In addition, if the evaluated technology is not design-friendly, the framework provides a diagnosis of the failures, and computes the minimum-cost technology change that makes the technology design-friendly.

DSA Pathfind

X-Mem

X-Mem is a flexible software tool for characterizing modern memory hierarchies in a variety of ways. The tool was developed jointly by Microsoft and our lab to address emerging challenges particular to cloud computing. X-Mem was originally authored by lab member Mark Gottscho as a Summer 2014 Ph.D. intern at Microsoft Research. To benefit the research and development community, we have open-sourced the code under the MIT License. Project homepage: https://github.com/nanocad-lab/X-Mem

UCLA_DRE

UCLA_DRE is a tool written in C++ that essentially creates a virtual standard-cell library for evaluating and exploring design rules, technology choices, and layout methodologies in terms of area, yield, and variability. A chip-level evaluation of design rules now also exists.

Publications
    [1] [PDF] [PDF Slides] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, 2014.
    [Bibtex] 
    @inproceedings{C74,
author = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,dre},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C74_slides.pdf},
title = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},
year = {2014}
}

    [2] [PDF] R. S. Ghaida, M. Gupta, and P. Gupta, “A Framework for Exploring the Interaction between Design Rules and Overlay Control,” in SPIE Advanced Lithography, 2013.
    [Bibtex] 
    @inproceedings{C69,
author = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},
booktitle = {{SPIE Advanced Lithography}},
category = {C69},
keywords = {overlay, design rules, dre, alignment},
month = {Feburary},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C69_paper.pdf},
title = {A {F}ramework for {E}xploring the {I}nteraction between {D}esign {R}ules and {O}verlay {C}ontrol},
year = {2013}
}

    [3] [PDF] [PDF Slides] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, “A methodology for the early exploration of design rules for multiple-patterning technologies,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012.
    [Bibtex] 
    @inproceedings{C64,
author = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C64},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C64_slides.pdf},
title = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},
year = {2012}
}

    [4] [PDF] [PDF Slides] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,” in Intl. Conf. on IC Design and Technology, 2012.
    [Bibtex] 
    @inproceedings{IP9,
author = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},
booktitle = {{Intl. Conf. on IC Design and Technology}},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ip9_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/ip9_slides.pdf},
title = {O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction},
year = {2012}
}

    [5] [PDF] R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
    [Bibtex] 
    @article{J19,
author = {Ghaida, R. S. and Gupta, P.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {design rules, technology assessment, dre, dats},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J19_paper.pdf},
title = {{DRE}: a {F}ramework for {E}arly {C}o-{E}valuation of {D}esign {R}ules, {T}echnology {C}hoices, and {L}ayout {M}ethodologies},
year = {2012}
}

    [6] [PDF] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, “Layout Decomposition and Legalization for Double-Patterning Technology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.
    [Bibtex] 
    @article{J27,
author = {Ghaida, R. S. and Agarwal, K. B. and Nassif, S. R. and Yuan, X. and Liebmann, L. W. and Gupta, P.},
journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi, multiple-patterning},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J27_paper.pdf},
title = {{L}ayout {D}ecomposition and {L}egalization for {D}ouble-{P}atterning {T}echnology},
year = {2012}
}

    [7] R. S. Ghaida, M. Gupta, and P. Gupta, “A framework for exploring the interaction between design rules and overlay control,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2012.
    [Bibtex] 
    @conference{W11,
author = {Ghaida, R. S. and Gupta, M. and Gupta, P.},
booktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},
category = {W11},
keywords = {dats, dre, design rules, overlay, alignment, process, multiple-patterning, lithography},
title = {A Framework for Exploring the Interaction Between Design Rules and Overlay Control},
year = {2012}
}

    [8] [PDF] [PDF Slides] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A Framework for Double Patterning-Enabled Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011.
    [Bibtex] 
    @inproceedings{C59,
author = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C59},
keywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C59_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C59_slides.pdf},
title = {A {F}ramework for {D}ouble {P}atterning-{E}nabled {D}esign},
year = {2011}
}

    [9] [PDF] [PDF Slides] R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic Evaluation of Design Rules,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2009.
    [Bibtex] 
    @inproceedings{C44,
author = {Ghaida, R. S. and Gupta, P.},
booktitle = {{Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}},
category = {C44},
keywords = {dats, design rules, dre, dmi},
month = {November},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C44_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C44_slides.pdf},
title = {A {F}ramework for {E}arly and {S}ystematic {E}valuation of {D}esign {R}ules},
year = {2009}
}

Pattern DRE UCLA DRE

PROCEED

PROCEED is a tool written in MATLAB for evaluating and exploring emerging Boolean devices in the context of circuit designs. The tool takes a device model (compatible with SPICE) and logic depth histogram of a digital circuit as input and evaluates trade-off of power, minimum working clock period, and area of the digital circuit design. It models and performs circuit optimizations including picking best supply voltage and threshold voltage, gate sizing, and dynamic voltage and frequency scaling. It outputs metrics of design power, minimum working clock period, and design area inwide ranges (up to several orders of magnitudes).

Publications
    [1] [PDF] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “Proceed: a pareto optimization-based circuit-level evaluator for emerging devices,” IEEE Transactions on Very Large Scale Integration Systems, 2015.
    [Bibtex] 
    @article{J37,
author = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
journal = {{IEEE Transactions on Very Large Scale Integration Systems}},
keywords = {Emerging device, evaluator, proceed },
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/J37_paper.pdf},
title = {PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices},
year = {2015}
}

    [2] [PDF] [PP Slides] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “PROCEED: a Pareto Optimization-based Circuit-level Evaluator for Emerging Devices,” in Proc. Asia and South Pacific Design Automation Conference, 2014.
    [Bibtex] 
    @inproceedings{C75,
author = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},
booktitle = {{Proc. Asia and South Pacific Design Automation Conference}},
keywords = {dats,proceed},
month = {January},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C75_paper.pdf},
slideurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C75_slides.pptx},
title = {{PROCEED:} A {P}areto {O}ptimization-based {C}ircuit-level {E}valuator for {E}merging {D}evices},
year = {2014}
}

PROCEED

MRAM_Switching_Model

MRAM_Switching_Model is a Monte-Carlo simulator, which can simulate the switching behavior and failure rate of the STT-MTJ and the VC-MTJ. It is a LLG equation based model including voltage-controlled magnetic anisotropy effect, Spin-transfer torque effect, temperature dependence, and thermal fluctuation. The model is written in C++ and CUDA. If you use this software or a modified version of it, please cite the most relevant among the following papers:

MRAM Switching Model

UCLA_TIMER

UCLA_TIMER: An enhanced OAGear-Static-Timer with SPEF-reading, Elmore-based wire delay calculation, power calculation, and Greedy Heuristic for Gate Sizing.

UCLA Timer

UCLA_SHAPE

uclaShape: uclaShape API is an extension of oaShape in Open Access, It is implemented by boost library 1.45.0. and Open Access.It allows users to do basic operations between layers that Open Access API does not provide.

UCLA Shape

RDSim

An efficient Reaction-diffusion model to simulate NBTI degradation.

Publications

UCLA_Eyecharts

UCLA_Eyecharts is a tool to generate benchmark circuits (called eyecharts) of arbitrary size along with their optimal solutions calculated using dynamic programming. The tool evaluates the suboptimalities of some popular gate sizing algorithms and helps diagnose weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research.

Publications
    [1] [PDF] P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2010.
    [Bibtex] 
    @inproceedings{C50,
author = {Gupta, Puneet and Kahng, Andrew and Kasibhatla, Amarnath and Sharma, Puneet},
booktitle = {{Proc. ACM/IEEE Design Automation Conference (DAC)}},
category = {C50},
keywords = {sizing, eyecharts},
month = {June},
paperurl = {https://nanocad.ee.ucla.edu/pub/Main/Publications/C50_paper.pdf},
title = {{E}yecharts: {C}onstructive {B}enchmarking of {G}ate {S}izing {H}euristics},
year = {2010}
}

UCLA_Eyecharts

UCLA_ENCOUNTER_TCL_SIZING

UCLA_ENCOUNTER_TCL_SIZING: Implementations of greedy and LP slack assignment heuristics for gate sizing. Implemented in TCL for Cadence Encounter. Methods implemented are:

Greedy Sizing Power: Sizing method similar to TILOS (Fishburn and Dunlop, “TILOS: a Posynomial Programming Approach to Transistor Sizing”, 1985). Starts with a timing-infeasible design, and iteratively sizes the critical path using a greedy Delay/Power metric until the design is timing-feasible.

Greedy Sizing Recover Power: Starts with a timing-feasible design, and trades power for slack using a greedy Power/Delay metric until no improvements are possible.

LP Slack Allocation: Starts with a timing-feasible design, and iterates between allocating slack using linear programming, and converting the allocated slacks for power savings using gate sizing. This implementation follows the work in Nguyen, Davare, Orshansky, Chinnery, Thompson, and Keutzer, “Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization,” 2003.

UCLA Encounter TCL Sizing