NanoCAD lab focuses its research efforts on cross-domain interactions in the integrated circuit application-architecture-design-manufacturing flow with emphasis on the VLSI design-manufacturing interface.

NEWS

2012

Prof. Gupta has been selected to receive 2012 IBM Faculty Award.

2011

Gate-length biasing - a design-aware manufacturing technique co-invented by Prof. Gupta reaches the Trillion Watt Hour energy saving mark. See the press release here. This and this paper formed the basis of the company Blaze DFM, that Prof. Gupta co-founded.

SRC issued a press release on the recent "Design-Dependent Process Monitoring" work in Nano CAD Lab. See the press release here. Read the related ICCAD 2010 paper here.

Prof. Gupta gives a half-day tutorial on "Designing for uncertainty: Addressing process variations and aging issues in VLSI designs", at the IEEE International Symposium on VLSI Design, Automation and Test in Hsinchu, Taiwan. See the slides here.

Congratulations and best of luck to Santiago and Parag for their new jobs at Altera.

2010

UCLA is part of the team winning one of the NSF Expeditions in Computing! See http://www.variability.org. Work done in Nano CAD Lab was the primary driver behind the expedition. See the press release here.

Prof. Puneet Gupta receives 2010 SRC Inventor Recognition Award for patent application titled "Single-Mask Double-Patterning Lithography".

Best of luck to Aashish at Mentor Graphics, Amarnath at Intel and Lerong at Sandisk in their new jobs.

Prof. Puneet Gupta receives 2010 ACM/SIGDA Outstanding New Faculty Award. The award was given at DAC 2010 opening ceremony.

Congratulations to Aashish Pant for getting Outstanding M.S. Award from EE Department.

Congratulations to Lerong Cheng for defending his Ph.D. thesis!

2009

Prof. Puneet Gupta receives 2009 SRC Inventor Recognition Award for the US Patent titled "Method for correcting a mask layout" (number 7,149,999).

Prof. Puneet Gupta has been awarded 2009 NSF Faculty Early Career Development (CAREER) Award for his proposal titled ``CAREER: Co-optimization of Integrated Circuit Design and Manufacturing''. See NSF website for further details.

NanoCAD Lab settles in its home at 53-109 Engr. IV! The lab furniture is here. Welcome everyone!