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CHICO Workshop 2024

CHICO 2024

Workshop on Chiplet-based Heterogeneous Integration and CO-design

June 23, 2024
Moscone Center
San Francisco, CA

Contemporary microelectronic design is facing tremendous challenges in memory bandwidth, processing speed, and power consumption. Although recent advances in monolithic design (e.g. near-memory and in-memory computing) help relieve some issues, the scaling trend is still lagging behind the ever increasing demand of AI, HPC and other applications.

In this context, technological innovations beyond a monolithic chip, such as 2.5D and 3D packaging at the macro and micro levels, are critical to enabling heterogeneous integration with various types of chiplets, and bringing significant performance and cost benefits for future systems. Such a paradigm shift further drives new innovations on chiplet IPs, heterogeneous architectures, and system mapping.

Organizers

Yu (Kevin) Cao, University of Minnesota Twin Cities

Puneet Gupta, University of California, Los Angeles

This workshop is designed to be a forum that is highly interactive, timely and informative, on the related topics:

  • Roadmap and technology perspectives of heterogeneous integration
  • IP definition of chiplets
  • Signaling interface cross chiplets
  • Network topology for data movement
  • Design solutions for power delivery
  • Thermal management
  • Testing in a heterogeneous system
  • High-level synthesis for the chiplet system
  • Architectural innovations
  • Ecosystems of IPs and EDA tools

Proposed Format: The format of the workshop will consist of multiple invited presentations from industry, academia, and government funding agencies. We will also organize a panel for discussions.

Intended Audience: Industry and academic researchers, funding agencies, IP providers, EDA tool vendors, foundry

Workshop Schedule (tentative)

TimeActivity
8:30am – 9:00amIntroduction and opening remarks
9:00am – 11:30amSession 1: Chiplet-based 2.5D/3D System

1. Robert Patti, Nhanced: Hybrid Bonding: Tools and Techniques Enabling Advanced Packaging (9:00am)

Robert S. Patti is the founder and President of NHanced Semiconductors and CTO of Tezzaron Semiconductor. Previously, Mr. Patti was a Member of Technical Staff for Tellabs, Inc. He then founded ASIC Designs, Inc., specializing in high-performance systems and ASICs. He served as its President for twelve years and participated in the design of over 100 chips. He co-founded Tezzaron and has served as its CTO for 18 years, using wafer-level stacking processes to create ultra-high-density 3D memory products and other semiconductor sub-components. He is a member of IEEE, the Tezzaron Board of Directors, and the Rose-Hulman Nano-Technology Advisory Board. He received the SEMI Award for North America in 2009 and in 2015 received the 3DIncites Individual Achievement Award. Mr. Patti also served as Vice-Chairman of JEDEC’s DDRIII / Future Memories Task Group. Mr. Patti holds 20 US patents, numerous foreign patents, and more than a dozen pending patent applications in sub-micron semiconductor chip technologies.

2. Lalitha Immaneni, Intel: Advanced Packaging Manufacturing – Challenges and Opportunities (9:30am)

Lalitha Immaneni is a Vice President of Semiconductor Research & Development in the Assembly Test Technology Development organization for Intel Corporation. Lalitha manages a world class and diverse team of packaging architects, designers, and specialized engineers in the “Architecture, Design & Technology Solutions” group, spanning multiple geographies (USA, Malaysia, and India).  She is responsible for developing substrate/silicon, assembly, and board design rules, designing essential building blocks for emerging packaging technologies, developing electrical and physical design methodologies for packaging as well as delivering product package architectures, supporting product electrical analysis, and executing product designs for Intel.   She is also responsible for the thermal, mechanical, and electrical analysis of Intel’s packaging choices and the implications across the product envelopes while also delivering industry leading power delivery and HSIO solutions. She drives the Intel pathfinding & development roadmap for all packaging technologies. Lalitha owns the vision and execution of a centralized package and board flows/tools as well as the enabling of the EDA ecosystem readiness for Intel’s packaging and board design needs. She owns the package architecture and design enabling services for Intel Foundry. Lalitha is a global leader and role model with a 30-year track record of stellar technical achievement in the semiconductor packaging industry.  Her technical accomplishments include leading Intel through multiple transitions in the package design tools towards better efficiency and quality. Widely recognized within the packaging EDA partner community, Lalitha is known for driving design tool capabilities for die disaggregation.  She has led many “firsts,” including enabling the definition of the first industry EDA packaging tool and leading package co-design for the first Foveros and EMIB products. She recently led the Package Assembly Design Kit delivery for Intel foundry Services and is currently focused on EDA ecosystem enablement, interoperable formats, and standards for chiplets. 

As a staunch believer in the power of DEI initiatives, Lalitha volunteers extensively as a coach and mentor for Positive Paths, a non-profit organization serving women in Phoenix.   She is a co-chair for the Intel Network of Executive Women (iNEW) and an executive co-sponsor for the Intel Network of Intel African Ancestry (NIA).  She is a renowned mentor and coach to countless engineers within and outside Intel. 
Lalitha holds a master’s degree from Arizona State University with an emphasis on computer graphics & software engineering.

3. Muhannad Bakir, GaTech: Advanced Packaging in the New Era of Moore’s Law (10:00am)

Mohan received his Ph.D. in Chemistry from Indian Institute of Science, Bangalore in 1994. He received his MS and BS degrees in Chemistry from Madras Christian College, Chennai. Following a 4 year stay in Japan as a visiting researcher at KAST and Waseda University, he worked as a research associate/scientist in Chemistry and College of Optics at the University of Arizona. He then joined Nitto Denko Technical Corporation as a research scientist in 2005 and went on to become an associate director, leading a team with a focus on developing waveguide/electrooptic, photorefractive and high-K capacitor materials. Mohan joined as a Senior research scientist at Georgia Tech’s Chemistry department in 2010 and currently he is a senior research engineer at ECE and the 3D Systems Packaging Research Center. His current research interests include advanced materials and processes for packaging with a focus on heterogeneous integration targeting applications in AI/HPC and 5G & beyond. Mohan is also interested in hybrid/photosensitive materials with very large breakdown strength/high temperature stability for energy storage/electronics/photonics applications as well as a special interest in multi-photon based fabrication and imaging studies of complex structures.

4. Nhat Nguyen, Ayar Labs: UCIe Optical Chiplets for AI/ML Compute Clusters (10:30am)

Nhat Nguyen received the B.S. degrees with highest honors in computer engineering, computer science, and mathematics from Portland State University, Oregon, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley. He worked at Hewlett, MicroUnity, and Rambus in various technical and management roles. He was also an adjunct professor at San Jose State University, California. Since 2021 he has been at Ayar Labs managing the architecture team. He has published one book chapter and authored over 30 journal and conference papers.  He holds over 30 U.S. patents.

5. Inna Partin-Vaisband, UIC: Vertical Power Delivery for High-Performance Chiplet-Based Systems (11:00am)

Inna P.-Vaisband is an Assistant Professor of Electrical and Computer Engineering and holds an appointment as a Courtesy Assistant Professor of Computer Science at the University of Illinois Chicago. She received the B.Sc. in computer science and M.Sc. in electrical engineering from the Technion-Israel Institute of Technology, Haifa, Israel, in, respectively, 2006 and 2009, and the Ph.D. degree in electrical engineering from the University of Rochester, Rochester, New York, in 2015. Between 2003 and 2009, Dr. P.-Vaisband held a variety of software and hardware R&D positions at Tower Semiconductor Ltd., G-Connect Ltd., and IBM Ltd., all in Israel. Dr. P.-Vaisband is an Associate Editor of the Microelectronics Journal.

Her research is currently focused on innovation in the areas of artificially intelligent hardware, hardware security, and electronic design automation.  Special emphasis is placed on analog and mixed-signal circuits and integrated power delivery and management. Her research into heterogeneous power delivery and management has been published in her book On-Chip Power Delivery and Management, 4th Edition. A distributed system of ultra-small high-efficiency on-chip power supplies previously designed, fabricated, and tested by her was in mass production within the Galaxy S5 android smart phones as part of the Qualcomm Snapdragon product line. She is the recipient of the 2022 Google Research Scholar Award and the 2023 NSF CAREER Award.
11:30am – 12:00pmMorning Panel Discussion: Joint with all invited speakers
12:00am – 2:00pmLunch
2:00pm – 5:00pmSession 2: Ecosystem for chiplet-based integration

1. Marek Hempel, Analog Devices: The Open Chiplet Economy: Current Status and Future Challenges (2:00pm)

Marek Hempel is a Staff Process Development Engineer in the CTO’s office of Analog Devices. Since joining ADI in 2021, Marek has focused on driving projects and developing a strategy for heterogeneous integration and chiplets, including D2D interface selection, testability, and business case analyses. He also leads the ODSA Business subgroup, as part of the Open Compute Project, a group that addresses challenges of chiplet technology from a business aspect. Originally from Germany, Marek earned his bachelor’s and master’s degree in electrical engineering from Aachen University, Germany and completed his graduate studies in Electrical Engineering at MIT in the US.

2. Daniel Friedman, IBM: AI Chiplets in An Open Ecosystem:  Barriers and Solution Approaches (2:30pm)

Dr. Daniel Friedman is currently a Distinguished Research Scientist and Senior Manager of the Communication Circuits and Systems department, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA; he is also an IEEE Fellow. At IBM, he initially developed field-powered RFID tags before turning to high data rate wireline communication, high data rate wireless communication, and exploratory accelerators. His current research interests include accelerator designs for AI, high-speed I/O design, phase-locked-loop design, millimeter-wave circuits and systems, and circuit/system approaches to enabling new computing paradigms, the latter including cryogenic electronics for use in quantum computing systems. Among other contributions to the IEEE Solid-State Circuits Society, he has held technical program committee roles at ISSCC since 2009 and is the current SSCS Vice President.

3. Albert Zeng, Cadence: EDA at the Forefront: Mastering Multi-Physics Challenges in Heterogeneous Integration (3:00pm)

Sr Software Engineering Group Director at Cadence Design Systems; PhD, Texas A&M University, 2011. Thermal analysis, Power signoff, EMIR signoff, EDA on cloud, circuit simulation, parallel computing, distributed computing.

4. Nader Sehatbaksh, UCLA: Can Chiplet-based Heterogeneous Integration Enhance Security? (3:30pm)

Nader Sehatbakhsh is an Assistant Professor at the Department of Electrical and Computer Engineering at UCLA. His work is broadly focused on developing secure and private systems and architectures and particularly on computer architecture security, IoT security, and side channels. P. His work received various recognitions and awards including IEEE/ACM MICRO-49 Best Paper Award and NSF CAREER Award.

5. David Ratchkov, Anemoi Software: Chiplets: Standards, Workflows and Tools (4:00pm)

David Ratchkov is the CEO of Anemoi Software Inc., an EDA startup delivering best-in-class Chiplet Architecture Exploration tools, with focus on power, thermal and mechanical. He is also a co-load of the Chiplet Data Exchange (CDX) workstream under Open Compute’s Open Chiplet Economy sub-project. Previously David has worked at Broadcom (through the LSI acquisition). He holds numerous patents in the field of EDA related to modeling and PDN design. David holds Master’s Degree from University of Plovdiv, Bulgaria.
4:30pm – 5:00pmAfternoon Panel Discussion: Joint with all invited speakers

Related Links

Registration to the #61DAC! https://www.dac.com/Attend/Registration