Contemporary microelectronic design is facing tremendous challenges in memory bandwidth, processing speed and power consumption. Although recent advances in monolithic design (e.g. near-memory and in-memory computing) help relieve some issues, the scaling trend is still lagging behind the ever increasing demand of AI, HPC and other applications.

In this context, technological innovations beyond a monolithic chip, such as 2.5D and 3D packaging at the macro and micro levels, are critical to enabling heterogeneous integration with various types of chiplets, and bringing significant performance and cost benefits for future systems. Such a paradigm shift further drives new innovations on chiplet IPs, heterogeneous architectures and system mapping.

Organizers

Yu (Kevin) Cao, Arizona State University

Puneet Gupta, University of California, Los Angeles

Frank Liu, Oak Ridge National Lab

This workshop is designed to be a forum that is highly interactive, timely and informative, on the related topics:

• Roadmap and technology perspectives of heterogeneous integration
• IP definition of chiplets
• Signaling interface cross chiplets
• Network topology for data movement
• Design solutions for power delivery
• Thermal management
• High-level synthesis for the chiplet system
• Architectural innovations
• Ecosystems of IPs and EDA tools

Tentative Program