CHICO 2025
Workshop on Chiplet-based Heterogeneous Integration and CO-design
June 22, 2025
Moscone Center
San Francisco, CA
Contemporary microelectronic design is facing tremendous challenges in memory bandwidth, processing speed, and power consumption. Although recent advances in monolithic design (e.g. near-memory and in-memory computing) help relieve some issues, the scaling trend is still lagging behind the ever increasing demand of AI, HPC and other applications.
In this context, technological innovations beyond a monolithic chip, such as 2.5D and 3D packaging at the macro and micro levels, are critical to enabling heterogeneous integration with various types of chiplets, and bringing significant performance and cost benefits for future systems. Such a paradigm shift further drives new innovations on chiplet IPs, heterogeneous architectures, and system mapping.
Organizers
Yu (Kevin) Cao, University of Minnesota Twin Cities
Puneet Gupta, University of California, Los Angeles
This workshop is designed to be a forum that is highly interactive, timely and informative, on the related topics:
- Roadmap and technology perspectives of heterogeneous integration
- IP definition of chiplets
- Signaling interface cross chiplets
- Network topology for data movement
- Design solutions for power delivery
- Thermal management
- Testing in a heterogeneous system
- High-level synthesis for the chiplet system
- Architectural innovations
- Ecosystems of IPs and EDA tools
Proposed Format: The format of the workshop will consist of multiple invited presentations from industry, academia, and government funding agencies. We will also organize a panel for discussions.
Intended Audience: Industry and academic researchers, funding agencies, IP providers, EDA tool vendors, foundry
Workshop Schedule (TBD)
| Time | Activity |
| 9:00am – 9:30am | Introduction and opening remarks |
| 9:30am – 10am | “Wafer Level Si-Core Substrates”, Steven Verhaverbeke, AMAT |
| 10am -10:30am | “Toward a Modular Chiplet Ecosystem for HPC and AI”, John Shalf, LBNL |
| 10:30am – 11am | Coffee Break |
| 11am – 11:30am | “Advanced Packaging Driven Co-Optimization of High Performance Architectures”, Chandra Nair, Etched AI |
| 11:30am – 12:00pm | “Disaggregation is the Only Way Forward”, Tanay Karnik, Intel |
| 12pm – 12.30pm | Morning Panel Discussion: Joint with all invited speakers |
| 12:30pm – 2pm | Lunch |
| 2:00pm – 2:30pm | “The Lord of the Rings: Multiphysics Challenges and Solutions for Co-Packaged Optics in 3DHI”, Lang Lin, Ansys |
| 2:30pm – 3:00pm | “Optical Links for the Next Generation of Scalable AI/ML Architectures”, Shahab Ardalan, OCP |
| 3:00pm – 3:30pm | Coffee Break |
| 3:30pm – 4:00pm | “An Introduction to IEEE Std. P3537/3DBlox”, Sandeep Goel, TSMC |
| 4:00pm – 4:30pm | “Security Advantages and Challenges for Heterogeneous Integration”, Ankur Srivastava, University of Maryland |
| 4:30pm – 5:00pm | Afternoon Panel Discussion: Joint with all invited speakers |
Related Links
Registration to the #62DAC! https://www.dac.com/Attend/Registration