Workshop on Chiplet-based Heterogeneous Integration and CO-design
Contemporary microelectronic design is facing tremendous challenges in memory bandwidth, processing speed and power consumption.
Although recent advances in monolithic design, such as near-memory and in-memory computing, help relieve some issues, the scaling trend is still lagging behind the ever-increasing demand of AI, HPC and other applications.
In this context, technological innovations beyond a monolithic chip, such as 2.5D and 3D packaging at the macro and micro levels, are critical to enabling heterogeneous integration with various types of chiplets and bringing significant performance and cost benefits for future systems. Such a paradigm shift further drives new innovations on chiplet IPs, heterogeneous architectures and system mapping.
Workshop scope
This workshop is designed to be a forum that is highly interactive, timely and informative, on the related topics:
Proposed Format
The format of the workshop will consist of multiple invited presentations from industry, academia, and government funding agencies. We will also organize panels for discussions.
Intended Audience
Industry and academic researchers, funding agencies, IP providers, EDA tool vendors, foundries, and practitioners working on chiplet-based heterogeneous systems.
Workshop program
| Time | Activity |
|---|---|
| 9:00 am – 9:15 am |
Opening |
| Section 1: Advanced Packaging and Multi-Physics Analysis (morning) | |
| 9:15 am – 9:45 am |
Ravi Mahajan, Intel: Advanced Packaging Architectures for Heterogeneous Integration |
| 9:45 am – 10:15 am |
Tiwei Wei, UCLA: Fabrication and Materials Innovations for Thermal and Stress Reliability in Semiconductor Packaging |
| 10:15 am – 10:45 am |
Akhilesh Kumar, Synopsys: Multiphysics Sign-off in the Agentic Era: Challenges and Opportunities for 3DHI |
| 10:45 am – 11:15 am |
Zheng Zhang, UCSB: Physics-constrained Operator Learning for Thermal Modeling and Optimization in 3D-IC Design |
| 11:15 am – 11:45 am |
Morning Panel Discussion: Joint with all invited speakers |
| 11:45 am – 1:30 pm |
Lunch Break |
| Section 2: Chiplet-based Design and Integration (afternoon) | |
| 1:30 pm – 2:00 pm |
Vinayak Honkote, Intel: Designing Heterogeneous SoCs with 3D Chiplets: From Passive-Base Integration to Hybrid-Bonded Fabrics |
| 2:00 pm – 2:30 pm |
Zhengya Zhang, Univ. of Michigan: Chiplet-Based Design: From Academic Prototypes to Scalable Multi-Chip Packages |
| 2:30 pm – 3:00 pm |
Sandeep Kumar Goel, TSMC: Bridging the Chiplet Gap: How IEEE Std. P3537 Streamlines 2.5D/3D Advanced Packaging |
| 3:00 pm – 3:30 pm |
Cho Moon, Precision Innovations: Open-source infrastructure for 3D IC design |
| 3:30 pm – 4:00 pm |
Anshuman Chandra, Siemens: 3D IC Interconnects: Defects, Test and Repair |
| 4:00 pm – 4:30 pm |
Afternoon Panel Discussion: Joint with all invited speakers |