Workshop on Chiplet-based Heterogeneous Integration and CO-design
Contemporary microelectronic design is facing tremendous challenges in memory bandwidth, processing speed and power consumption.
Although recent advances in monolithic design, such as near-memory and in-memory computing, help relieve some issues, the scaling trend is still lagging behind the ever-increasing demand of AI, HPC and other applications.
In this context, technological innovations beyond a monolithic chip, such as 2.5D and 3D packaging at the macro and micro levels, are critical to enabling heterogeneous integration with various types of chiplets and bringing significant performance and cost benefits for future systems. Such a paradigm shift further drives new innovations on chiplet IPs, heterogeneous architectures and system mapping.
Workshop scope
This workshop is designed to be a forum that is highly interactive, timely and informative, on the related topics:
Proposed Format
The format of the workshop will consist of multiple invited presentations from industry, academia, and government funding agencies. We will also organize panels for discussions.
Intended Audience
Industry and academic researchers, funding agencies, IP providers, EDA tool vendors, foundries, and practitioners working on chiplet-based heterogeneous systems.
Workshop program
| Time | Activity |
|---|---|
| 9:00 am – 9:15 am |
Introduction |
| Section 1: Advanced Packaging and Multi-Physics Analysis (morning) | |
| 9:15 am – 11:30 am |
|
| 11:30 am – 12:00 pm |
Morning Panel Discussion: Joint with all invited speakers |
| 12:00 pm – 1:30 pm |
Lunch |
| Section 2: Chiplet-based Design and Integration (afternoon) | |
| 1:30 pm – 4:30 pm |
|
| 4:30 pm – 5:00 pm |
Afternoon Panel Discussion: Joint with all invited speakers |