oagTimerSdcData.h

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00001 /* (c) Copyright 2004-2005, Cadence Design Systems, Inc.  All rights reserved. 
00002 
00003 This file is part of the OA Gear distribution.  See the COPYING file in
00004 the top level OA Gear directory for copyright and licensing information. */
00005 
00006 /*
00007 Author: Zhong Xiu <zxiu@andrew.cmu.edu>
00008 
00009 ChangeLog:
00010 2004-09-15: ChangeLog started
00011 */
00012 
00013 #if !defined(oagTimerSdcData_P)
00014 #define oagTimerSdcData_P
00015 
00016 #include <map>
00017 #include <set>
00018 #include <vector>
00019 #include <string.h>
00020 #include <string>
00021 #include "oaDesignDB.h"
00022 
00023 namespace oagTimer {
00024 
00028 struct stringIsLess {
00029   bool operator()(const std::string a, const std::string b)  const {
00030     return a.compare(b) < 0;
00031   }
00032 };
00033 
00034 
00036 typedef std::map<std::string, double, stringIsLess> delayMap;
00037 
00039 typedef std::map<std::string, std::string, stringIsLess> cellMap;
00040 
00041 /* afshin-begin */
00042 
00043 
00044 struct clock {
00045     double period;
00046     std::string name;
00047 };
00048 
00049 struct propagatedClock {
00050     clock *clk;
00051     int m;
00052     bool phase;
00053 };
00054 
00055 typedef std::map<std::string, int, stringIsLess> termIntMap;
00056 /* afshin-end */
00057 
00058 
00060 class SdcData {
00061   public:
00063     SdcData() {
00064       allInputs = allOutputs = false;
00065       allLoads = allCells = false;
00066       clockPeriod = allInputsDelay = allOutputsDelay = 0.0;
00067       propagatedClocks.clear();
00068       allFanoutLoads = 0.0;
00069       currentPort = "";
00070       allDrivingCells = "";
00071     }
00073     ~SdcData() {
00074       clear();
00075     }
00076 
00078     void clear();
00079 
00080     int pushAllInputs();
00081     int pushAllOutputs();
00082     int pushPorts(const char *s);
00083     int pushClockPorts(const char *s);
00084     int pushMultiCyclePath(std::string pathType, int m);
00085     int pushClock(double c, const char *s);
00086     int pushInputDelay(double d);
00087     int pushInputDelay(double d, std::string s);
00088     int pushOutputDelay(double d);
00089     int pushOutputDelay(double d, std::string s);
00090 
00091     int pushAllCells();
00092     int pushAllLoads();
00093     int pushDrivingCell(const char *s);
00094     int pushFanoutLoad(double d);
00095 
00097     double clockPeriod;
00099     bool allInputs;
00101     double allInputsDelay;
00102     int allInputsClock;
00104     bool allOutputs;
00106     double allOutputsDelay;
00107     int allOutputsClock;
00108 
00110     bool allLoads;
00112     double allFanoutLoads;
00114     bool allCells;
00116     std::string allDrivingCells;
00117 
00118 /* afshin-begin */
00119     termIntMap termClock;
00120     termIntMap isClock;
00121     std::vector<propagatedClock*> propagatedClocks;
00122     termIntMap multiCycleConstraints;
00123     std::vector<std::string> ports;
00124     //clockPorts.reserve(numClockTP);
00125 /* afshin-end */
00126 
00128     delayMap extInputDelays;
00130     delayMap extOutputDelays;
00132     delayMap fanoutLoads;
00134     cellMap drivingCells;
00136     std::string currentPort;
00137 };
00138 
00139 }
00140 
00141 #endif

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