{"id":84,"date":"2019-10-01T04:01:35","date_gmt":"2019-10-01T04:01:35","guid":{"rendered":"http:\/\/nanocad.ee.ucla.edu\/?page_id=84"},"modified":"2024-06-18T00:15:16","modified_gmt":"2024-06-18T00:15:16","slug":"publications","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=84","title":{"rendered":"Publications"},"content":{"rendered":"\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=84\/#Journals\" >Journals<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=84\/#Conferences\" >Conferences<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=84\/#Invited_Papers\" >Invited Papers<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=84\/#Books_and_Book_Chapters\" >Books and Book Chapters<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=84\/#Invited_Talks_and_Tutorials\" >Invited Talks and Tutorials<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=84\/#Patents\" >Patents<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=84\/#Workshops_No_Published_Proceedings\" >Workshops (No Published Proceedings)<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Journals\"><\/span> Journals<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><ul class=\"papercite_bibliography\">          [J88]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j88.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/TCAD.2026.3657674' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        Z. Chen and P. Gupta, &#8220;YAP+: pad-layout-aware yield modeling and simulation for hybrid bonding,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2026.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_85\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_85_block\"><pre><code class=\"tex bibtex\">@article{J88,\nauthor = {Chen, Zhichao and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/TCAD.2026.3657674},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ntitle = {{YAP+}: Pad-Layout-Aware Yield Modeling and Simulation for Hybrid Bonding},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [J89]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j89.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Graening, P. Gupta, A. B. Kahng, B. Pramanik, and Z. Wang, &#8220;ChipletPart: cost-aware partitioning for 2.5D systems,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2026.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_86\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_86_block\"><pre><code class=\"tex bibtex\">@article{J89,\nauthor = {Graening, Alexander and Gupta, Puneet and Kahng, Andrew B. and Pramanik, Bodhi and Wang, Zhiang},\ndoi = {},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\ntitle = {{ChipletPart:} Cost-Aware Partitioning for {2.5D} Systems},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [J82]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j82.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1016\/j.msea.2025.148173' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        Y. Li, T. Li, L. Tang, S. Ma, Q. Wu, P. Gupta, and M. Bauchy, &#8220;ConvFeatNet ensemble: integrating microstructure and pre-defined features for enhanced prediction of porous material properties,&#8221; <span style=\"font-style: italic\">Materials Science and Engineering: A<\/span>, vol. 931, p. 148173, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_79\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_79_block\"><pre><code class=\"tex bibtex\">@article{J82,\nauthor = {Li ,Yuhai and Li, Tianmu and Tang, Longwen and Ma, Shiyu and Wu, Qinglin and Gupta, Puneet and Bauchy, Mathieu},\ndoi = {https:\/\/doi.org\/10.1016\/j.msea.2025.148173},\nissn = {0921-5093},\njournal = {{Materials Science and Engineering: A}},\npages = {148173},\ntitle = {{ConvFeatNet} ensemble: Integrating microstructure and pre-defined features for enhanced prediction of porous material properties},\nurl = {https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0921509325003971},\nvolume = {931},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [J83]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j83.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/JSSC.2025.3554554' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        J. Yang, T. Li, W. Romaszkan, P. Gupta, and S. Pamarti, &#8220;A 65-nm digital stochastic compute-in-memory CNN processor with 8-bit precision,&#8221; <span style=\"font-style: italic\">IEEE Journal of Solid State Circuits<\/span>, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_80\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_80_block\"><pre><code class=\"tex bibtex\">@article{J83,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\ndoi = {https:\/\/doi.org\/10.1109\/JSSC.2025.3554554},\njournal = {{IEEE Journal of Solid State Circuits}},\ntitle = {A 65-nm Digital Stochastic Compute-in-Memory {CNN} Processor With 8-bit Precision},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [J84]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j84.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/JETCAS.2025.3595909' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        G. Karfakis, M. Bouzidi, Y. Im, A. Graening, S. K. Sitaraman, and P. Gupta, &#8220;Optimizing thermal performance in 2.5d systems using embedded isolators,&#8221; <span style=\"font-style: italic\">IEEE Journal on Emerging and Selected Topics in Circuits and Systems<\/span>, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_81\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_81_block\"><pre><code class=\"tex bibtex\">@article{J84,\nauthor = {Karfakis, George and Bouzidi, Myriam and Im, Yunhyeok and Graening, Alexander and Sitaraman, Suresh K. and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/JETCAS.2025.3595909},\njournal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},\ntitle = {Optimizing Thermal Performance in 2.5D Systems Using Embedded Isolators},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [J85]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j85.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/TCAD.2025.3597570' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        A. Graening, J. Talukdar, S. Pal, K. Chakrabarty, and P. Gupta, &#8220;CATCH: a cost analysis tool for co-optimization of chiplet-based heterogeneous systems,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_82\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_82_block\"><pre><code class=\"tex bibtex\">@article{J85,\nauthor = {Graening, Alexander and Talukdar, Jonti and Pal, Saptadeep and Chakrabarty, Krishnendu and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/TCAD.2025.3597570},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ntitle = {{CATCH}: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [J86]                            H. Yang, N. Peserico, S. Li, X. Ma, R. L. Schwartz, M. Hosseini, A. Babakhani, C. W. Wong, P. Gupta, and V. J. Sorger, &#8220;Near-energy-free photonic fourier transformation for convolution operation acceleration,&#8221; <span style=\"font-style: italic\">Advanced Photonics<\/span>, vol. 7, iss. 5, p. 056007\u2013056007, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_83\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_83_block\"><pre><code class=\"tex bibtex\">@article{J86,\nauthor = {Yang, Hangbo and Peserico, Nicola and Li, Shurui and Ma, Xiaoxuan and Schwartz, Russell LT and Hosseini, Mostafa and Babakhani, Aydin and Wong, Chee Wei and Gupta, Puneet and Sorger, Volker J},\njournal = {{Advanced Photonics}},\nnumber = {5},\npages = {056007--056007},\npublisher = {Society of Photo-Optical Instrumentation Engineers},\ntitle = {Near-energy-free photonic Fourier transformation for convolution operation acceleration},\nvolume = {7},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [J87]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j87.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1117\/1.JMM.24.4.041205' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        S. Jain, P. Woltgens, and P. Gupta, &#8220;Design enablement of low-cost stitching in high na euv patterning,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, vol. 24, iss. 5, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_84\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_84_block\"><pre><code class=\"tex bibtex\">@article{J87,\nauthor = {Jain, Sagar and Woltgens, Pieter and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1117\/1.JMM.24.4.041205},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nnumber = {5},\ntitle = {Design enablement of low-cost stitching in high NA EUV patterning},\nvolume = {24},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [J78]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j78.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam and P. Gupta, &#8220;Achieving dram-like pcm by trading off capacity for latency,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computers<\/span>, 2024.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_74\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_74_block\"><pre><code class=\"tex bibtex\">@article{J78,\nauthor = {Irina Alam and Puneet Gupta},\njournal = {{IEEE Transactions on Computers}},\ntitle = {Achieving DRAM-like PCM By Trading Off Capacity For Latency},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [J79]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j79.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    E. Glukhov, T. Li, V. Gupta, and P. Gupta, &#8220;Learned approximate computing: algorithm hardware co-optimization,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2024.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_75\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_75_block\"><pre><code class=\"tex bibtex\">@article{J79,\nauthor = {Egor Glukhov and Tianmu Li and Vaibhav Gupta and Puneet Gupta},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ntitle = {Learned Approximate Computing: Algorithm Hardware Co-optimization},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [J80]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j80.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1038\/s44287-024-00078-x' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        S. Pal, A. Mallik, and P. Gupta, &#8220;System technology co-optimization for advanced integration,&#8221; <span style=\"font-style: italic\">Nature Reviews Electrical Engineering<\/span>, 2024.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_77\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_77_block\"><pre><code class=\"tex bibtex\">@article{J80,\nauthor = {Pal, S. and Mallik, A. and Gupta, P},\ndoi = {10.1038\/s44287-024-00078-x},\njournal = {{Nature Reviews Electrical Engineering}},\ntitle = {System technology co-optimization for advanced integration},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [J81]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j81.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1109\/TVLSI.2024.3508673' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        Z. Chen, H. Hassan  A., R. Ramadhan, Y. Li, C. K. Yang, S. Pamarti, and P. Gupta, &#8220;A comparative analysis of low temperature and room temperature circuit operation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration (TVLSI) Systems<\/span>, 2024.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_78\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_78_block\"><pre><code class=\"tex bibtex\">@article{J81,\nauthor = {Chen, Z. and Hassan, A., H. and Ramadhan, R. and Li, Y. and Yang, C. K. and Pamarti, S. and Gupta, P.},\ndoi = {10.1109\/TVLSI.2024.3508673},\njournal = {{{IEEE Transactions on Very Large Scale Integration (TVLSI) Systems}}},\ntitle = {A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [J74]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j74.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Li, W. Romaszkan, S. Pamarti, and P. Gupta, &#8220;REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_71\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_71_block\"><pre><code class=\"tex bibtex\">@article{J74,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nmonth = {June},\npublisher = {{IEEE}},\ntitle = {{REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [J73]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j73.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1109\/JXCDC.2023.3258431' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        V. K. Jacob, J. Yang, H. He, P. Gupta, K. Wang, and S. Pamarti, &#8220;A Nonvolatile Compute-In-Memory Macro Using Voltage-Controlled MRAM and In-Situ Magnetic-to-Digital Converter,&#8221; <span style=\"font-style: italic\">IEEE Journal on Exploratory Solid-State Computational Devices and Circuits<\/span>, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_70\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_70_block\"><pre><code class=\"tex bibtex\">@article{J73,\nauthor = {Jacob, Vinod Kurian and Yang, Jiyue and He, Haoran and Gupta, Puneet and Wang, Kang and Pamarti, Sudhakar},\ndoi = {10.1109\/JXCDC.2023.3258431},\njournal = {{IEEE Journal on Exploratory Solid-State Computational Devices and Circuits}},\nmonth = {March},\npaperurl = {https:\/\/ieeexplore.ieee.org\/document\/10075423},\npublisher = {{IEEE}},\ntitle = {{A Nonvolatile Compute-In-Memory Macro Using Voltage-Controlled MRAM and In-Situ Magnetic-to-Digital Converter}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [J76]                    <a href='http:\/\/dx.doi.org\/10.1109\/TED.2022.3228831' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        A. Lee, I. Alam, J. Yang, D. Wu, S. Pamarti, P. Gupta, and K. L. Wang, &#8220;Low-energy shared-current write schemes for voltage-controlled spin-orbit-torque memory,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electron Devices<\/span>, vol. 70, iss. 2, pp. 478-484, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_72\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_72_block\"><pre><code class=\"tex bibtex\">@article{J76,\nauthor = {Lee, Albert and Alam, Irina and Yang, Jiyue and Wu, Di and Pamarti, Sudhakar and Gupta, Puneet and Wang, Kang L.},\ndoi = {10.1109\/TED.2022.3228831},\njournal = {{IEEE Transactions on Electron Devices}},\nnumber = {2},\npages = {478-484},\ntitle = {Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory},\nvolume = {70},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [J77]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j77.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1145\/3635867' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        N. Ardalani, S. Pal, and P. Gupta, &#8220;Deepflow: a cross-stack pathfinding framework for distributed ai systems,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_73\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_73_block\"><pre><code class=\"tex bibtex\">@article{J77,\nauthor = {Newsha Ardalani and Saptadeep Pal and Puneet Gupta},\ndoi = {10.1145\/3635867},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\ntitle = {DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [J71]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j71.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Z. Hu, S. Li, R. Schwartz, M. Solyanik-Gorgone, M. Miscuglio, P. Gupta, and V. Sorger, &#8220;High-Throughput Multichannel Parallelized Diffraction Convolutional Neural Network Accelerator,&#8221; <span style=\"font-style: italic\">Laser &#038; Photonics Reviews<\/span>, 2022.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_68\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_68_block\"><pre><code class=\"tex bibtex\">@article{J71,\nauthor = {Hu, Zibo and Li, Shurui and Schwartz, Russel and Solyanik-Gorgone, Maria and Miscuglio, Mario and Gupta, Puneet and Sorger, Volker},\njournal = {{Laser \\& Photonics Reviews}},\nmonth = {October},\npublisher = {{Wiley}},\ntitle = {{High-Throughput Multichannel Parallelized Diffraction Convolutional Neural Network Accelerator}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [J72]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j72.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, T. Li, and P. Gupta, &#8220;SASCHA &#8211; Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,&#8221; , p. 12, 2022.  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_69\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_69_block\"><pre><code class=\"tex bibtex\">@article{J72,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {October},\nnote = {Best paper nomination},\npages = {12},\ntitle = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [J70]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j70.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, T. Li, R. Garg, J. Yang, S. Pamarti, and P. Gupta, &#8221; A 4.4-75 TOPS\/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator,&#8221; <span style=\"font-style: italic\">IEEE Solid State Circuits Letters<\/span>, 2022.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_67\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_67_block\"><pre><code class=\"tex bibtex\">@article{J70,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Garg, Rahul and Yang, Jiyue and Pamarti, Sudhakar and Gupta, Puneet},\njournal = {{IEEE Solid State Circuits Letters}},\nkeywords = {mledge},\nmonth = {August},\npublisher = {{IEEE}},\ntitle = {{ A 4.4-75 TOPS\/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [J69]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j69.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam, T. Li, S. Brock, and P. Gupta, &#8220;DRDebug: Automated Design Rule Debugging,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2022.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_65\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_65_block\"><pre><code class=\"tex bibtex\">@article{J69,\nauthor = {Alam, Irina and Li, Tianmu and Brock, Sean and Gupta, Puneet},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\npublisher = {{IEEE}},\ntitle = {{DRDebug: Automated Design Rule Debugging}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [J65]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j65.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/ieeexplore.ieee.org\/document\/8902181' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        E. Chu, Y. Luo, and P. Gupta, &#8220;Design Impacts of Back-End-of-Line Line Edge Roughness,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_61\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_61_block\"><pre><code class=\"tex bibtex\">@article{J65,\nauthor = {Chu, Eugene and Luo, Yandong and Gupta, Puneet},\ndoi = {https:\/\/ieeexplore.ieee.org\/document\/8902181},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nmonth = {February},\npublisher = {{IEEE}},\ntitle = {{Design Impacts of Back-End-of-Line Line Edge Roughness}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [J64]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j64.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/TCAD.2019.2957359' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        W. Wang, Y. Wu, and P. Gupta, &#8220;Reverse Engineering for 2.5D Split Manufactured ICs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_60\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_60_block\"><pre><code class=\"tex bibtex\">@article{J64,\nauthor = {Wang, Wei-Che and Wu, Yizhang and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/TCAD.2019.2957359},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\npublisher = {{IEEE}},\ntitle = {{Reverse Engineering for 2.5D Split Manufactured ICs}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [J66]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j66.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/ieeexplore.ieee.org\/document\/8998304' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        S. Pal, D. Petrisko, R. Kumar, and P. Gupta, &#8220;Design Space Exploration for Chiplet Assembly Based Processors,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_62\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_62_block\"><pre><code class=\"tex bibtex\">@article{J66,\nauthor = {Pal, Saptadeep and Petrisko, Daniel and Kumar, Rakesh and Gupta, Puneet},\ndoi = {https:\/\/ieeexplore.ieee.org\/document\/8998304},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {{2.5-D integration, chiplet assembly, micro-architectural design space exploration (DSE), multichiplet optimization, wsi}},\npublisher = {{IEEE}},\ntitle = {{Design Space Exploration for Chiplet Assembly Based Processors}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [J67]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j67.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Miscuglio, Z. Hu, S. Li, J. George, R. Capanna, P. Bardet, P. Gupta, and V. Sorger, &#8220;Massively parallel amplitude-only Fourier neural network,&#8221; <span style=\"font-style: italic\">Optica<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_63\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_63_block\"><pre><code class=\"tex bibtex\">@article{J67,\nauthor = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and George, Jonathan and Capanna, Roberto and Bardet, Philippe and Gupta, Puneet and Sorger, Volker},\njournal = {{Optica}},\npublisher = {{OSA}},\ntitle = {{Massively parallel amplitude-only Fourier neural network}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [J63]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j63.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, T. Li, and P. Gupta, &#8220;3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning,&#8221; <span style=\"font-style: italic\">ACM Transactions on Embedded Computing Systems (TECS)<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_59\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_59_block\"><pre><code class=\"tex bibtex\">@article{J63,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\njournal = {{ACM Transactions on Embedded Computing Systems (TECS)}},\nkeywords = {mledge, 3pxnet},\nmonth = {November},\npublisher = {ACM},\ntitle = {{3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [J62]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j62.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Schoeny, F. Sala, M. Gottscho, I. Alam, P. Gupta, and L. Dolecek, &#8220;Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Information Theory<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_58\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_58_block\"><pre><code class=\"tex bibtex\">@article{J62,\nauthor = {Schoeny, Clayton and Sala, Frederic and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},\njournal = {{IEEE Transactions on Information Theory}},\nkeywords = {memres},\nmonth = {October},\ntitle = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [J61]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j61.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal, E. Ebrahimi, A. Zulfiqar, Y. Fu, V. Zhang, S. Migacz, D. Nellans, and P. Gupta, &#8220;Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training,&#8221; <span style=\"font-style: italic\">IEEE Micro<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_57\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_57_block\"><pre><code class=\"tex bibtex\">@article{J61,\nauthor = {Pal, Saptadeep and Ebrahimi, Eiman and Zulfiqar, Arslan and Fu, Yaosheng and Zhang, Victor and Migacz, Szymon and Nellans, David and Gupta, Puneet},\njournal = {{{IEEE Micro}}},\nmonth = {September},\npublisher = {IEEE},\ntitle = {{Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [J60]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j60.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang, Y. Yona, Y. Wu, S. Diggavi, and P. Gupta, &#8220;SLATE: A Secure Lightweight Entity Authentication Hardware Primitive,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Information Forensics and Security<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_56\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_56_block\"><pre><code class=\"tex bibtex\">@article{J60,\nauthor = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Diggavi, Suhas and Gupta, Puneet},\njournal = {{{IEEE Transactions on Information Forensics and Security}}},\nmonth = {May},\npublisher = {IEEE},\ntitle = {{SLATE: A Secure Lightweight Entity Authentication Hardware Primitive}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [J68]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j68.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta and S. S. Iyer, &#8220;Goodbye Motherboard, Hello Silicon Interconnect Fabric,&#8221; <span style=\"font-style: italic\">IEEE Spectrum<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_64\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_64_block\"><pre><code class=\"tex bibtex\">@article{J68,\nauthor = {Gupta, Puneet and Iyer, S.S.},\njournal = {{IEEE Spectrum}},\npublisher = {{IEEE}},\ntitle = {{Goodbye Motherboard, Hello Silicon Interconnect Fabric}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [J57]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j57.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang, C. Zhao, and P. Gupta, &#8220;Assessing Layout Density Benefits of Vertical Channel Devices,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2018.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_52\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_52_block\"><pre><code class=\"tex bibtex\">@article{J57,\nauthor = {Wang, Wei-Che and Zhao, Charles and Gupta, Puneet},\nissue = {},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nmonth = {},\ntitle = {{Assessing Layout Density Benefits of Vertical Channel Devices}},\nvolume = {},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [J58]                            H. Lee, A. Lee, S. Wang, F. Ebrahimi, P. Gupta, P. K. Amiri, and K. L. Wang, &#8220;Analysis and Compact Modeling of Magnetic Tunner Junctions Using Voltage-Controlled Magnetic Anisotropy,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Magnetics<\/span>, 2018.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_53\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_53_block\"><pre><code class=\"tex bibtex\">@article{J58,\nauthor = {H. Lee and A. Lee and S. Wang and F. Ebrahimi and P. Gupta and P.K. Amiri and K.L. Wang},\njournal = {{IEEE Transactions on Magnetics}},\ntitle = {{Analysis and Compact Modeling of Magnetic Tunner Junctions Using Voltage-Controlled Magnetic Anisotropy}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [J59]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j59.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Wang, H. Lee, C. Grezes, K. P. Amiri, K. L. Wang, and P. Gupta, &#8220;Adaptive MRAM Write and Read with MTJ Variation Monitor,&#8221; <span style=\"font-style: italic\">Transactions on Emerging Topics in Computing<\/span>, 2018.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_54\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_54_block\"><pre><code class=\"tex bibtex\">@article{J59,\nauthor = {Wang, Shaodi and Lee, Hochul and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Gupta, Puneet},\njournal = {{Transactions on Emerging Topics in Computing}},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J59_paper.pdf},\ntitle = {{Adaptive MRAM Write and Read with MTJ Variation Monitor}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [J56]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j56.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang, Y. Yona, S. Diggavi, and P. Gupta, &#8220;Design and Analysis of Stability-Guaranteed PUFs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Information Forensics and Security (TIFS)<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_51\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_51_block\"><pre><code class=\"tex bibtex\">@article{J56,\nauthor = {Wang, Wei-Che and Yona, Yair and Diggavi, Suhas and Gupta, Puneet},\njournal = {{IEEE Transactions on Information Forensics and Security (TIFS)}},\nmonth = {November},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J56_paper.pdf},\ntitle = {{Design and Analysis of Stability-Guaranteed PUFs}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [J54]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j54.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Gottscho, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Low-Cost Memory Fault Tolerance for IoT Devices,&#8221; <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_49\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_49_block\"><pre><code class=\"tex bibtex\">@article{J54,\nauthor = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\njournal = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},\nkeywords = {memres},\nmonth = {October},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J54_paper.pdf},\ntitle = {{Low-Cost Memory Fault Tolerance for IoT Devices}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [J53]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j53.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Lai and P. Gupta, &#8220;System-level Dynamic Variation Margining in Presence of Monitoring and Actuation,&#8221; <span style=\"font-style: italic\">IEEE Embedded System Letters<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_48\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_48_block\"><pre><code class=\"tex bibtex\">@article{J53,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\njournal = {{IEEE Embedded System Letters}},\nkeywords = {Monitoring, Temperature measurement, Temperature sensors, Actuators, Power system dynamics, Aging, Clocks},\nmonth = {June},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J53_paper.pdf},\ntitle = {{System-level Dynamic Variation Margining in Presence of Monitoring and Actuation}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [J51]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j51.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    H. Lee, A. Lee, S. Wang, F. Ebrahimi, P. Gupta, K. P. Amiri, and K. L. Wang, &#8220;A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_46\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_46_block\"><pre><code class=\"tex bibtex\">@article{J51,\nauthor = {Lee, Hochul and Lee, Albert and Wang, Shaodi and Ebrahimi, Farbod and Gupta, Puneet and Amiri, P. Khalili and Wang, Kang L.},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {},\nmonth = {March},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J51_paper.pdf},\ntitle = {{A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [J49]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j49.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Wang, A. Pan, C. O. Chui, and P. Gupta, &#8220;Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electronic Devices<\/span>, vol. 64, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_43\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_43_block\"><pre><code class=\"tex bibtex\">@article{J49,\nauthor = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},\nissue = {1},\njournal = {{IEEE Transactions on Electronic Devices}},\nkeywords = {Negative differential resistance, Magnetic tunnel junction, Magnetic random access memory, MRAM, read, write termination},\nmonth = {1},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J49_paper.pdf},\ntitle = {{Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operation}},\nvolume = {64},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [J50]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j50.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Grezes, H. Lee, A. Lee, S. Wang, F. Ebrahimi, X. Li, K. Wong, Q. Hu, P. Gupta, K. P. Amiri, and K. L. Wang, &#8220;Write Error Rate and Read Disturbance in Electric-Field-Controlled MRAM,&#8221; <span style=\"font-style: italic\">IEEE Magnetic Letters<\/span>, vol. 8, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_45\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_45_block\"><pre><code class=\"tex bibtex\">@article{J50,\nauthor = {Grezes, Cecile and Lee, Hochul and Lee, Albert and Wang, Shaodi and Ebrahimi, Farbod and Li, Xiang and Wong, Kin and Hu, Qi and Gupta, Puneet and Amiri, P. Khalili and Wang, Kang L.},\njournal = {{IEEE Magnetic Letters}},\nkeywords = {},\nmonth = {},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J50_paper.pdf},\ntitle = {{Write Error Rate and Read Disturbance in Electric-Field-Controlled MRAM}},\nvolume = {8},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [J52]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j52.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Badr and P. Gupta, &#8220;Technology path-finding framework for directed-self assembly for via layers,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_47\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_47_block\"><pre><code class=\"tex bibtex\">@article{J52,\nauthor = {Badr, Yasmine and Gupta, Puneet},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J52_paper.pdf},\ntitle = {Technology path-finding framework for directed-self assembly for via layers},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [J55]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j55.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Wang, A. Pan, C. Grezes, P. Amiri, C. O. Chui, and P. Gupta, &#8220;Leveraging NMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electronic Devices<\/span>, vol. PP, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_50\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_50_block\"><pre><code class=\"tex bibtex\">@article{J55,\nauthor = {Wang, Shaodi and Pan, Andrew and Grezes, Cecile and Amiri, Pedram and Chui, Chi On and Gupta, Puneet},\njournal = {{IEEE Transactions on Electronic Devices}},\nkeywords = {Negative differential resistance, Magnetic tunnel junction, Magnetic random access memory, MRAM, read, write termination},\nmonth = {8},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J55_paper.pdf},\ntitle = {{Leveraging NMOS Negative Differential Resistance\nfor Low Power, High Reliability Magnetic Memory}},\nvolume = {PP},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [J47]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j47.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Wang, H. Hu, H. Zheng, and P. Gupta, &#8220;MEMRES: A Fast Memory System Reliability Simulator,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Reliability<\/span>, vol. 65, pp. 1783-1797, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_41\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_41_block\"><pre><code class=\"tex bibtex\">@article{J47,\nauthor = { Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},\nissue = {4},\njournal = {{IEEE Transactions on Reliability}},\nkeywords = {Memory fault, memory reliability, simulator, reliability management, memory page retirement, sparing, memory mirroring, STT-RAM, MRAM, write error, retention error},\nmonth = {October},\npages = {1783-1797},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J47_paper.pdf},\ntitle = {{MEMRES}: {A} {F}ast {M}emory {S}ystem {R}eliability {S}imulator},\nvolume = {65},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [J48]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j48.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Badr, A. Torres, and P. Gupta, &#8220;Mask Assignment and Dsa Grouping for DSA-MP Hybrid Lithography for sub-7nm Contact\/Via Holes,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_42\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_42_block\"><pre><code class=\"tex bibtex\">@article{J48,\nauthor = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},\ncategory = {J48},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J48_paper.pdf},\ntitle = {{M}ask {A}ssignment and {D}SA {G}rouping for {DSA-MP} {H}ybrid {L}ithography for sub-7nm {C}ontact\/{V}ia {H}oles},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [J46]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j46.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Gottscho, M. Shoaib, S. Govindan, B. Sharma, D. Wang, and P. Gupta, &#8220;Measuring the Impact of Memory Errors on Application Performance,&#8221; <span style=\"font-style: italic\">IEEE Computer Architecture Letters (CAL)<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_40\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_40_block\"><pre><code class=\"tex bibtex\">@article{J46,\nauthor = {Gottscho, Mark and Shoaib, Mohammed and Govindan, Sriram and Sharma, Bikash and Wang, Di and Gupta, Puneet},\nissue = {},\njournal = {{IEEE Computer Architecture Letters (CAL)}},\nkeywords = {memres},\nmonth = {August},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J46_paper.pdf},\ntitle = {{Measuring the Impact of Memory Errors on Application Performance}},\nvolume = {},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [J42]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j42.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Wang, H. Lee, F. Ebrahimi, K. P. Amiri, K. L. Wang, and P. Gupta, &#8220;Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory,&#8221; <span style=\"font-style: italic\">IEEE Journal on Emerging and Selected Topics in Circuits and Systems<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_36\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_36_block\"><pre><code class=\"tex bibtex\">@article{J42,\nauthor = {Wang, Shaodi and Lee, Hochul and Ebrahimi, Farbod and Amiri, P. Khalili and Wang, Kang L. and Gupta, Puneet},\njournal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},\nkeywords = {STT-RAM, MeRAM, MTJ, process variation, write error rate, MTJ Model},\nmonth = {June},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J42_paper.pdf},\ntitle = {{C}omparative {E}valuation of {S}pin-{T}ransfer-{T}orque and {M}agnetoelectric {R}andom {A}ccess {M}emory},\nvolume = {},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [J45]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j45.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Zhu, Y. Badr, S. Wang, S. Iyer, and P. Gupta, &#8220;Assessing Benefits of a Buried Interconnect Layer in Digital Designs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_39\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_39_block\"><pre><code class=\"tex bibtex\">@article{J45,\nauthor = {Zhu, Liheng and Badr, Yasmine and Wang, Shaodi and Iyer, Subramanian and Gupta, Puneet},\ncategory = {J45},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J45_paper.pdf},\ntitle = {Assessing {B}enefits of a {B}uried {I}nterconnect {L}ayer in {D}igital {D}esigns},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [J40]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j40.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    G. Leung, S. Wang, A. Pan, P. Gupta, and C. O. Chui, &#8220;An Evaluation Framework for Nanotransfer Printing Based Feature-Level Heterogeneous Integration in VLSI Circuits,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_34\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_34_block\"><pre><code class=\"tex bibtex\">@article{J40,\nauthor = {Leung, Greg and Wang, Shaodi and Pan, Andrew and Gupta, Puneet and Chui, Chi On},\nissue = {},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J40_paper.pdf},\ntitle = {{A}n {E}valuation {F}ramework for {N}anotransfer {P}rinting {B}ased {F}eature-{L}evel {H}eterogeneous {I}ntegration in {VLSI} {C}ircuits},\nvolume = {},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [J41]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j41.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang and P. Gupta, &#8220;Efficient Layout Generation and Design Evaluation of Vertical Channel Devices,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_35\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_35_block\"><pre><code class=\"tex bibtex\">@article{J41,\nauthor = {Wang, Wei-Che and Gupta, Puneet},\nissue = {},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J41_paper.pdf},\ntitle = {{Efficient Layout Generation and Design Evaluation of Vertical Channel Devices}},\nvolume = {},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [J43]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j43.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    H. Lee, C. Grezes, S. Wang, K. P. Amiri, P. Gupta, and K. L. Wang, &#8220;A Source Line Sensing (SLS) Scheme in Magnetoelectric Random Access Memory (MeRAM) for Reducing Read Disturbance and Improving Sensing Margin,&#8221; <span style=\"font-style: italic\">IEEE Magnetics Letters<\/span>, vol. 7, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_37\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_37_block\"><pre><code class=\"tex bibtex\">@article{J43,\nauthor = { Lee, Hochul and Grezes, Cecile and Wang, Shaodi and Amiri, P. Khalili and Gupta, Puneet and Wang, Kang L.},\njournal = {{IEEE Magnetics Letters}},\nkeywords = {MeRAM, MTJ, read disturbance, source line sensing, sensing scheme},\nmonth = {},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J43_paper.pdf},\ntitle = {A {S}ource {L}ine {S}ensing ({SLS}) {S}cheme in {M}agnetoelectric {R}andom {A}ccess {M}emory ({MeRAM}) for {R}educing {R}ead {D}isturbance and {I}mproving {S}ensing {M}argin},\nvolume = {7},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [J44]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j44.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, and A. B. Kahng, &#8220;Benchmarking of Mask Fracturing Heuristics,&#8221; in <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_38\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_38_block\"><pre><code class=\"tex bibtex\">@inproceedings{J44,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. },\nbooktitle = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ncategory = {J44},\nkeywords = {dats},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J44_paper.pdf},\ntitle = {Benchmarking of {M}ask {F}racturing {H}euristics},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [J39]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j39.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Gottscho, A. BanaiyanMofrad, N. Dutt, A. Nicolau, and P. Gupta, &#8220;DPCS: Dynamic Power\/Capacity Scaling for SRAM Caches in the Nanoscale Era,&#8221; <span style=\"font-style: italic\">ACM Transactions on Architecture and Code Optimization (TACO)<\/span>, vol. 12, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_32\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_32_block\"><pre><code class=\"tex bibtex\">@article{J39,\nauthor = {Gottscho, Mark and BanaiyanMofrad, Abbas and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},\nissue = {3},\njournal = {{ACM Transactions on Architecture and Code Optimization (TACO)}},\nmonth = {August},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J39_paper.pdf},\ntitle = {{DPCS}: {D}ynamic {P}ower\/{C}apacity {S}caling for {SRAM} {C}aches in the {N}anoscale {E}ra},\nvolume = {12},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [J38]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j38.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Wanner, L. Lai, A. Rahimi, M. Gottscho, P. Mercati, C. Huang, F. Sala, Y. Agarwal, L. Dolecek, N. Dutt, P. Gupta, R. Gupta, R. Jhala, R. Kumar, S. Lerner, M. Subhasish, A. Nicolau, T. S. Rosing, M. B. Srivastava, S. Swanson, D. Sylvester, and Y. Zhou, &#8220;NSF Expedition on Variability-Aware Software: Recent Results and Contributions,&#8221; <span style=\"font-style: italic\">De Gruyter Information Technology (it)<\/span>, vol. 57, pp. 181-198, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_31\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_31_block\"><pre><code class=\"tex bibtex\">@article{J38,\nauthor = {Wanner, Lucas and Lai, Liangzhen and Rahimi, Abbas and Gottscho, Mark and Mercati, Pietro and Huang, Chu-Hsiang and Sala, Frederic and Agarwal, Yuvraj and Dolecek, Lara and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh and Jhala, Ranjit and Kumar, Rakesh and Lerner, Sorin and Mitra Subhasish and Nicolau, Alexandru and Rosing, Tajana Simunic and Srivastava, Mani B. and Swanson, Steve and Sylvester, Dennis and Zhou, Yuanyuan},\nissue = {3},\njournal = {{De Gruyter Information Technology (it)}},\nmonth = {June},\npages = {181-198},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J38_paper.pdf},\ntitle = {{NSF} {E}xpedition on {V}ariability-{A}ware {S}oftware: {R}ecent {R}esults and {C}ontributions},\nvolume = {57},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [J33]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j33.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Gottscho, L. A. D. Bathen, N. Dutt, A. Nicolau, and P. Gupta, &#8220;ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computers<\/span>, vol. 64, p. 1483\u20131496, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_26\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_26_block\"><pre><code class=\"tex bibtex\">@article{J33,\nauthor = {Gottscho, Mark and Bathen, Luis A. D. and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},\nissue = {5},\njournal = {{IEEE Transactions on Computers}},\nkeywords = {DRAM, variability, energy-aware systems, main memory, allocation\/deallocation strategies, operating systems},\nmonth = {May},\npages = {1483--1496},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J33_paper.pdf},\ntitle = {{V}i{P}{Z}on{E}: {H}ardware {P}ower {V}ariability-{A}ware {V}irtual {M}emory {M}anagement for {E}nergy {S}avings},\nvolume = {64},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [J37]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j37.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Wang, A. Pan, C. O. Chui, and P. Gupta, &#8220;Proceed: a pareto optimization-based circuit-level evaluator for emerging devices,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_30\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_30_block\"><pre><code class=\"tex bibtex\">@article{J37,\nauthor = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {Emerging device, evaluator, proceed },\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J37_paper.pdf},\ntitle = {PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [J34]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j34.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Lai, V. Chandra, R. Aitken, and P. Gupta, &#8220;SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, vol. 33, iss. 8, pp. 1168-1179, 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_27\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_27_block\"><pre><code class=\"tex bibtex\">@article{J34,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {hsi},\nmonth = {Aug},\nnumber = {8},\npages = {1168-1179},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J34_paper.pdf},\ntitle = {{S}lack{P}robe: {A} {F}lexible and {E}fficient {I}n {S}itu {T}iming {S}lack {M}onitoring {M}ethodology},\nvolume = {33},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [J32]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j32.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Lai, V. Chandra, R. Aitken, and P. Gupta, &#8220;BTI-Gater: An Aging-Resilient Clock Gating Methodology,&#8221; <span style=\"font-style: italic\">IEEE Journal on Emerging and Selected Topics in Circuits and Systems<\/span>, vol. 4, iss. 2, pp. 180-189, 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_25\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_25_block\"><pre><code class=\"tex bibtex\">@article{J32,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},\njournal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},\nkeywords = {hsi, NBTI},\nmonth = {June},\nnumber = {2},\npages = {180-189},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J32_paper.pdf},\ntitle = {{B}{T}{I}-{G}ater: {A}n {A}ging-{R}esilient {C}lock {G}ating {M}ethodology},\nvolume = {4},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [J35]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j35.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1117\/1.JMM.13.4.043005' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        A. A. Kagalwalla and P. Gupta, &#8220;Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, vol. 13, iss. 4, p. 43005, 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_28\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_28_block\"><pre><code class=\"tex bibtex\">@article{J35,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\ndoi = {10.1117\/1.JMM.13.4.043005},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\nnumber = {4},\npages = {043005},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J35_paper.pdf},\ntitle = {Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects},\nvolume = {13},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [J36]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j36.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Badr, K. Ma, and P. Gupta, &#8220;Layout pattern-driven design rule evaluation,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_29\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_29_block\"><pre><code class=\"tex bibtex\">@article{J36,\nauthor = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J36_paper.pdf},\ntitle = {Layout Pattern-driven Design Rule Evaluation},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [J30]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j30.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, M. Gupta, and P. Gupta, &#8220;Framework for exploring the interaction between design rules and overlay control,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, vol. 12, iss. 3, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_23\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_23_block\"><pre><code class=\"tex bibtex\">@article{J30,\nauthor = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {variability},\nmonth = {August },\nnumber = {3},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J30_paper.pdf},\ntitle = {Framework for exploring the interaction between design rules and overlay control},\nvolume = {12},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [J29]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j29.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Wang, G. Leung, A. Pan, C. O. Chui, and P. Gupta, &#8220;Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless Finfet Technologies,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electronic Devices<\/span>, vol. 60, iss. 7, pp. 2186-2193, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_21\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_21_block\"><pre><code class=\"tex bibtex\">@article{J29,\nauthor = {Wang, Shaodi and Leung, Greg and Pan, Andrew and Chui, Chi On and Gupta, Puneet},\njournal = {{IEEE Transactions on Electronic Devices}},\nkeywords = {variability},\nmonth = {July },\nnumber = {7},\npages = {2186 - 2193},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J29_paper.pdf},\ntitle = {{E}valuation of {D}igital {C}ircuit-{L}evel {V}ariability in {I}nversion-{M}ode and {J}unctionless {F}inFET {T}echnologies},\nvolume = {60},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [J28]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j28.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. A. Kagalwalla and P. Gupta, &#8220;Design-Aware Defect-Avoidance Floorplanning of EUV Masks,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, vol. 26, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_20\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_20_block\"><pre><code class=\"tex bibtex\">@article{J28,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\nissue = {1},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J28_paper.pdf},\ntitle = {{Design-Aware Defect-Avoidance Floorplanning of EUV Masks}},\nvolume = {26},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [J31]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j31.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Chan, P. Gupta, A. B. Kahng, and L. Lai, &#8220;Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_24\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_24_block\"><pre><code class=\"tex bibtex\">@article{J31,\nauthor = {Chan, Tuck-Boon and Gupta, Puneet and Kahng, A. B. and Lai, Liangzhen},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi, DDRO},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J31_paper.pdf},\ntitle = {{S}ynthesis and {A}nalysis of {D}esign-{D}ependent {R}ing {O}scillator ({D}{D}{R}{O}) {P}erformance {M}onitors},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [J22]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j22.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    G. Leung, L. Lai, P. Gupta, and C. O. Chui, &#8220;Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32nm Finfet Technologies,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electronic Devices<\/span>, vol. 59, iss. 8, pp. 2057-2063, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_14\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_14_block\"><pre><code class=\"tex bibtex\">@article{J22,\nauthor = {Leung, Greg and Lai, Liangzhen and Gupta, Puneet and Chui, Chi On},\njournal = {{IEEE Transactions on Electronic Devices}},\nkeywords = {variability},\nmonth = {aug. },\nnumber = {8},\npages = {2057 -2063},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J22_paper.pdf},\ntitle = {{D}evice- and {C}ircuit-{L}evel {V}ariability {C}aused\nby {L}ine {E}dge {R}oughness for {S}ub-32nm {F}inFET {T}echnologies},\nvolume = {59},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j18.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, &#8220;Design-Aware Mask Inspection,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_9\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_9_block\"><pre><code class=\"tex bibtex\">@article{J18,\nauthor = {Kagalwalla, Abde Ali and Puneet Gupta and Progler, Chris and McDonald, Steve},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J18_paper.pdf},\ntitle = {Design-{A}ware {M}ask {I}nspection},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j19.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida and P. Gupta, &#8220;DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_10\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_10_block\"><pre><code class=\"tex bibtex\">@article{J19,\nauthor = {Ghaida, R. S. and Gupta, P.},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {design rules, technology assessment, dre, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J19_paper.pdf},\ntitle = {{DRE}: a {F}ramework for {E}arly {C}o-{E}valuation of {D}esign {R}ules, {T}echnology {C}hoices, and {L}ayout {M}ethodologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J20]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j20.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Gottscho, A. A. Kagalwalla, and P. Gupta, &#8220;Power Variability in Contemporary DRAMs,&#8221; <span style=\"font-style: italic\">IEEE Embedded Systems Letters<\/span>, vol. 4, p. 37\u201340, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_12\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_12_block\"><pre><code class=\"tex bibtex\">@article{J20,\nauthor = {Gottscho, Mark and Kagalwalla, Abde Ali and Gupta, Puneet},\nissue = {2},\njournal = {{IEEE Embedded Systems Letters}},\nkeywords = {DRAM, DDR3, power, variability, hsi},\npages = {37--40},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J20_paper.pdf},\ntitle = {{P}ower {V}ariability in {C}ontemporary {DRAM}s},\nvolume = {4},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J21]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j21.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Chan, A. Pant, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_13\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_13_block\"><pre><code class=\"tex bibtex\">@article{J21,\nauthor = {Chan, Tuck-Boon and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {Process monitoring, wafer pruning, variability},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J21_paper.pdf},\ntitle = {{D}esign {D}ependent {P}rocess {M}onitoring for {W}afer {M}anufacturing and {T}est {C}ost {R}eduction},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J23]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j23.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, &#8220;Hardware Variability-Aware Duty Cycling for Embedded Sensors,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_15\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_15_block\"><pre><code class=\"tex bibtex\">@article{J23,\nauthor = {Lucas Wanner and Charwak Apte and Rahul Balani and Puneet Gupta and Mani Srivastava},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/j23.pdf},\ntitle = {{H}ardware {V}ariability-{A}ware {D}uty {C}ycling for {E}mbedded {S}ensors},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J24]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j24.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Lee and P. Gupta, &#8220;ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_16\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_16_block\"><pre><code class=\"tex bibtex\">@article{J24,\nauthor = {John Lee and Puneet Gupta},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J24_paper.pdf},\ntitle = {{ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes}},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J25]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j25.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Mok, J. Lee, and P. Gupta, &#8220;Discrete sizing for leakage power optimization in physical design: a comparative study,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_17\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_17_block\"><pre><code class=\"tex bibtex\">@article{J25,\nauthor = {Santiago Mok and John Lee and Puneet Gupta},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J25_paper.pdf},\ntitle = {Discrete Sizing for Leakage Power Optimization in Physical Design: A Comparative Study},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J26]                            P. Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. N. T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester, &#8220;Underdesigned and opportunistic computing in presence of hardware variability,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012.  &#8211; <b>Keynote Paper<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_18\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_18_block\"><pre><code class=\"tex bibtex\">@article{J26,\nauthor = {Puneet Gupta and Yuvraj Agarwal and Lara Dolecek and Nikil Dutt and Rajesh K. Gupta and Rakesh Kumar and Subhasish Mitra and Alexandru Nicolauand Tajana Simunic Rosing and Mani B. Srivastava and Steven Swanson and Dennis Sylvester},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {hsi},\nnote = {Keynote Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/UnO_keynote.pdf},\ntitle = {Underdesigned and Opportunistic Computing in Presence of Hardware Variability},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J27]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j27.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, &#8220;Layout Decomposition and Legalization for Double-Patterning Technology,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_19\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_19_block\"><pre><code class=\"tex bibtex\">@article{J27,\nauthor = {Ghaida, R. S. and Agarwal, K. B. and Nassif, S. R. and Yuan, X. and Liebmann, L. W. and Gupta, P.},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi, multiple-patterning},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J27_paper.pdf},\ntitle = {{L}ayout {D}ecomposition and {L}egalization for {D}ouble-{P}atterning {T}echnology},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [J15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. B. Chan, A. A. Kagalwalla, and P. Gupta, &#8220;Measurement and Optimization of Electrical Process Window,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_6\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_6_block\"><pre><code class=\"tex bibtex\">@article{J15,\nauthor = {Chan, T.B. and Kagalwalla, Abde Ali and Gupta, P. },\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J15_paper.pdf},\ntitle = {{M}easurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [J16]                            P. Kulkarni, P. Gupta, and M. D. Ercegovac, &#8220;Trading accuracy for power in a multiplier architecture,&#8221; <span style=\"font-style: italic\">Journal of Low Power Electronics<\/span>, 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_7\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_7_block\"><pre><code class=\"tex bibtex\">@article{J16,\nauthor = {Kulkarni, P. and Gupta, P. and Ercegovac, M.D.},\njournal = {{Journal of Low Power Electronics}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/JOLPE_v3.pdf},\ntitle = {Trading Accuracy for Power in a Multiplier Architecture},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [J17]                            A. Pant, P. Gupta, and M. van der Schaar, &#8220;Appadapt: opportunistic application adaptation in presence of hardware variation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_8\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_8_block\"><pre><code class=\"tex bibtex\">@article{J17,\nauthor = {Aashish Pant and Gupta, Puneet and Mihaela van der Schaar},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/VarAwareAdapt.pdf},\ntitle = {AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [J12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Cong, P. Gupta, and J. Lee, &#8220;Evaluating Statistical Power Optimization,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, vol. 29, iss. 11, p. 1750\u20131762, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_3\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_3_block\"><pre><code class=\"tex bibtex\">@article{J12,\nauthor = {Cong, J. and Gupta, P. and Lee, John},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {sizing, mad},\nmonth = {Nov},\nnumber = {11},\npages = {1750--1762},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J12_paper.pdf},\ntitle = {{Evaluating Statistical Power Optimization}},\nvolume = {29},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [J10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida and P. Gupta, &#8220;Within-Layer Overlay Impact for Design in Metal Double Patterning,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_1\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_1_block\"><pre><code class=\"tex bibtex\">@article{J10,\nauthor = {Ghaida, R. S. and Gupta, P.},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {double patterning, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J10_paper.pdf},\ntitle = {Within-{L}ayer {O}verlay {I}mpact for {D}esign in {M}etal {D}ouble {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [J11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, &#8220;Electrical Assessment of Lithographic Gate Line-End Patterning,&#8221; <span style=\"font-style: italic\">spieJ<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_2\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_2_block\"><pre><code class=\"tex bibtex\">@article{J11,\nauthor = {Gupta, P. and Jeong, K. and Kahng, A.B. and Park, C.-H.},\njournal = {{spieJ}},\nkeywords = {mad, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J11_paper.pdf},\ntitle = {Electrical {A}ssessment of {L}ithographic {G}ate {L}ine-{E}nd {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [J13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, G. Torres, and P. Gupta, &#8220;Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_4\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_4_block\"><pre><code class=\"tex bibtex\">@article{J13,\nauthor = {Ghaida, R. S. and Torres, G. and Gupta, P.},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {double patterning, stdpl, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J13_paper.pdf},\ntitle = {{S}ingle-{M}ask {D}ouble-{P}atterning {L}ithography for {R}educed {C}ost and {I}mproved {O}verlay {C}ontrol},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [J14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Cheng, P. Gupta, C. J. Spanos, K. Qian, and L. He, &#8220;Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_5\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_5_block\"><pre><code class=\"tex bibtex\">@article{J14,\nauthor = {Cheng, L. and Gupta, P. and Spanos, C. J. and Qian, K. and He, L.},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J14_paper.pdf},\ntitle = {{P}hysically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [J9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Cheng, P. Gupta, and L. He, &#8220;Efficient Additive Statistical Leakage Estimation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2009.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_87\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_87_block\"><pre><code class=\"tex bibtex\">@article{J9,\nauthor = {Cheng, L. and Gupta, P. and He, L.},\ncategory = {J9},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J9_paper.pdf},\ntitle = {Efficient {A}dditive {S}tatistical {L}eakage {E}stimation},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [J7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Detailed Placement for Enhanced Control of Resist and Etch CDs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2007.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_66\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_66_block\"><pre><code class=\"tex bibtex\">@article{J7,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H.},\ncategory = {J7},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\nmonth = {December},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J7_paper.pdf},\ntitle = {Detailed {P}lacement for {E}nhanced {C}ontrol of {R}esist and {E}tch {CD}s},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [J6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, &#8220;Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2007.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_55\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_55_block\"><pre><code class=\"tex bibtex\">@article{J6,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},\ncategory = {J6},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J6_paper.pdf},\ntitle = {Self-{C}ompensating {D}esign for {R}eduction of {T}iming and {L}eakage {S}ensitivity to {S}ystematic {P}attern {D}ependent {V}ariation},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [J8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Performance-Driven Optical Proximity Correction for Mask Cost Reduction,&#8221; <span style=\"font-style: italic\">spieJ<\/span>, 2007.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_76\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_76_block\"><pre><code class=\"tex bibtex\">@article{J8,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\ncategory = {J8},\njournal = {{spieJ}},\nkeywords = {dats},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J8_paper.pdf},\ntitle = {Performance-{D}riven {O}ptical {P}roximity {C}orrection for {M}ask {C}ost {R}eduction},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [J4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, &#8220;Gate-Length Biasing for Runtime Leakage Control,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2006.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_33\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_33_block\"><pre><code class=\"tex bibtex\">@article{J4,\nauthor = {Gupta, P. and Kahng, A. B. and Sharma, P. and Sylvester, D.},\ncategory = {J4},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {sizing, mad},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J4_paper.pdf},\ntitle = {Gate-{L}ength {B}iasing for {R}untime {L}eakage {C}ontrol},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [J5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, C. -H. Park, K. Samadi, and X. Xu, &#8220;Wafer Topography-Aware Optical Proximity Correction,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2006.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_44\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_44_block\"><pre><code class=\"tex bibtex\">@article{J5,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Samadi, K. and Xu, X.},\ncategory = {J5},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\nmonth = {April},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J5_paper.pdf},\ntitle = {Wafer {T}opography-{A}ware {O}ptical {P}roximity {C}orrection},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [J2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, I. I. Mandoiu, and P. Sharma, &#8220;Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2005.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_11\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_11_block\"><pre><code class=\"tex bibtex\">@article{J2,\nauthor = {Gupta, P. and Kahng, A. B. and Mandoiu, I.I. and Sharma, P.},\ncategory = {J2},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J2_paper.pdf},\ntitle = {Layout-{A}ware {S}can {C}hain {S}ynthesis for {I}mproved {P}ath {D}elay {F}ault {C}overage},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [J1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and S. Mantik, &#8220;Routing Driven Scan Chain Ordering,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2005.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_0\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_0_block\"><pre><code class=\"tex bibtex\">@article{J1,\nauthor = {Gupta, P. and Kahng, A. B. and Mantik, S.},\ncategory = {J1},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\nkeywords = {},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J1_paper.pdf},\ntitle = {Routing {D}riven {S}can {C}hain {O}rdering},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [J3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and S. Muddu, &#8220;Quantifying Error in Dynamic Power Estimation of CMOS Circuits,&#8221; <span style=\"font-style: italic\">Journal of Analog Integrated Circuits and Signal Processing<\/span>, 2005.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_22\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_22_block\"><pre><code class=\"tex bibtex\">@article{J3,\nauthor = {Gupta, P. and Kahng, A. B. and Muddu, S.},\ncategory = {J3},\njournal = {{Journal of Analog Integrated Circuits and Signal Processing}},\nkeywords = {},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J3_paper.pdf},\ntitle = {Quantifying {E}rror in {D}ynamic {P}ower {E}stimation of {CMOS} {C}ircuits},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n\n<hr class=\"wp-block-separator is-style-wide\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Conferences\"><\/span>Conferences<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p> <ul class=\"papercite_bibliography\">          [C139]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c139.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Bhoumik, Z. Chen, P. Gupta, and K. Chakrabarty, &#8220;DART: Dynamic Repair for Interconnect Fault Tolerance in Hybrid Bonding,&#8221; in <span style=\"font-style: italic\">44th IEEE VLSI Test Symposium<\/span>,  2026, p. 7  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_132\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_132_block\"><pre><code class=\"tex bibtex\">@inproceedings{C139,\nauthor = {Bhoumik, Partho and Chen, Zhichao and Gupta, Puneet and Chakrabarty, Krishnendu},\nbooktitle = {{{44th IEEE VLSI Test Symposium}}},\ndoi = {},\nkeywords = {chiplets},\nmonth = {April},\nnote = {},\npages = {7},\ntitle = {{DART: Dynamic Repair for Interconnect Fault Tolerance in Hybrid Bonding}},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [C137]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c137.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    D. Ray, G. Karfakis, A. Graening, D. Ratchkov, and P. Gupta, &#8220;Thermally-aware system-technology co-optimization for ai systems,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2026  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_130\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_130_block\"><pre><code class=\"tex bibtex\">@inproceedings{C137,\nauthor = {Ray, Dedeepyo and Karfakis, George and Graening, Alexander and Ratchkov, David and Gupta, Puneet},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {},\nnumber = {},\npages = {},\ntitle = {Thermally-Aware System-Technology Co-Optimization for AI Systems},\nvolume = {},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [C138]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c138.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Yen, J. Jeong, and P. Gupta, &#8220;Link quality aware pathfinding for chiplet interconnects,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2026  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_131\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_131_block\"><pre><code class=\"tex bibtex\">@inproceedings{C138,\nauthor = {Yen, Aaron and Jeong, Jooyeon and Gupta, Puneet},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {},\nnumber = {},\npages = {},\ntitle = {Link Quality Aware Pathfinding for Chiplet Interconnects},\nvolume = {},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [C133]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c133.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/DAC63849.2025.11132483' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        Z. Chen and P. Gupta, &#8220;YAP: Yield Modeling and Simulation for Advanced Packaging,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2025, p. 7  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_126\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_126_block\"><pre><code class=\"tex bibtex\">@inproceedings{C133,\nauthor = {Chen, Zhichao and Gupta, Puneet},\nbooktitle = {{{Proc. ACM\/IEEE Design Automation Conference (DAC)}}},\ndoi = {https:\/\/doi.org\/10.1109\/DAC63849.2025.11132483},\nkeywords = {chiplets},\nmonth = {June},\nnote = {},\npages = {7},\ntitle = {{YAP: Yield Modeling and Simulation for Advanced Packaging}},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [C134]                    <a href='http:\/\/dx.doi.org\/10.1145\/3695053.3731055' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        S. Rashidi, W. Won, S. Srinivasan, P. Gupta, and T. Krishna, &#8220;Fred: a wafer-scale fabric for 3d parallel dnn training,&#8221; in <span style=\"font-style: italic\">Proceedings of the 52nd Annual International Symposium on Computer Architecture<\/span>,  2025, p. 34\u201348  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_127\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_127_block\"><pre><code class=\"tex bibtex\">@inproceedings{C134,\nauthor = {Rashidi, Saeed and Won, William and Srinivasan, Sudarshan and Gupta, Puneet and Krishna, Tushar},\nbooktitle = {{Proceedings of the 52nd Annual International Symposium on Computer Architecture}},\ndoi = {10.1145\/3695053.3731055},\nnumpages = {15},\npages = {34\u201348},\npublisher = {Association for Computing Machinery},\ntitle = {FRED: A Wafer-scale Fabric for 3D Parallel DNN Training},\nurl = {https:\/\/doi.org\/10.1145\/3695053.3731055},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [C135]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c135.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1117\/12.3051566' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        S. Jain, P. Woltgens, and P. Gupta, &#8220;Design enablement of low-cost stitching in high-na euv patterning,&#8221; in <span style=\"font-style: italic\">DTCO and Computational Patterning IV<\/span>,  2025  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_128\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_128_block\"><pre><code class=\"tex bibtex\">@inproceedings{C135,\nauthor = {Jain, Sagar and Woltgens, Pieter and Gupta, Puneet},\nbooktitle = {{DTCO and Computational Patterning IV}},\ndoi = {https:\/\/doi.org\/10.1117\/12.3051566},\npublisher = {SPIE},\ntitle = {Design enablement of low-cost stitching in high-NA EUV patterning},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [C136]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c136.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/MWSCAS53549.2025.11244410' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        A. H. Hassan, P. Gupta, S. Pamarti, and C. K. Yang, &#8220;Design and optimization of on-chip interconnects for cryogenic operation,&#8221; in <span style=\"font-style: italic\">2025 IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS)<\/span>,  2025, pp. 1036-1039  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_129\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_129_block\"><pre><code class=\"tex bibtex\">@inproceedings{C136,\nauthor = {Hassan, Ali H. and Gupta, Puneet and Pamarti, Sudhakar and Yang, Chih-Kong Ken},\nbooktitle = {{2025 IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS)}},\ndoi = {https:\/\/doi.org\/10.1109\/MWSCAS53549.2025.11244410},\nkeywords = {Temperature;Upper bound;Integrated circuit interconnections;Metals;Cryogenics;Repeaters;FinFETs;Delays;Logic;Optimization;Cryogenic Computing;Low Temperature;InverterBased Repeater;BEOL Interconnects;RC delay;DTCO},\nnumber = {},\npages = {1036-1039},\ntitle = {Design and Optimization of On-Chip Interconnects for Cryogenic Operation},\nvolume = {},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [C131]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c131.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Graening, D. A. Patel, G. Sisto, E. Lenormand, M. Perumkunnil, N. Pantano, V. B. Y. Kumar, P. Gupta, and A. Mallik, &#8220;Cost-performance co-optimization for the chiplet era,&#8221; in <span style=\"font-style: italic\">IEEE Electronics Packaging Technology Conference (EPTC)<\/span>,  2024, p. 6  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_124\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_124_block\"><pre><code class=\"tex bibtex\">@inproceedings{C131,\nauthor = {Graening, Alexander and Patel, Darayus Adil and Sisto, Giuliano and Lenormand, Erwan and Perumkunnil, Manu and Pantano, Nicolas and Kumar, Vinay B.Y. and Gupta, Puneet and Mallik, Arindam},\nbooktitle = {{IEEE Electronics Packaging Technology Conference (EPTC)}},\ndoi = {},\nkeywords = {},\nmonth = {December},\nnumber = {},\npages = {6},\ntitle = {Cost-Performance Co-Optimization for the Chiplet Era},\nvolume = {},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [C127]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c127.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, J. Yang, A. Graening, V. Jacob, J. Sen, S. Pamarti, and P. Gupta, &#8220;SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2024, p. 12  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_119\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_119_block\"><pre><code class=\"tex bibtex\">@inproceedings{C127,\nauthor = {Romaszkan, Wojciech and Yang, Jiyue and Graening, Alexander and Jacob, Vinod and Sen, Jishnu and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {},\nmonth = {September},\npages = {12},\ntitle = {{SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [C129]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c129.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Kundu, W. Guo, A. BanaGozar, U. D. Alwis, S. Sengupta, P. Gupta, and A. Mallik, &#8220;Performance Modeling and Workload Analysis of Distributed Large Language Model Training and Inference,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Workload Characterization<\/span>,  2024, p. 12  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_121\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_121_block\"><pre><code class=\"tex bibtex\">@inproceedings{C129,\nauthor = {Kundu, Joyjit and Guo, Wenzhe and BanaGozar, Ali and Alwis, Udari De and Sengupta, Sourav and Gupta, Puneet and Mallik, Arindam},\nbooktitle = {{IEEE International Symposium on Workload Characterization}},\ndoi = {},\nkeywords = {},\nmonth = {September},\nnote = {Best paper nomination},\npages = {12},\ntitle = {{Performance Modeling and Workload Analysis of Distributed\nLarge Language Model Training and Inference}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [C126]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c126.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal, J. Yang, S. Bauer, P. Gupta, and S. Pamarti, &#8220;Novel Energy-Efficient and Latency-Improved PVT Tolerant Read Scheme for SRAM Design in Video Processing and Machine Learning Applications,&#8221; in <span style=\"font-style: italic\">IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)<\/span>,  2024, p. 4  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_118\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_118_block\"><pre><code class=\"tex bibtex\">@inproceedings{C126,\nauthor = {Pal, Soumitra and Yang, Jiyue and Bauer, Stephen and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{{IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)}}},\ndoi = {},\nkeywords = {},\nmonth = {August},\nnote = {},\npages = {4},\ntitle = {{Novel Energy-Efficient and Latency-Improved PVT Tolerant Read Scheme for SRAM Design in Video Processing and Machine Learning Applications}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [C128]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c128.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Yang, A. Graening, W. Romaszkan, V. K. Jacob, P. Gupta, and S. Pamarti, &#8220;A 278-514M Event\/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera,&#8221; in <span style=\"font-style: italic\">IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)<\/span>,  2024, p. 2  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_120\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_120_block\"><pre><code class=\"tex bibtex\">@inproceedings{C128,\nauthor = {Yang, Jiyue and Graening, Alexander and Romaszkan, Wojciech and Jacob, Vinod K. and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)}},\ndoi = {},\nkeywords = {},\nmonth = {June},\npages = {2},\ntitle = {{A 278-514M Event\/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [C130]                    <a href='http:\/\/dx.doi.org\/10.1109\/MWSCAS60917.2024.10658785' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        A. H. Hassan, P. Gupta, S. Pamarti, and C. K. Yang, &#8220;Cryogenic alternative: cmos versus dynamic-based logic,&#8221; in <span style=\"font-style: italic\">2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)<\/span>,  2024, pp. 1007-1010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_123\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_123_block\"><pre><code class=\"tex bibtex\">@inproceedings{C130,\nauthor = {Hassan, Ali H. and Gupta, Puneet and Pamarti, Sudhakar and Yang, Chih-Kong Ken},\nbooktitle = {{2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)}},\ndoi = {10.1109\/MWSCAS60917.2024.10658785},\nkeywords = {Costs;Cooling;Liquid nitrogen;FinFETs;Threshold voltage;Energy efficiency;Logic;Cryogenic Computing;Efficient Computing;CryoCMOS;CMOS Logic;Domino Logic;NORA Logic;Adders},\nnumber = {},\npages = {1007-1010},\ntitle = {Cryogenic Alternative: CMOS Versus Dynamic-Based Logic},\nvolume = {},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [C132]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c132.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    H. Suhail, H. He, J. Yang, Q. Shu, C. -Y. Wang, S. -Y. Yang, Y. -C. Hsin, C. -Y. Shih, H. -H. Lee, D. Wu, A. Lee, J. H. Wei, P. Gupta, K. L. Wang, and S. Pamarti, &#8220;The first cmos-integrated voltage-controlled mram with 0.7ns switching time,&#8221; in <span style=\"font-style: italic\">IEEE International Electron Devices Meeting<\/span>,  2023, p. 4  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_125\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_125_block\"><pre><code class=\"tex bibtex\">@inproceedings{C132,\nauthor = {Suhail, Harris and He, H. and Yang, Jiyue and Shu, Q. and Wang, C. -Y. and Yang, S. -Y. and Hsin, Y. -C. and Shih, C. -Y. and Lee, H. -H and Wu, D. and Lee, A. and Wei, J. H. and Gupta, Puneet and Wang, Kang L. and Pamarti, Sudhakar},\nbooktitle = {{IEEE International Electron Devices Meeting}},\ndoi = {},\nkeywords = {},\nmonth = {December},\nnumber = {},\npages = {4},\ntitle = {The First CMOS-Integrated Voltage-Controlled MRAM with 0.7ns Switching Time},\nvolume = {},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [C125]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c125.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1145\/3613424.3623798.' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        S. Li, H. Yang, C. W. Wong, V. J. Sorger, and P. Gupta, &#8220;ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM International Symposium on Microarchitecture (MICRO)<\/span>,  2023, p. 13  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_117\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_117_block\"><pre><code class=\"tex bibtex\">@inproceedings{C125,\nauthor = {Li, Shurui and Yang, Hangbo and Wong, Chee Wei and Sorger, Volker J. and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM International Symposium on Microarchitecture (MICRO)}},\ndoi = {https:\/\/doi.org\/10.1145\/3613424.3623798.},\nkeywords = {photonic neural network,deep learning, accelerator, photonics},\nmonth = {October},\nnote = {},\npages = {13},\ntitle = {{ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [C124]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c124.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Graening, S. Pal, and P. Gupta, &#8220;Chiplets: How Small is too Small?,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2023, p. 6  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_116\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_116_block\"><pre><code class=\"tex bibtex\">@inproceedings{C124,\nauthor = {Graening, Alexander and Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ndoi = {},\nkeywords = {chiplets,wsi},\nmonth = {July},\nnote = {},\npages = {6},\ntitle = {{Chiplets: How Small is too Small?}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [C123]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c123.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c123_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. Li, S. Li, and P. Gupta, &#8220;Training Neural Networks for Execution on Approximate Hardware,&#8221; in <span style=\"font-style: italic\">International Research Symposium on Tiny Machine Learning (tinyML)<\/span>,  2023, p. 6  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_115\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_115_block\"><pre><code class=\"tex bibtex\">@inproceedings{C123,\nauthor = {Li, Tianmu and Li, Shurui and Gupta, Puneet},\nbooktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},\ndoi = {},\nkeywords = {approximate computing, neural networks, training},\nmonth = {March},\nnote = {},\npages = {6},\ntitle = {{Training Neural Networks for Execution on Approximate Hardware}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [C122]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c122.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Li, H. Yang, C. W. Wong, V. J. Sorger, and P. Gupta, &#8220;PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on High-Performance Computer Architecture (HPCA)<\/span>,  2023, p. 12  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_114\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_114_block\"><pre><code class=\"tex bibtex\">@inproceedings{C122,\nauthor = {Li, Shurui and Yang, Hangbo and Wong, Chee Wei and Sorger, Volker J. and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},\ndoi = {},\nkeywords = {photonics, neural network, accelerator},\nmonth = {February},\nnote = {},\npages = {12},\ntitle = {{PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [C121]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c121.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Yang, T. Li, W. Romaszkan, P. Gupta, and S. Pamarti, &#8220;A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor,&#8221; in <span style=\"font-style: italic\">IEEE Asian Solid-State Circuits Conference<\/span>,  2022, p. 2  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_113\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_113_block\"><pre><code class=\"tex bibtex\">@inproceedings{C121,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{IEEE Asian Solid-State Circuits Conference}},\ndoi = {},\nkeywords = {mledge},\nmonth = {November},\nnote = {},\npages = {2},\ntitle = {{A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [C120]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c120.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, T. Li, and P. Gupta, &#8220;SASCHA &#8211; Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2022, p. 12  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_112\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_112_block\"><pre><code class=\"tex bibtex\">@inproceedings{C120,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {October},\nnote = {Best paper nomination},\npages = {12},\ntitle = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [C119]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c119.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c119_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               S. Li and P. Gupta, &#8220;Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors,&#8221; in <span style=\"font-style: italic\">Conference on Machine Learning and Systems (MLSys)<\/span>,  2022, p. 10  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_110\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_110_block\"><pre><code class=\"tex bibtex\">@inproceedings{C119,\nauthor = {Li, Shurui and Gupta, Puneet},\nbooktitle = {{Conference on Machine Learning and Systems (MLSys)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {August},\nnote = {},\npages = {10},\ntitle = {{Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [C118]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c118.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam and P. Gupta, &#8220;COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors,&#8221; in <span style=\"font-style: italic\">IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)<\/span>,  2022, p. 13  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_109\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_109_block\"><pre><code class=\"tex bibtex\">@inproceedings{C118,\nauthor = {Alam, Irina and Gupta, Puneet},\nbooktitle = {{IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)}},\ndoi = {},\nkeywords = {},\nmonth = {June},\nnote = {},\npages = {13},\ntitle = {{COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [C117]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c117.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    V. Gupta, T. Li, and P. Gupta, &#8220;LAC: Learned Approximate Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2022, p. 4  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_108\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_108_block\"><pre><code class=\"tex bibtex\">@inproceedings{C117,\nauthor = {Gupta, Vaibhav and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {},\nkeywords = {},\nmonth = {March},\nnote = {},\npages = {4},\ntitle = {{LAC: Learned Approximate Computing}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [C116]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c116.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal, J. Liu, I. Alam, N. Cebry, H. Suhail, S. Bu, S. S. Iyer, S. Pamarti, R. Kumar, and P. Gupta, &#8220;Designing a 2048-Chiplet, 14336-Core Waferscale Processor,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_107\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_107_block\"><pre><code class=\"tex bibtex\">@inproceedings{C116,\nauthor = {Pal, Saptadeep and Liu, Jingyang and Alam, Irina and Cebry, Nicholas and Suhail, Haris and Bu, Shi and Iyer, Subramanian S. and Pamarti, Sudhakar and Kumar, Rakesh and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ndoi = {},\nkeywords = {wsi},\nmonth = {December},\nnote = {},\npages = {},\ntitle = {{Designing a 2048-Chiplet, 14336-Core Waferscale Processor}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [C115]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c115.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Yang, D. Wu, A. Lee, S. A. Razavi, P. Gupta, K. L. Wang, and S. Pamarti, &#8220;A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM,&#8221; in <span style=\"font-style: italic\">IEEE European Solid-State Circuits Conference (ESSCIRC)<\/span>,  2021, p. 4  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_106\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_106_block\"><pre><code class=\"tex bibtex\">@inproceedings{C115,\nauthor = {Yang, Jiyue and Wu, Di and Lee, Albert and Razavi, Seyed Armin and Gupta, Puneet and Wang, Kang L. and Pamarti, Sudhakar},\nbooktitle = {{IEEE European Solid-State Circuits Conference (ESSCIRC)}},\ndoi = {},\nkeywords = {},\nmonth = {September},\nnote = {},\npages = {4},\ntitle = {{A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [C114]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c114.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal, K. Sahoo, I. Alam, H. Suhail, R. Kumar, S. Pamarti, P. Gupta, and S. S. Iyer, &#8220;I\/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_105\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_105_block\"><pre><code class=\"tex bibtex\">@inproceedings{C114,\nauthor = {Pal, Saptadeep and Sahoo, Krutikesh and Alam, Irina and Suhail, Haris and Kumar, Rakesh and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {wsi},\nmonth = {June},\nnote = {},\npages = {},\ntitle = {{I\/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [C113]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c113.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Li, W. Romaszkan, A. Graening, and P. Gupta, &#8220;SWIS &#8211; Shared Weight bIt Sparsity for Efficient Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">International Research Symposium on Tiny Machine Learning (tinyML)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_104\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_104_block\"><pre><code class=\"tex bibtex\">@inproceedings{C113,\nauthor = {Li, Shurui and Romaszkan, Wojciech and Graening, Alexander and Gupta, Puneet},\nbooktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},\ndoi = {},\nkeywords = {mledge, quantization, systolic array},\nmonth = {March},\nnote = {},\npages = {},\ntitle = {{SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [C112]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c112.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Li, W. Romaszkan, S. Pamarti, and P. Gupta, &#8220;GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_103\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_103_block\"><pre><code class=\"tex bibtex\">@inproceedings{C112,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {},\nkeywords = {mledge},\nmonth = {February},\nnote = {},\npages = {},\ntitle = {{GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [C111]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c111.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal and P. Gupta, &#8220;Pathfinding for 2.5D Interconnect Technologies,&#8221; in <span style=\"font-style: italic\">System-Level Interconnect &#8211; Problems and Pathfinding Workshop<\/span>, New York, NY, USA,  2020  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_102\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_102_block\"><pre><code class=\"tex bibtex\">@inproceedings{C111,\naddress = {New York, NY, USA},\nauthor = {Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{System-Level Interconnect - Problems and Pathfinding Workshop}},\nkeywords = {wsi},\nlocation = {San Diego, California},\nmonth = {November},\nnumpages = {8},\npublisher = {ACM},\nseries = {SLIP '20},\ntitle = {{Pathfinding for 2.5D Interconnect Technologies}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [C110]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c110.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam and P. Gupta, &#8220;SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge,&#8221; in <span style=\"font-style: italic\">Proceedings of the International Symposium on Memory Systems<\/span>, New York, NY, USA,  2020  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_101\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_101_block\"><pre><code class=\"tex bibtex\">@inproceedings{C110,\naddress = {New York, NY, USA},\nauthor = {Alam, Irina and Gupta, Puneet},\nbooktitle = {{Proceedings of the International Symposium on Memory Systems}},\nkeywords = {memres},\nlocation = {Washington, District of Columbia},\nmonth = {September},\nnumpages = {13},\npublisher = {ACM},\nseries = {MEMSYS '20},\ntitle = {{SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [C109]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c109.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.23919\/DATE48585.2020.9116289' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        W. Romaszkan, T. Li, T. Melton, S. Pamarti, and P. Gupta, &#8220;ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2020, pp. 768-773  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_99\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_99_block\"><pre><code class=\"tex bibtex\">@inproceedings{C109,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Melton, Tristan and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {10.23919\/DATE48585.2020.9116289},\nkeywords = {mledge},\nmonth = {March},\nnote = {Best paper nomination},\npages = {768-773},\ntitle = {{ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [C108]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c108.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1145\/3357526.3357533' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        I. Alam, S. Pal, and P. Gupta, &#8220;Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories,&#8221; in <span style=\"font-style: italic\">Proceedings of the International Symposium on Memory Systems<\/span>, New York, NY, USA,  2019, p. 85\u2013100  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_98\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_98_block\"><pre><code class=\"tex bibtex\">@inproceedings{C108,\nacmid = {3357533},\naddress = {New York, NY, USA},\nauthor = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{Proceedings of the International Symposium on Memory Systems}},\ndoi = {10.1145\/3357526.3357533},\nisbn = {978-1-4503-7206-0},\nkeywords = {memres},\nlocation = {Washington, District of Columbia},\nmonth = {September},\nnumpages = {16},\npages = {85--100},\npublisher = {ACM},\nseries = {MEMSYS '19},\ntitle = {{Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},\nurl = {http:\/\/doi.acm.org\/10.1145\/3357526.3357533},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [C107]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c107.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1109\/HPCA.2019.00042' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        S. Pal, D. Petrisko, M. Tomei, S. S. Iyer, P. Gupta, and R. Kumar, &#8220;Architecting Waferscale Processors &#8211; A GPU Case Study,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on High-Performance Computer Architecture (HPCA)<\/span>,  2019, pp. 250-263  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_97\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_97_block\"><pre><code class=\"tex bibtex\">@inproceedings{C107,\nauthor = {Pal, Saptadeep and Petrisko, Daniel and Tomei, Matthew and Iyer, Subramanian S. and Gupta, Puneet and Kumar, Rakesh},\nbooktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},\ndoi = {10.1109\/HPCA.2019.00042},\nissn = {1530-0897},\nkeywords = {wsi},\nmonth = {February},\npages = {250-263},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C106_paper.pdf},\ntitle = {{Architecting Waferscale Processors - A GPU Case Study}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [C106]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c106.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Schoeny, I. Alam, M. Gottscho, P. Gupta, and L. Dolecek, &#8220;Error Correction and Detection for Computing Memories Using System Side Information,&#8221; in <span style=\"font-style: italic\">IEEE Information Theory Workshop (ITW)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_96\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_96_block\"><pre><code class=\"tex bibtex\">@inproceedings{C106,\nauthor = {Schoeny, Clayton and Alam, Irina and Gottscho, Mark and Gupta, Puneet and Dolecek, Lara},\nbooktitle = {{IEEE Information Theory Workshop (ITW)}},\nkeywords = {memres},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C108_paper.pdf},\ntitle = {{Error Correction and Detection for Computing Memories Using System Side Information}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [C105]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c105.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Chae, R. Jonckheere, and P. Gupta, &#8220;Defect Avoidance for Extreme Ultraviolet Mask Defects using Intentional Pattern Deformation,&#8221; in <span style=\"font-style: italic\">SPIE, International Conference on Extreme Ultraviolet Lithography<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_95\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_95_block\"><pre><code class=\"tex bibtex\">@inproceedings{C105,\nauthor = {Chae, Yoojin and Jonckheere, Rik and Gupta, Puneet},\nbooktitle = {{SPIE, International Conference on Extreme Ultraviolet Lithography}},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C105_paper.pdf},\ntitle = {{Defect Avoidance for Extreme Ultraviolet Mask Defects using Intentional Pattern Deformation}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [C104]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c104.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Parity++: Lightweight Error Correction for Last Level Caches,&#8221; in <span style=\"font-style: italic\">IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_94\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_94_block\"><pre><code class=\"tex bibtex\">@inproceedings{C104,\nauthor = {Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)}},\nkeywords = {memres},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C104_paper.pdf},\ntitle = {{Parity++: Lightweight Error Correction for Last Level Caches}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [C103]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c103.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Luo and P. Gupta, &#8220;Relaxing ler requirement in euv lithography,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_93\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_93_block\"><pre><code class=\"tex bibtex\">@inproceedings{C103,\nauthor = {Luo, Yandong and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography}},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C103_paper.pdf},\ntitle = {Relaxing LER requirement in EUV Lithography},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [C100]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c100.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal, D. Petrisko, A. Bajwa, S. S. Iyer, R. Kumar, and P. Gupta, &#8220;A Case for Packageless Processors,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on High-Performance Computer Architecture (HPCA)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_90\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_90_block\"><pre><code class=\"tex bibtex\">@inproceedings{C100,\nauthor = {Pal, Saptadeep and Petrisko, Daniel and Bajwa, Adeel and Iyer, Subramanian S. and Kumar, Rakesh and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},\nkeywords = {wsi},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C100_paper.pdf},\ntitle = {{A Case for Packageless Processors}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [C102]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c102.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c102_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               A. Deng, Y. Badr, and P. Gupta, &#8220;Dynamic programming approach to adaptive slicing for optimization under a global volumetric error constraint,&#8221; in <span style=\"font-style: italic\">SPIE Laser 3D Manufacturing V<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_92\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_92_block\"><pre><code class=\"tex bibtex\">@inproceedings{C102,\nauthor = {Deng, Andrew and Badr, Yasmine and Gupta, Puneet},\nbooktitle = {{SPIE Laser 3D Manufacturing V}},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C102_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C102_slides.pptx},\ntitle = {Dynamic programming approach to adaptive slicing for optimization under a global volumetric error constraint},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [C101]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c101.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Schoeny, F. Sala, M. Gottscho, I. Alam, P. Gupta, and L. Dolecek, &#8220;Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories,&#8221; in <span style=\"font-style: italic\">IEEE Information Theory Workshop (ITW)<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_91\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_91_block\"><pre><code class=\"tex bibtex\">@inproceedings{C101,\nauthor = {Schoeny, Clayton and Sala, Fredric and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},\nbooktitle = {{IEEE Information Theory Workshop (ITW)}},\nkeywords = {memres},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C101_paper.pdf},\ntitle = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [C98]               <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c98_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               M. Gottscho, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Low-Cost Memory Fault Tolerance for IoT Devices,&#8221; , 2017.  &#8211; <b>Best paper award<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_224\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_224_block\"><pre><code class=\"tex bibtex\">@article{C98,\nauthor = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},\nkeywords = {memres},\nmonth = {October},\nnote = {Best paper award},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J54_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C98_slides.pptx},\ntitle = {{Low-Cost Memory Fault Tolerance for IoT Devices}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [C99]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c99.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang, Y. Yona, Y. Wu, S. Hung, S. Diggavi, and P. Gupta, &#8220;Implementation of Stable PUFs Using Gate Oxide Breakdown,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST)<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_225\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_225_block\"><pre><code class=\"tex bibtex\">@inproceedings{C99,\nauthor = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Hung, Szu-Yao and Diggavi, Suhas and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST)}},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C99_paper.pdf},\ntitle = {{Implementation of Stable PUFs Using Gate Oxide Breakdown}},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [C96]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c96.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c96_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            S. Jangam, S. Pal, A. Bajwa, S. Pamarti, P. Gupta, and S. S. Iyer, &#8220;Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_222\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_222_block\"><pre><code class=\"tex bibtex\">@inproceedings{C96,\nauthor = {Jangam, SivaChandra and Pal, Saptadeep and Bajwa, Adeel and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\nkeywords = {Silicon Interconnect Fabric; Thermal Compression Bonding; Fine Pitch Interconnect, SuperCHIPS, wsi},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C96_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C96_slides.pdf},\ntitle = {{L}atency, {B}andwidth and {P}ower {B}enefits of the {S}uper{CHIPS} {I}ntegration {S}cheme},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [C95]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c95.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c95_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            S. Wang, S. Pal, T. Li, A. Pan, C. Grezes, K. P. Amiri, K. L. Wang, C. O. Chui, and P. Gupta, &#8220;Hybrid VC-MTJ\/CMOS Non-volatile Stochastic Logic for Efficient Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2017  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_221\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_221_block\"><pre><code class=\"tex bibtex\">@inproceedings{C95,\nauthor = {Wang, Shaodi and Pal, Saptadeep and Li, Tianmu and Pan, Andrew and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Chui, Chi On and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nkeywords = {mledge,Negative differential resistance, Magnetic tunnel junction, stochastic computing, stochastic bitstream generator, non-volatile computing},\nmonth = {March},\nnote = {Best paper nomination},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_slides.pdf},\ntitle = {{H}ybrid {VC-MTJ\/CMOS} {N}on-volatile {S}tochastic {L}ogic for {E}fficient {C}omputing},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [C97]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c97.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Badr and P. Gupta, &#8220;Technology Path-finding for Directed Self-assembly for Via Layers&#8221;,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_223\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_223_block\"><pre><code class=\"tex bibtex\">@inproceedings{C97,\nauthor = {Badr, Yasmine and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C97_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C97_slides.pdf},\ntitle = {{T}echnology {P}ath-finding for {D}irected {S}elf-assembly for {V}ia {L}ayers\"},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [C92]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c92.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c92_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            S. Wang, H. Lee, C. Grezes, P. Khalili, K. L. Wang, and P. Gupta, &#8220;MTJ Variation Monitor-assisted Adaptive MRAM Write,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_218\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_218_block\"><pre><code class=\"tex bibtex\">@inproceedings{C92,\nauthor = {Wang, Shaodi and Lee, Hochul and Grezes, Cecile and Khalili, Pedram and Wang, Kang L. and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {MRAM},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C92_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C92_slides.pdf},\ntitle = { {MTJ} {V}ariation {M}onitor-assisted {A}daptive {MRAM} {W}rite},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [C93]                            M. Gottscho, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Software-Defined Error-Correcting Codes,&#8221; in <span style=\"font-style: italic\">IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_219\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_219_block\"><pre><code class=\"tex bibtex\">@conference{C93,\nauthor = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)}},\nkeywords = {ecc,memory,reliability,architecture,coding,systems,dram,caches,memres},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_slides.pptx},\ntitle = {{Software-Defined Error-Correcting Codes}},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [C94]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c94.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang, Y. Yona, S. Diggavi, and P. Gupta, &#8220;LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Hardware Oriented Security and Trust (HOST)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_220\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_220_block\"><pre><code class=\"tex bibtex\">@inproceedings{C94,\nauthor = {Wang, Wei-Che and Yona, Yair and Diggavi, Suhas and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Hardware Oriented Security and Trust (HOST)}},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C94_paper.pdf},\ntitle = {{LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity}},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [C91]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c91.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c91_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            M. Gottscho, S. Govindan, B. Sharma, M. Shoaib, and P. Gupta, &#8220;X-Mem: A Cross-Platform and Extensible Memory Characterization Tool for the Cloud,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_217\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_217_block\"><pre><code class=\"tex bibtex\">@inproceedings{C91,\nauthor = {Gottscho, Mark and Govindan, Sriram and Sharma, Bikash and Shoaib, Mohammed and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)}},\nkeywords = {},\nmonth = {April},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C91_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C91_slides.pdf},\ntitle = {{X}-{M}em: {A} {C}ross-{P}latform and {E}xtensible {M}emory {C}haracterization {T}ool for the {C}loud},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [C89]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c89.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c89_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               Q. Zhang, L. Lai, M. Gottscho, and P. Gupta, &#8220;Multi-Story Power Distribution Networks for GPUs,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_214\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_214_block\"><pre><code class=\"tex bibtex\">@inproceedings{C89,\nauthor = {Zhang, Qixiang and Lai, Liangzhen and Gottscho, Mark and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C89_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C89_slides.pptx},\ntitle = {{M}ulti-{S}tory {P}ower {D}istribution {N}etworks for {GPU}s},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [C90]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c90.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c90_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               L. Lai and P. Gupta, &#8220;Hardware Reliability Margining for the Dark Silicon Era,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_216\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_216_block\"><pre><code class=\"tex bibtex\">@inproceedings{C90,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {hsi},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C90_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C90_slides.pptx},\ntitle = {{H}ardware {R}eliability {M}argining for the {D}ark {S}ilicon {E}ra},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [C88]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c88.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c88_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            L. Lai, V. Chandra, and P. Gupta, &#8220;Evaluating and Exploiting Impacts of Dynamic Power Management Schemes on System Reliability,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_213\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_213_block\"><pre><code class=\"tex bibtex\">@inproceedings{C88,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)}},\nkeywords = {hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C88_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C88_slides.pdf},\ntitle = {{E}valuating and {E}xploiting {I}mpacts of {D}ynamic {P}ower {M}anagement {S}chemes on {S}ystem {R}eliability},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [C86]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c86.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c86_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            Y. Badr, A. Torres, and P. Gupta, &#8220;Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts\/Vias,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_211\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_211_block\"><pre><code class=\"tex bibtex\">@inproceedings{C86,\nauthor = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C86_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C86_slides.pdf},\ntitle = { {M}ask {A}ssignment and {S}ynthesis of {DSA}-{MP} {H}ybrid {L}ithography for sub-7nm {C}ontacts\/{V}ias},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [C87]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c87.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c87_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               A. A. Kagalwalla and P. Gupta, &#8220;Effective Model-Based Mask Fracturing for Mask Cost Reduction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_212\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_212_block\"><pre><code class=\"tex bibtex\">@inproceedings{C87,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C87_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C87_slides.pptx},\ntitle = { {E}ffective {M}odel-{B}ased {M}ask {F}racturing for {M}ask {C}ost {R}eduction},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [C85]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c85.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Badr, A. Torres, and P. Gupta, &#8220;Incorporating DSA in multipatterning semiconductor manufacturing technologies,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_210\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_210_block\"><pre><code class=\"tex bibtex\">@inproceedings{C85,\nauthor = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C85_paper.pdf},\ntitle = { {I}ncorporating {DSA} in {m}ultipatterning {s}emiconductor {m}anufacturing {t}echnologies},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [C83]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c83.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Sarma, N. Dutt, P. Gupta, N. Venkatasubramanian, and A. Nicolau, &#8220;CyberPhysical-System-On-Chip (CPSoC) : A Self-Aware MPSoC Paradigm with Cross-Layer Virtual Sensing and Actuation,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_209\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_209_block\"><pre><code class=\"tex bibtex\">@inproceedings{C83,\nauthor = {Sarma, Santanu and Dutt, Nikil and Gupta, Puneet and Venkatasubramanian, Nalini and Nicolau, Alex},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C83_paper.pdf},\nslideurl = {},\ntitle = {{CyberPhysical-System-On-Chip (CPSoC) : A Self-Aware MPSoC Paradigm with Cross-Layer Virtual Sensing and Actuation}},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [C80]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c80.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, A. B. Kahng, and E. Sahouria, &#8220;Benchmarking of Mask Fracturing Heuristics,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_206\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_206_block\"><pre><code class=\"tex bibtex\">@inproceedings{C80,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. and Sahouria, Emile},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C80},\nkeywords = {dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C80_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C80_slides.pdf},\ntitle = {Benchmarking of {M}ask {F}racturing {H}euristics},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C81]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c81.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang and P. Gupta, &#8220;Efficient Layout Generation and Evaluation of Vertical Channel Devices,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_207\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_207_block\"><pre><code class=\"tex bibtex\">@inproceedings{C81,\nauthor = {Wang, Wei-Che and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C81},\nkeywords = {dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C81_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C81_slides.pdf},\ntitle = {{E}fficient {L}ayout {G}eneration and {E}valuation of {V}ertical {C}hannel {D}evices},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C82]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c82.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c82_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            S. Elmalaki, M. Gottscho, P. Gupta, and M. Srivastava, &#8220;A Case for Battery Charging-Aware Power Management and Deferrable Task Scheduling in Smartphones,&#8221; in <span style=\"font-style: italic\">USENIX Workshop on Power-Aware Computing and Systems (HotPower)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_208\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_208_block\"><pre><code class=\"tex bibtex\">@inproceedings{C82,\nauthor = {Elmalaki, Salma and Gottscho, Mark and Gupta, Puneet and Srivastava, Mani},\nbooktitle = {{USENIX Workshop on Power-Aware Computing and Systems (HotPower)}},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C82_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C82_slides.pdf},\ntitle = {{A} {C}ase for {B}attery {C}harging-{A}ware {P}ower {M}anagement and {D}eferrable {T}ask {S}cheduling in {S}martphones},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C79]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c79.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c79_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            M. Gottscho, A. Banaiyan  Mofrad, N. Dutt, A. Nicolau, and P. Gupta, &#8220;Power \/ Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_204\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_204_block\"><pre><code class=\"tex bibtex\">@inproceedings{C79,\nauthor = {Gottscho, Mark and Banaiyan, Mofrad, Abbas and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {memres},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C79_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C79_slides.pdf},\ntitle = {{P}ower \/ {C}apacity {S}caling: {E}nergy {S}avings {W}ith {S}imple {F}ault-{T}olerant {C}aches},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C76]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c76.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c76_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            P. Kulkarni, P. Gupta, and R. Beraha, &#8220;Minimizing Clock Domain Crossing in Network on Chip Interconnect,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_201\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_201_block\"><pre><code class=\"tex bibtex\">@inproceedings{C76,\nauthor = {Kulkarni, Parag and Gupta, Puneet and Beraha, Rudy},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\nkeywords = {dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C76_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C76_slides.pdf},\ntitle = {{M}inimizing {C}lock {D}omain {C}rossing in {N}etwork on {C}hip {I}nterconnect},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C77]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c77.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c77_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            A. A. Kagalwalla and P. Gupta, &#8220;Comprehensive Defect Avoidance Framework for Mitigating EUV Mask Defects,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_202\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_202_block\"><pre><code class=\"tex bibtex\">@inproceedings{C77,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C77_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C77_slides.pdf},\ntitle = {{C}omprehensive {D}efect {A}voidance {F}ramework for {M}itigating {EUV} {M}ask {D}efects},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C78]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c78.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c78_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            Y. Badr, K. Ma, and P. Gupta, &#8220;Layout Pattern-driven Design Rule Evaluation,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_203\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_203_block\"><pre><code class=\"tex bibtex\">@inproceedings{C78,\nauthor = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C78_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C78_slides.pdf},\ntitle = {{L}ayout {P}attern-driven {D}esign {R}ule {E}valuation},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C73]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c73.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c73_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            A. A. Kagalwalla, M. Lam, K. Adam, and P. Gupta, &#8220;EUV-CDA: Pattern Shift Aware Critical Density Analysis for EUV Mask Layouts,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_198\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_198_block\"><pre><code class=\"tex bibtex\">@inproceedings{C73,\nauthor = {Kagalwalla, Abde Ali and Lam, Michael and Adam, Kostas and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C73_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C73_slides.pdf},\ntitle = {{EUV-CDA}: {P}attern {S}hift {A}ware {C}ritical {D}ensity {A}nalysis for {EUV} {M}ask {L}ayouts},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C74]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c74.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c74_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, &#8220;Comprehensive Die-level Assessment of Design Rules and Layouts,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_199\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_199_block\"><pre><code class=\"tex bibtex\">@inproceedings{C74,\nauthor = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {dats,dre},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_slides.pdf},\ntitle = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C75]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c75.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c75_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               S. Wang, A. Pan, C. O. Chui, and P. Gupta, &#8220;PROCEED: a Pareto Optimization-based Circuit-level Evaluator for Emerging Devices,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_200\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_200_block\"><pre><code class=\"tex bibtex\">@inproceedings{C75,\nauthor = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {dats,proceed},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C75_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C75_slides.pptx},\ntitle = {{PROCEED:} A {P}areto {O}ptimization-based {C}ircuit-level {E}valuator for {E}merging {D}evices},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [C70]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c70.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Wanner, S. Elmalaki, L. Lai, P. Gupta, and M. Srivastava, &#8220;VarEMU: An Emulation Testbed for Variability-Aware Software,&#8221; in <span style=\"font-style: italic\">ACM International Conference on Hardware\/Software Codesign and System Synthesis<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_195\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_195_block\"><pre><code class=\"tex bibtex\">@inproceedings{C70,\nauthor = {Wanner, Lucas and Elmalaki, Salma and Lai, Liangzhen and Gupta, Puneet and Srivastava, Mani},\nbooktitle = {{ACM International Conference on Hardware\/Software Codesign and System Synthesis}},\ncategory = {C70},\nkeywords = {hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C70_paper.pdf},\ntitle = {{V}ar{E}{M}{U}: {A}n {E}mulation {T}estbed for {V}ariability-{A}ware {S}oftware},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [C71]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c71.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Namaki-Shoushtari, A. Rahimi, N. Dutt, P. Gupta, and R. K. Gupta, &#8220;ARGO: Aging-aware GPGPU register file allocation,&#8221; in <span style=\"font-style: italic\">ACM International Conference on Hardware\/Software Codesign and System Synthesis<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_196\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_196_block\"><pre><code class=\"tex bibtex\">@inproceedings{C71,\nauthor = {Namaki-Shoushtari, Majid and Rahimi, Abbas and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh K.},\nbooktitle = {{ACM International Conference on Hardware\/Software Codesign and System Synthesis}},\nkeywords = {hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C71_paper.pdf},\ntitle = {{A}{R}{G}{O}: {A}ging-aware {G}{P}{G}{P}{U} Register File Allocation},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [C72]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c72.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Sharma, J. Sloan, L. F. Wanner, S. H. Elmalaki, M. B. Srivastava, and P. Gupta, &#8220;Towards Analyzing and Improving Robustness of Software Applications to Intermittent and Permanent Faults in Hardware,&#8221; in <span style=\"font-style: italic\">Proc. IEEE International Conference on Computer Design<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_197\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_197_block\"><pre><code class=\"tex bibtex\">@inproceedings{C72,\nauthor = {Sharma, Ankur and Sloan, Joseph and Wanner, Lucas F. and Elmalaki, Salma H. and Srivastava, Mani B. and Gupta, Puneet},\nbooktitle = {{Proc. IEEE International Conference on Computer Design}},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C72_paper.pdf},\ntitle = {{T}owards {A}nalyzing and {I}mproving {R}obustness of {S}oftware {A}pplications to {I}ntermittent and {P}ermanent {F}aults in {H}ardware},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [C68]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c68.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c68_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            L. Lai, V. Chandra, R. Aitken, and P. Gupta, &#8220;SlackProbe: a low overhead in situ on-line timing slack monitoring methodology,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_192\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_192_block\"><pre><code class=\"tex bibtex\">@inproceedings{C68,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ncatetory = {C68},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C68_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C68_slides.pdf},\ntitle = {{S}lack{P}robe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [C69]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c69.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, M. Gupta, and P. Gupta, &#8220;A Framework for Exploring the Interaction between Design Rules and Overlay Control,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_193\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_193_block\"><pre><code class=\"tex bibtex\">@inproceedings{C69,\nauthor = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C69},\nkeywords = {overlay, design rules, dre, alignment},\nmonth = {Feburary},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C69_paper.pdf},\ntitle = {A {F}ramework for {E}xploring the {I}nteraction between {D}esign {R}ules and {O}verlay {C}ontrol},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [C64]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c64.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c64_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, &#8220;A methodology for the early exploration of design rules for multiple-patterning technologies,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_188\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_188_block\"><pre><code class=\"tex bibtex\">@inproceedings{C64,\nauthor = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C64},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_slides.pdf},\ntitle = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [C67]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c67.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c67_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            J. Lee and P. Gupta, &#8220;Impact of range and precision in technology on cell-based design,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_191\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_191_block\"><pre><code class=\"tex bibtex\">@inproceedings{C67,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C67},\nkeywords = {sizing},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C67_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C67_slides.pdf},\ntitle = {Impact of Range and Precision in Technology on Cell-Based Design},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [C65]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c65.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Bathen, M. Gottscho, N. Dutt, P. Gupta, and A. Nicolau, &#8220;ViPZonE: OS-Level Memory Variability-Aware Physical Address Zoning for Energy Savings,&#8221; in <span style=\"font-style: italic\">ACM International Conference on Hardware\/Software Codesign and System Synthesis<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_189\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_189_block\"><pre><code class=\"tex bibtex\">@inproceedings{C65,\nauthor = {Bathen, Luis and Gottscho, Mark and Dutt, Nikil and Gupta, Puneet and Nicolau, Alex},\nbooktitle = {{ACM International Conference on Hardware\/Software Codesign and System Synthesis}},\ncategory = {C65},\nkeywords = {hsi, vipzone, os, variability, variability-aware, dram, memory, power, zone, zoning, allocation},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C65_paper.pdf},\ntitle = {{V}i{P}{Z}on{E}: {O}{S}-{L}evel {M}emory {V}ariability-{A}ware {P}hysical {A}ddress {Z}oning for {E}nergy {S}avings},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [C66]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c66.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c66_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            J. Lee, P. Gupta, and F. Pikus, &#8220;Parametric hierarchy recovery in layout extracted netlists,&#8221; in <span style=\"font-style: italic\">Proc. IEEE Computer Society Annual Symposium on VLSI<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_190\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_190_block\"><pre><code class=\"tex bibtex\">@inproceedings{C66,\nauthor = {Lee, John and Gupta, Puneet and Pikus, Fedor},\nbooktitle = {{Proc. IEEE Computer Society Annual Symposium on VLSI}},\ncategory = {C66},\nkeywords = {variability-aware},\nmonth = {August},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C66_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C66_slides.pdf},\ntitle = {Parametric Hierarchy Recovery in Layout Extracted Netlists},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [C60]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c60.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c60_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. B. Chan, P. Gupta, A. Kahng, and L. Lai, &#8220;DDRO: a Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,&#8221; in <span style=\"font-style: italic\">ISQED<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_184\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_184_block\"><pre><code class=\"tex bibtex\">@inproceedings{C60,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen},\nbooktitle = {{ISQED}},\ncategory = {C60},\nkeywords = {hsi, DDRO},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C60_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C60_slides.pdf},\ntitle = {{DDRO}: A {N}ovel {P}erformance {M}onitoring {M}ethodology {B}ased on {D}esign-{D}ependent {R}ing {O}scillators},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [C61]                            L. A. D. Bathen, N. D. Dutt, A. Nicolau, and P. Gupta, &#8220;Vamv: variability-aware memory virtualization,&#8221; in <span style=\"font-style: italic\">DATE<\/span>,  2012  &#8211; <b>Best interactive presentation<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_185\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_185_block\"><pre><code class=\"tex bibtex\">@inproceedings{C61,\nauthor = {L.A.D. Bathen and N.D. Dutt and A. Nicolau and P. Gupta},\nbooktitle = {{DATE}},\nkeywords = {hsi},\nmonth = {March},\nnote = {Best interactive presentation},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/BathenDNG12.pdf},\ntitle = {VaMV: Variability-aware Memory Virtualization},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [C62]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c62.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta, &#8220;Design-of-Experiments Based Design Rule Optimization,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_186\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_186_block\"><pre><code class=\"tex bibtex\">@inproceedings{C62,\nauthor = {Kagalwalla, Abde Ali and Muddu, Swamy and Capodieci, Luigi and Zelnik, Coby and Gupta, Puneet },\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C62},\nkeywords = {Design Rules, DOE, dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C62_paper.pdf},\ntitle = {{D}esign-of-{E}xperiments {B}ased {D}esign {R}ule {O}ptimization},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [C63]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c63.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, K. Agarwal, L. Liebmann, S. R. Nassif, and P. Gupta, &#8220;A Novel Methodology for Triple\/Multiple-Patterning Layout Decomposition,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_187\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_187_block\"><pre><code class=\"tex bibtex\">@inproceedings{C63,\nauthor = {Ghaida, R. S. and Agarwal, K. and Liebmann, L. and Nassif, S. R. and Gupta, P.},\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C63},\nkeywords = {triple patterning, double patterning, dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C63_paper.pdf},\ntitle = {{A} {N}ovel {M}ethodology for {T}riple\/{M}ultiple-{P}atterning {L}ayout {D}ecomposition},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [C59]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c59.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c59_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, &#8220;A Framework for Double Patterning-Enabled Design,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_182\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_182_block\"><pre><code class=\"tex bibtex\">@inproceedings{C59,\nauthor = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C59},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C59_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C59_slides.pdf},\ntitle = {A {F}ramework for {D}ouble {P}atterning-{E}nabled {D}esign},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [C55]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c55.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c55_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, J. Sartori, P. Gupta, and R. Kumar, &#8220;On the Efficacy of NBTI Mitigation Techniques,&#8221; in <span style=\"font-style: italic\">Design, Automation, and Test in Europe (DATE)<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_178\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_178_block\"><pre><code class=\"tex bibtex\">@inproceedings{C55,\nauthor = {Chan, T.-B. and Sartori, John and Gupta, Puneet and Kumar, Rakesh},\nbooktitle = {{Design, Automation, and Test in Europe (DATE)}},\ncategory = {C55},\nkeywords = {variabilty-aware, embedded sensing, hsi, ucla_rdmode},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C55_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C55_slides.pdf},\ntitle = {{O}n the {E}fficacy of {NBTI} {M}itigation {T}echniques},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [C56]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c56.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c56_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            L. Wanner, R. Balani, S. Zahedi, C. Apte, P. Gupta, and M. Srivastava, &#8220;Variability Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems,&#8221; in <span style=\"font-style: italic\">Design, Automation, and Test in Europe (DATE)<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_179\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_179_block\"><pre><code class=\"tex bibtex\">@inproceedings{C56,\nauthor = {Wanner, Lucas and Balani, Rahul and Zahedi, Sadaf and Apte, Charwak and Gupta, Puneet and Srivastava, Mani },\nbooktitle = {{Design, Automation, and Test in Europe (DATE)}},\ncategory = {C56},\nkeywords = {variabilty-aware, embedded sensing, hsi},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C56_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C56_slides.pdf},\ntitle = {{V}ariability {A}ware {D}uty {C}ycle {S}cheduling in {L}ong {R}unning {E}mbedded {S}ensing {S}ystems},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [C57]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c57.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. A. Kagalwalla, P. Gupta, D. Hur, and C. Park, &#8220;Defect-aware Reticle Floorplanning for EUV Masks,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_180\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_180_block\"><pre><code class=\"tex bibtex\">@inproceedings{C57,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet and Hur, Duck-Hyung and Park, Chul-Hong },\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C57},\nkeywords = {EUV, floorplanning, dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C57_paper.pdf},\ntitle = {{D}efect-aware {R}eticle {F}loorplanning for {EUV} {M}asks},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [C54]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c54.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c54_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            P. Kulkarni, P. Gupta, and M. Ercegovac, &#8220;Trading Accuracy for Power with an Underdesigned Multiplier Architecture,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_177\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_177_block\"><pre><code class=\"tex bibtex\">@inproceedings{C54,\nauthor = {Kulkarni, Parag and Gupta, Puneet and Ercegovac, Milos},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C54},\nkeywords = {low power, hsi},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C54_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C54_slides.pdf},\ntitle = {{T}rading {A}ccuracy for {P}ower with an {U}nderdesigned {M}ultiplier {A}rchitecture},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [C52]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c52.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c52_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, &#8220;Design-aware Mask Inspection,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_175\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_175_block\"><pre><code class=\"tex bibtex\">@inproceedings{C52,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C52},\nkeywords = {mask manufacturing, inspection, dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C52_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C52_slides.pdf},\ntitle = {{D}esign-aware {M}ask {I}nspection},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C53]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c53.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c53_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, A. Pant, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_176\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_176_block\"><pre><code class=\"tex bibtex\">@inproceedings{C53,\nauthor = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C53},\nkeywords = {process variation, process monitoring, dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_slides.pdf},\ntitle = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C51]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c51.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c51_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            J. Lee and P. Gupta, &#8220;Incremental Gate Sizing for Late Process Changes,&#8221; in <span style=\"font-style: italic\">Proc. IEEE International Conference on Computer Design<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_174\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_174_block\"><pre><code class=\"tex bibtex\">@inproceedings{C51,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{Proc. IEEE International Conference on Computer Design}},\ncategory = {C51},\nkeywords = {sizing, mad},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C51_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C51_slides.pdf},\ntitle = {{I}ncremental {G}ate {S}izing for {L}ate {P}rocess {C}hanges},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C58]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c58.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c58_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, &#8220;A Case for Opportunistic Embedded Sensing In Presence of Hardware Power Varibility,&#8221; in <span style=\"font-style: italic\">HotPower&#8217;10<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_181\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_181_block\"><pre><code class=\"tex bibtex\">@conference{C58,\nauthor = {Wanner, Lucas and Apte, Charwak and Balani, Rahul and Gupta, Puneet and Srivastava, Mani},\nbooktitle = {{HotPower'10}},\ncategory = {C58},\nkeywords = {embedded sensing, leakage power, duty cycling, hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C58_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C58_slides.pdf},\ntitle = {{A} {C}ase for {O}pportunistic {E}mbedded {S}ensing {I}n {P}resence of {H}ardware {P}ower {V}aribility},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C50]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c50.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, &#8220;Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_173\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_173_block\"><pre><code class=\"tex bibtex\">@inproceedings{C50,\nauthor = {Gupta, Puneet and Kahng, Andrew and Kasibhatla, Amarnath and Sharma, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C50},\nkeywords = {sizing, eyecharts},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C50_paper.pdf},\ntitle = {{E}yecharts: {C}onstructive {B}enchmarking of {G}ate {S}izing {H}euristics},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C49]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c49.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Pant, P. Gupta, and M. van der Schaar, &#8220;Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability,&#8221; in <span style=\"font-style: italic\">ACM Great Lakes Symposium on Very Large Scale Integration<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_171\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_171_block\"><pre><code class=\"tex bibtex\">@inproceedings{C49,\nauthor = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},\nbooktitle = {{ACM Great Lakes Symposium on Very Large Scale Integration}},\ncategory = {C49},\nkeywords = {hsi},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C49_paper.pdf},\ntitle = {{S}oftware {A}daptation in {Q}uality {S}ensitive {A}pplications to {D}eal with {H}ardware {V}ariability},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C48]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c48.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Sartori, A. Pant, R. Kumar, and P. Gupta, &#8220;Variation Aware Speed Binning of Multi-core Processors,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_170\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_170_block\"><pre><code class=\"tex bibtex\">@inproceedings{C48,\nauthor = {Sartori, John and Pant, Aashish and Kumar, Rakesh and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\ncategory = {C48},\nkeywords = {hsi},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C48_paper.pdf},\ntitle = {{V}ariation {A}ware {S}peed {B}inning of {M}ulti-core {P}rocessors},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C46]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c46.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c46_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, A. A. Kagalwalla, and P. Gupta, &#8220;Measurement and Optimization of Electrical Process Window,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_168\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_168_block\"><pre><code class=\"tex bibtex\">@inproceedings{C46,\nauthor = {Chan, T.-B. and Kagalwalla, Abde Ali and Gupta, P.},\nbooktitle = {{Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration}},\ncategory = {C46},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C46_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C46_slides.pdf},\ntitle = {Measurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C45]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c45.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c45_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan and P. Gupta, &#8220;On Electrical Modeling of Imperfect Diffusion Patterning,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_167\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_167_block\"><pre><code class=\"tex bibtex\">@inproceedings{C45,\nauthor = {Chan, T.-B. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C45},\nkeywords = {dats, mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C45_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C45_slides.pdf},\ntitle = {On {E}lectrical {M}odeling of {I}mperfect {D}iffusion {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C47]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c47.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Cheng, P. Gupta, and L. He, &#8220;On Confidence in Characterization and Application of Variation Models,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_169\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_169_block\"><pre><code class=\"tex bibtex\">@inproceedings{C47,\nauthor = {Cheng, L. and Gupta, P. and He, L.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C47},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C47_paper.pdf},\ntitle = {On {C}onfidence in {C}haracterization and {A}pplication of {V}ariation {M}odels},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [C44]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c44.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c44_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida and P. Gupta, &#8220;A Framework for Early and Systematic Evaluation of Design Rules,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_166\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_166_block\"><pre><code class=\"tex bibtex\">@inproceedings{C44,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C44},\nkeywords = {dats, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C44_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C44_slides.pdf},\ntitle = {A {F}ramework for {E}arly and {S}ystematic {E}valuation of {D}esign {R}ules},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [C41]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c41.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c41_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, G. Torres, and P. Gupta, &#8220;Single-Mask Double-Patterning Lithography,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_163\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_163_block\"><pre><code class=\"tex bibtex\">@inproceedings{C41,\nauthor = {Ghaida, R. S. and Torres, G. and Gupta, P.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\nkeywords = {dats},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C41_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C41_slides.pdf},\ntitle = {Single-{M}ask {D}ouble-{P}atterning {L}ithography},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [C40]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c40.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c40_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida and P. Gupta, &#8220;Design-Overlay Interactions in Metal Double Patterning,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_162\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_162_block\"><pre><code class=\"tex bibtex\">@inproceedings{C40,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {double patterning, test pattern, dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C40_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C40_slides.pdf},\ntitle = {Design-{O}verlay {I}nteractions in {M}etal {D}ouble {P}atterning},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [C38]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c38.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c38_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            J. Cong, P. Gupta, and J. Lee, &#8220;On the Futlity of Statistical Power Optimization,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_159\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_159_block\"><pre><code class=\"tex bibtex\">@inproceedings{C38,\nauthor = {Cong, J. and Gupta, P. and Lee, John},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C38},\nkeywords = {sizing, mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C38_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C38_slides.pdf},\ntitle = {On the {F}utlity of {S}tatistical {P}ower {O}ptimization},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [C39]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c39.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Cheng, P. Gupta, and L. He, &#8220;Accounting for Non-linear Dependence Using Function Driven Component Analysis,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_160\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_160_block\"><pre><code class=\"tex bibtex\">@inproceedings{C39,\nauthor = {Cheng, L. and Gupta, P. and He, L.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C39},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C39_paper.pdf},\ntitle = {Accounting for {N}on-linear {D}ependence {U}sing {F}unction {D}riven {C}omponent {A}nalysis},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [C42]                            P. Gupta and D. Reinhard, &#8220;On Comparing Conventional and Electrically Driven OPC Techniques,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_164\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_164_block\"><pre><code class=\"tex bibtex\">@inproceedings{C42,\nauthor = {Gupta, P. and Reinhard, D.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\ncategory = {C42},\nkeywords = {dats},\nmonth = {},\ntitle = {On {C}omparing {C}onventional and {E}lectrically {D}riven {OPC} {T}echniques},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [C43]                            L. Cheng, P. Gupta, K. Qian, C. Spanos, and L. He, &#8220;Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_165\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_165_block\"><pre><code class=\"tex bibtex\">@inproceedings{C43,\nauthor = {Cheng, L. and Gupta, P. and Qian, K. and Spanos, C. and He, L.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C43},\nkeywords = {mad},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C43_paper.pdf},\ntitle = {Physically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [C37]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c37.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta and A. B. Kahng, &#8220;Bounded Lifetime Integrated Circuits,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2008  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_158\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_158_block\"><pre><code class=\"tex bibtex\">@inproceedings{C37,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C37},\nkeywords = {mad},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C37_paper.pdf},\ntitle = {Bounded {L}ifetime {I}ntegrated {C}ircuits},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [C36]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c36.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, &#8220;Electrical Metrics for Lithographic Line-End Tapering,&#8221; in <span style=\"font-style: italic\">SPIE Photomask and NGL Mask Technology<\/span>,  2008  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_157\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_157_block\"><pre><code class=\"tex bibtex\">@inproceedings{C36,\nauthor = {Gupta, P. and Jeong, K. and Kahng, A. B. and Park, C.-H},\nbooktitle = {{SPIE Photomask and NGL Mask Technology}},\ncategory = {C36},\nkeywords = {mad, dats},\nmonth = {April},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C36_paper.pdf},\ntitle = {Electrical {M}etrics for {L}ithographic {L}ine-{E}nd {T}apering},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [C35]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c35.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, &#8220;Shaping Gate Channels for Improved Devices,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2008  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_156\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_156_block\"><pre><code class=\"tex bibtex\">@inproceedings{C35,\nauthor = {Gupta, P. and Kahng, A. B. and Shah, S. and Sylvester, D.},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\ncategory = {C35},\nkeywords = {dats, mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C35_paper.pdf},\ntitle = {Shaping {G}ate {C}hannels for {I}mproved {D}evices},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [C34]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c34.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, &#8220;Investigation of Diffusion Rounding for Post-Lithography Analysis,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2008  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_155\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_155_block\"><pre><code class=\"tex bibtex\">@inproceedings{C34,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S. and Sylvester, D.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C34},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C34_paper.pdf},\ntitle = {Investigation of {D}iffusion {R}ounding for {P}ost-{L}ithography {A}nalysis},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [C33]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c33.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, &#8220;Line End Shortening is not Always a Failure,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2007  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_154\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_154_block\"><pre><code class=\"tex bibtex\">@inproceedings{C33,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C2},\nkeywords = {mad, dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C33_paper.pdf},\ntitle = {Line {E}nd {S}hortening is not {A}lways a {F}ailure},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [C32]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c32.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and S. Shah, &#8220;Standard Cell Library Optimization for Leakage Reduction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2006  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_153\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_153_block\"><pre><code class=\"tex bibtex\">@inproceedings{C32,\nauthor = {Gupta, P. and Kahng, A. B. and Shah, S.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C32},\nkeywords = {sizing},\nmonth = {July},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C32_paper.pdf},\ntitle = {Standard {C}ell {L}ibrary {O}ptimization for {L}eakage {R}eduction},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [C28]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c28.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah, and P. Sharma, &#8220;Lithography Simulation-Based Full-Chip Design Analyses,&#8221; in <span style=\"font-style: italic\">SPIE Microlithography<\/span>,  2006  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_148\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_148_block\"><pre><code class=\"tex bibtex\">@inproceedings{C28,\nauthor = {Gupta, P. and Kahng, A. B. and Nakagawa, S. and Shah, S. and Sharma, P.},\nbooktitle = {{SPIE Microlithography}},\ncategory = {C28},\nkeywords = {mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C28_paper.pdf},\ntitle = {Lithography {S}imulation-{B}ased {F}ull-{C}hip {D}esign {A}nalyses},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [C29]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c29.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, &#8220;Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis,&#8221; in <span style=\"font-style: italic\">SPIE Microlithography<\/span>,  2006  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_149\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_149_block\"><pre><code class=\"tex bibtex\">@inproceedings{C29,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S. and Sylvester, D.},\nbooktitle = {{SPIE Microlithography}},\ncategory = {C29},\nkeywords = {mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C2999999999_paper.pdf},\ntitle = {Modeling of {N}on-{U}niform {D}evice {G}eometries for {P}ost-{L}ithography {C}ircuit {A}nalysis},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [C31]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c31.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, &#8220;Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,&#8221; in <span style=\"font-style: italic\">SPIE Microlithography<\/span>,  2006  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_152\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_152_block\"><pre><code class=\"tex bibtex\">@inproceedings{C31,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},\nbooktitle = {{SPIE Microlithography}},\ncategory = {C31},\nkeywords = {mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C31_paper.pdf},\ntitle = {Self-{C}ompensating {D}esign for {R}eduction of {T}iming and {L}eakage {S}ensitivity to {S}ystematic {P}attern {D}ependent {V}ariation},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [C27]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c27.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta and A. B. Kahng, &#8220;Efficient Design and Analysis of Robust Power Distribution Meshes,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2006  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_147\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_147_block\"><pre><code class=\"tex bibtex\">@inproceedings{C27,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C27},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C27_paper.pdf},\ntitle = {Efficient {D}esign and {A}nalysis of {R}obust {P}ower {D}istribution {M}eshes},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [C30]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c30.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, S. V. Muddu, and N. S., &#8220;Modeling Edge Placement Error Distribution in Standard Cell Library,&#8221; in <span style=\"font-style: italic\">SPIE Microlithography<\/span>,  2006  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_151\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_151_block\"><pre><code class=\"tex bibtex\">@inproceedings{C30,\nauthor = {Gupta, P. and Kahng, A. B. and Muddu, S.V. and Nakagawa S.},\nbooktitle = {{SPIE Microlithography}},\ncategory = {C30},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C30_paper.pdf},\ntitle = {Modeling {E}dge {P}lacement {E}rror {D}istribution in {S}tandard {C}ell {L}ibrary},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [C24]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c24.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Enhanced Resist and Etch CD Control by Design Perturbation,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2005  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_144\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_144_block\"><pre><code class=\"tex bibtex\">@inproceedings{C24,\nauthor = {Gupta, P. and Kahng, A. B. and C.-H. Park},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\ncategory = {C24},\nkeywords = {mad},\nmonth = {October},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C24_paper.pdf},\ntitle = {Enhanced {R}esist and {E}tch {CD} {C}ontrol by {D}esign {P}erturbation},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C25]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c25.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, S. Muddu, O. S. Nakagawa, and C. -H. Park, &#8220;Modeling OPC Complexity for Design for Manufacturability,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2005  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_145\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_145_block\"><pre><code class=\"tex bibtex\">@inproceedings{C25,\nauthor = {Gupta, P. and Kahng, A. B. and Muddu,S. and Nakagawa, O.S. and Park, C.-H.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\ncategory = {C25},\nkeywords = {dats},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C25_paper.pdf},\ntitle = {Modeling {OPC} {C}omplexity for {D}esign for {M}anufacturability},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C23]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c23.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, &#8220;Self-Compensating Design for Focus Variation,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2005  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_143\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_143_block\"><pre><code class=\"tex bibtex\">@inproceedings{C23,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D. },\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C23},\nkeywords = {mad},\nmonth = {June},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C23_paper.pdf},\ntitle = {Self-{C}ompensating {D}esign for {F}ocus {V}ariation},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C26]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c26.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Zhang, R. Gray, O. S. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and C. Progler, &#8220;Interaction and Balance of Mask Write Time and Design RET Strategies,&#8221; in <span style=\"font-style: italic\">SPIE Photomask and NGL Mask Technology<\/span>,  2005  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_146\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_146_block\"><pre><code class=\"tex bibtex\">@inproceedings{C26,\nauthor = {Zhang, Y. and Gray, R. and Nakagawa, O.S. and Gupta, P. and Kamberian, H. and Xiao, G. and Cottle, R. and Progler, C.},\nbooktitle = {{SPIE Photomask and NGL Mask Technology}},\ncategory = {C26},\nkeywords = {dats},\nmonth = {April},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C26_paper.pdf},\ntitle = {Interaction and {B}alance of {M}ask {W}rite {T}ime and {D}esign {RET} {S}trategies},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c17.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Performance-Driven OPC for Mask Cost Reduction,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2005, pp. 270-275  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_136\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_136_block\"><pre><code class=\"tex bibtex\">@inproceedings{C17,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\ncategory = {C17},\nkeywords = {dats},\nmonth = {March},\npages = {270-275},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C17_paper.pdf},\ntitle = {Performance-{D}riven {OPC} for {M}ask {C}ost {R}eduction},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c18.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and P. Sharma, &#8220;A Practical Transistor-Level Threshold Voltage Assignment Methodology,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2005, pp. 261-265  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_137\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_137_block\"><pre><code class=\"tex bibtex\">@inproceedings{C18,\nauthor = {Gupta, P. and Kahng, A. B. and Sharma, P.},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\ncategory = {C18},\nkeywords = {sizing},\nmonth = {March},\npages = {261-265},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C18_paper.pdf},\ntitle = {A {P}ractical {T}ransistor-{L}evel {T}hreshold {V}oltage {A}ssignment {M}ethodology},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C20]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c20.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Manufacturing-Aware Design Methodology for Assist Feature Correctness,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2005  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_140\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_140_block\"><pre><code class=\"tex bibtex\">@inproceedings{C20,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H.},\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C20},\nkeywords = {mad},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C20_paper.pdf},\ntitle = {Manufacturing-{A}ware {D}esign {M}ethodology for {A}ssist {F}eature {C}orrectness},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C21]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c21.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, F. -L. Heng, and J. -F. Lee, &#8220;Toward Through-Process Layout Quality Metrics,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2005  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_141\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_141_block\"><pre><code class=\"tex bibtex\">@inproceedings{C21,\nauthor = {Gupta, P. and Heng, F.-L. and Lee, J.-F. },\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C21},\nkeywords = {mad},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C21_paper.pdf},\ntitle = {Toward {T}hrough-{P}rocess {L}ayout {Q}uality {M}etrics},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c19.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Detailed Placement for Improved Depth of Focus and CD Control,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2005  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_138\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_138_block\"><pre><code class=\"tex bibtex\">@inproceedings{C19,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C19},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C19_paper.pdf},\ntitle = {Detailed {P}lacement for {I}mproved {D}epth of {F}ocus and {CD} {C}ontrol},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C22]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c22.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, C. -H. Park, K. Samadi, and X. Xu, &#8220;Topography-Aware Optical Proximity Correction for Better DOF margin and CD Control,&#8221; in <span style=\"font-style: italic\">SPIE Photomask and NGL Mask Technology<\/span>,  2005  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_142\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_142_block\"><pre><code class=\"tex bibtex\">@inproceedings{C22,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Samadi, K. and Xu, X. },\nbooktitle = {{SPIE Photomask and NGL Mask Technology}},\ncategory = {C22},\nkeywords = {dats},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C22_paper.pdf},\ntitle = {Topography-{A}ware {O}ptical {P}roximity {C}orrection for {B}etter {DOF} margin and {CD} {C}ontrol},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [C14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta and F. -L. Heng, &#8220;Toward a Systematic-Variation Aware Timing Methodology,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2004  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_133\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_133_block\"><pre><code class=\"tex bibtex\">@inproceedings{C14,\nauthor = {Gupta, P. and Heng, F.-L.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C14},\nkeywords = {mad},\nmonth = {July},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C14_paper.pdf},\ntitle = {Toward a {S}ystematic-{V}ariation {A}ware {T}iming {M}ethodology},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [C15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, P. Sharma, and D. D. Sylvester, &#8220;Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Reduction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2004  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_134\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_134_block\"><pre><code class=\"tex bibtex\">@inproceedings{C15,\nauthor = {Gupta, P. and Kahng, A. B. and Sharma, P. and D. Sylvester, D.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C5},\nkeywords = {sizing, mad},\nmonth = {July},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C15_paper.pdf},\ntitle = {Selective {G}ate-{L}ength {B}iasing for {C}ost-{E}ffective {R}untime {L}eakage {R}eduction},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [C16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c16.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Toward a Methodology for Manufacturability Driven Design Rule Exploration,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2004  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_135\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_135_block\"><pre><code class=\"tex bibtex\">@inproceedings{C16,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C16},\nkeywords = {dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C16_paper.pdf},\ntitle = {Toward a {M}ethodology for {M}anufacturability {D}riven {D}esign {R}ule {E}xploration},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [C11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, F. -L. Heng, and M. Lavin, &#8220;Merits of Cellwise Model-Based OPC,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2004  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_100\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_100_block\"><pre><code class=\"tex bibtex\">@inproceedings{C11,\nauthor = {Gupta, P. and Heng, F.-L. and Lavin, M. },\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C11},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C11_paper.pdf},\ntitle = {Merits of {C}ellwise {M}odel-{B}ased {OPC}},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [C12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, F. -L. Heng, R. L. Gordon, K. Lai, and J. Lee, &#8220;Taming Focus Variation in VLSI Design,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2004  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_111\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_111_block\"><pre><code class=\"tex bibtex\">@inproceedings{C12,\nauthor = {Gupta, P. and Heng, F.-L. and Gordon, R.L. and Lai, K. and Lee, J. },\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C12},\nkeywords = {mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C12_paper.pdf},\ntitle = {Taming {F}ocus {V}ariation in {VLSI} {D}esign},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [C13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, &#8220;Investigation of Performance Metrics for Interconnect Stack Architectures,&#8221; in <span style=\"font-style: italic\">Proc. g SLIP<\/span>,  2004  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_122\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_122_block\"><pre><code class=\"tex bibtex\">@inproceedings{C13,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},\nbooktitle = {{Proc. g SLIP}},\ncategory = {C13},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C13_paper.pdf},\ntitle = {Investigation of {P}erformance {M}etrics for {I}nterconnect {S}tack {A}rchitectures},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [C10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and S. Mantik, &#8220;Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2004  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_89\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_89_block\"><pre><code class=\"tex bibtex\">@inproceedings{C10,\nauthor = {Gupta, P. and Kahng, A. B. and Mantik, S.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C2},\nkeywords = {},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C10_paper.pdf},\ntitle = {Wire {S}wizzling to {R}educe {D}elay {U}ncertainty {D}ue to {C}apacitive {C}oupling},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [C8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, I. I. Mandoiu, and P. Sharma, &#8220;Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2003, pp. 754-759  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_205\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_205_block\"><pre><code class=\"tex bibtex\">@inproceedings{C8,\nauthor = {Gupta, P. and Kahng, A. B. and Mandoiu, I.I. and Sharma, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C8},\nkeywords = {},\nmonth = {November},\npages = {754-759},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C8_paper.pdf},\ntitle = {Layout-{A}ware {S}can {C}hain {S}ynthesis for {I}mproved {P}ath {D}elay {F}ault {C}overage},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [C9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta and A. B. Kahng, &#8220;Manufacturing-Aware Physical Design,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2003, pp. 681-687  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_215\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_215_block\"><pre><code class=\"tex bibtex\">@inproceedings{C9,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C9},\ncomments = {embedded tutorial},\nkeyword = {mad},\nmonth = {November},\npages = {681-687},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C9_paper.pdf},\ntitle = {Manufacturing-{A}ware {P}hysical {D}esign},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [C6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Chen, P. Gupta, and A. B. Kahng, &#8220;Performance-Impact Limited Area Fill Synthesis,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2003  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_183\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_183_block\"><pre><code class=\"tex bibtex\">@inproceedings{C6,\nauthor = {Chen, Y. and Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C6},\nkeywords = {mad},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C6_paper.pdf},\ntitle = {Performance-{I}mpact {L}imited {A}rea {F}ill {S}ynthesis},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [C7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c7_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2003  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_194\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_194_block\"><pre><code class=\"tex bibtex\">@inproceedings{C7,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C7},\nkeywords = {sizing, dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C7_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C7_slides.pdf},\ntitle = {A {C}ost-{D}riven {L}ihographic {C}orrection {M}ethodology {B}ased on {O}ff-the-{S}helf {S}izing {T}ools},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [C4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta and A. B. Kahng, &#8220;Quantifying Error in Dynamic Power Estimation of CMOS Circuits,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2003, pp. 273-278  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_161\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_161_block\"><pre><code class=\"tex bibtex\">@inproceedings{C4,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\ncategory = {C4},\nkeywords = {},\nmonth = {March},\npages = {273-278},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C4_paper.pdf},\ntitle = {Quantifying {E}rror in {D}ynamic {P}ower {E}stimation of {CMOS} {C}ircuits},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [C5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>          <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c5_slides.ppt\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>            P. Gupta, A. B. Kahng, and S. Mantik, &#8220;A Proposal for Routing-Based Timing-Driven Scan Chain Ordering,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2003, pp. 339-343  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_172\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_172_block\"><pre><code class=\"tex bibtex\">@inproceedings{C5,\nauthor = {Gupta, P. and Kahng, A. B. and Mantik, S.},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\ncategory = {C5},\nkeywords = {},\nmonth = {March},\npages = {339-343},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C5_paper.pdf},\ntitle = {A {P}roposal for {R}outing-{B}ased {T}iming-{D}riven {S}can {C}hain {O}rdering},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [C3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c3_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            Y. Chen, P. Gupta, and A. B. Kahng, &#8220;Performance-Impact Limited Dummy Fill Insertion,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2003, pp. 857-862  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_150\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_150_block\"><pre><code class=\"tex bibtex\">@inproceedings{C3,\nauthor = {Chen, Y. and Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C3},\nkeywords = {mad},\nmonth = {February},\npages = {857-862},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C3_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C3_slides.pdf},\ntitle = {Performance-{I}mpact {L}imited {D}ummy {F}ill {I}nsertion},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [C2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c2_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            P. Gupta, A. B. Kahng, and S. Mantik, &#8220;Routing-Aware Scan Chain Ordering,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2003, pp. 857-862  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_139\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_139_block\"><pre><code class=\"tex bibtex\">@inproceedings{C2,\nauthor = {Gupta, P. and Kahng, A. B. and Mantik, S.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C2},\nkeywords = {},\nmonth = {January},\npages = {857-862},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C2_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C2_slides.pdf},\ntitle = {Routing-{A}ware {S}can {C}hain {O}rdering},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [C1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI,&#8221; in <span style=\"font-style: italic\">IEEE ASIC\/SoC Conference<\/span>,  2002, pp. 411-415  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_88\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_88_block\"><pre><code class=\"tex bibtex\">@inproceedings{C1,\nauthor = {Cao, Y. and Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{IEEE ASIC\/SoC Conference}},\ncategory = {C1},\nkeywords = {mad},\nmonth = {September},\npages = {411-415},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C1_paper.pdf},\ntitle = {Design {S}ensitivities to {V}ariability: {E}xtrapolation and {A}ssessments in {N}anometer {VLSI}},\nyear = {2002}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n\n<hr class=\"wp-block-separator is-style-wide\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Invited_Papers\"><\/span>Invited Papers<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip19.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Niemier, Z. Enciso, M. M. Sharifi, X. S. Hu, I. O&#8217;Conner, A. Graening, R. Sharma, P. Gupta, J. Castrillon, J. P. C. Lima, N. Afroze, A. Khan, and J. Ryckaert, &#8220;Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, &#038; Compilers,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2024, p. 10  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_236\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_236_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP19,\nauthor = {Niemier, Michael and Enciso, Zephan and Sharifi, Mohammed Mehdi and Hu, Xiaobo Sharon and O'Conner, Ian and Graening, Alexander and Sharma, Ravit and Gupta, Puneet and Castrillon, Jeronimo and Lima, J.P.C. and Afroze, Nashrah and Khan, Asif and Ryckaert, Julien},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {},\nkeywords = {chiplets,wsi},\nmonth = {March},\nnote = {},\npages = {10},\ntitle = {{Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip18.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Li and P. Gupta, &#8220;4F optical neural network acceleration: an architecture perspective,&#8221; in <span style=\"font-style: italic\">SPIE 12019, AI and Optical Data Sciences III<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_235\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_235_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP18,\nauthor = {Li, Shurui and Gupta, Puneet},\nbooktitle = {{{SPIE 12019, AI and Optical Data Sciences III}}},\nkeywords = {photonics},\ntitle = {{4F optical neural network acceleration: an architecture perspective}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip17.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal, S. S. Iyer, and P. Gupta, &#8220;Advanced packaging and heterogeneous integration to reboot computing,&#8221; in <span style=\"font-style: italic\">IEEE International Conference on Rebooting Computing<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_234\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_234_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP17,\nauthor = {Pal, Saptadeep and Iyer, Subramanian S. and Gupta, Puneet},\nbooktitle = {{IEEE International Conference on Rebooting Computing}},\nkeywords = {wsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP17_paper.pdf},\ntitle = {Advanced Packaging and Heterogeneous Integration to Reboot Computing},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    N. Dutt, P. Gupta, A. Nicolau, A. BanaiyanMofrad, M. Gottscho, and M. Shoushtari, &#8220;Multi-Layer Memory Resiliency,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_231\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_231_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP14,\nauthor = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and BanaiyanMofrad, Abbas and Gottscho, Mark and Shoushtari, Majid},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP14_paper.pdf},\ntitle = {{M}ulti-{L}ayer {M}emory {R}esiliency},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Lai and P. Gupta, &#8220;Accurate and inexpensive performance monitoring for variability-aware systems,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014, pp. 467-473  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_230\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_230_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP13,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {hsi},\nmonth = {Jan},\npages = {467-473},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP13_paper.pdf},\ntitle = {Accurate and inexpensive performance monitoring for variability-aware systems},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. S., N. Dutt, P. Gupta, A. Nicolau, and V. N., &#8220;On-Chip Self-Awareness Using Cyberphysical-Systems-On-Chip (CPSoC),&#8221; in <span style=\"font-style: italic\">ACM International Conference on Hardware\/Software Codesign and System Synthesis<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_232\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_232_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP15,\nauthor = {Sarma S. and Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and Venkatasubramanian N.},\nbooktitle = {{ACM International Conference on Hardware\/Software Codesign and System Synthesis}},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP15_paper.pdf},\ntitle = {{On-Chip Self-Awareness Using Cyberphysical-Systems-On-Chip (CPSoC)}},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip16.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, Y. Badr, and P. Gupta, &#8220;Pattern-restricted design at 10nm and beyond,&#8221; in <span style=\"font-style: italic\">Proc. IEEE International Conference on Computer Design<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_233\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_233_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP16,\nauthor = { Ghaida, Rani S. and Badr, Yasmine and Gupta, Puneet},\nbooktitle = {{Proc. IEEE International Conference on Computer Design}},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP16_paper.pdf},\ntitle = {Pattern-restricted design at 10nm and beyond},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    N. Dutt, P. Gupta, A. Nicolau, L. Bathen, and M. Gottscho, &#8220;Variability-Aware Memory Management for Nanoscale Computing,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_227\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_227_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP10,\nauthor = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and Bathen, Luis and Gottscho, Mark},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {hsi, variability, memory, dram, uno},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP10_paper.pdf},\ntitle = {{V}ariability-{A}ware {M}emory {M}anagement for {N}anoscale {C}omputing},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [9]                            R. S. Ghaida and P. Gupta, &#8220;Role of design in multiple patterning: technology development, design enablement and process control,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_228\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_228_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP11,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/mp_and_design_date13.pdf},\ntitle = {Role of Design in Multiple Patterning: Technology\nDevelopment, Design Enablement and Process Control},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [10]                            J. Henkel, L. Bauer, N. Dutt, P. Gupta, S. Nassif, M. Shafique, M. Tahoori, and N. Wehn, &#8220;Reliable on-chip systems in the nano-era: lessons learnt and future trends,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2013, p. 99:1\u201399:10  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_229\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_229_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP12,\nauthor = {Henkel, J\\\"{o}rg and Bauer, Lars and Dutt, Nikil and Gupta, Puneet and Nassif, Sani and Shafique, Muhammad and Tahoori, Mehdi and Wehn, Norbert},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {hsi},\npages = {99:1--99:10},\ntitle = {Reliable on-chip systems in the nano-era: lessons learnt and future trends},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/ip9_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, &#8220;O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,&#8221; in <span style=\"font-style: italic\">Intl. Conf. on IC Design and Technology<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_244\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_244_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP9,\nauthor = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},\nbooktitle = {{Intl. Conf. on IC Design and Technology}},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/ip9_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/ip9_slides.pdf},\ntitle = {O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [12]                            A. R. Neureuther, J. Rubinstein, M. Miller, Y. K. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T. -J. K. Liu, X. Sun, K. Jeong, P. and Gupta, A. A. Kagalwalla, R. S. Ghaida, and T. -B. Chan, &#8220;Collaborative research on emerging technologies and design,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Photomask and Next-Generation Lithography Mask Technology<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_242\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_242_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP7,\nauthor = {A.R. Neureuther and J. Rubinstein and M. Miller and K. Yamazoeand E. Chin and C. Levy and L. Wang and N. Xu and C. Spanos and K. Qian and K. Poolla and J. Ghan and A. Subramanian and T.-J. K. Liu and X. Sun and K. Jeong and and P. Gupta and Kagalwalla, Abde Ali and Ghaida, R. S. and T.-B. Chan},\nbooktitle = {{Proc. SPIE Photomask and Next-Generation Lithography Mask Technology}},\ncategory = {IP7},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/pmj11.pdf},\ntitle = {Collaborative research on emerging technologies and design},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [13]                            P. Gupta and R. Gupta, &#8220;Underdesigned and opportunistic computing,&#8221; in <span style=\"font-style: italic\">Proc. Asian Test Symposium<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_243\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_243_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP8,\nauthor = {P. Gupta and R. Gupta},\nbooktitle = {{Proc. Asian Test Symposium}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/uno_ats_v4.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/ats_11_v1.pdf},\ntitle = {Underdesigned and Opportunistic Computing},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/ip6_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, R. S. Ghaida, and P. Gupta, &#8220;Electrical Modeling of Lithographic Imperfections,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2010  &#8211; <b>Embedded Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_241\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_241_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP6,\nauthor = {Chan, T.-B. and Ghaida, R. S. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {IP6},\nkeywords = {mad},\nnote = {Embedded Tutorial},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP6_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP6_slides.pdf},\ntitle = {{E}lectrical {M}odeling of {L}ithographic {I}mperfections},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, O. S. Nakagawa, and K. Samadi, &#8220;Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing,&#8221; in <span style=\"font-style: italic\">Proc. 22nd Intl. VLSI\/ULSI Multilevel Interconnection (VMIC) Conf.<\/span>,  2005  &#8211; <b>Invited Paper<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_240\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_240_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP4,\nauthor = {Gupta, P. and Kahng, A. B. and Nakagawa, O.S. and Samadi, K.},\nbooktitle = {{Proc. 22nd Intl. VLSI\/ULSI Multilevel Interconnection (VMIC) Conf.}},\ncategory = {IP4},\nkeywords = {mad},\nmonth = {October},\nnote = {Invited Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP4_paper.pdf},\ntitle = {Closing the {L}oop in {I}nterconnect {A}nalyses and {O}ptimization: {CMP} {F}ill, {L}ithography and {T}iming},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Improving OPC Quality Via Interactions Within the Design-to-Manufacturing Flow,&#8221; in <span style=\"font-style: italic\">SPIE Photomask and NGL Mask Technology<\/span>,  2005  &#8211; <b>Invited Paper<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_239\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_239_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP3,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H.},\nbooktitle = {{SPIE Photomask and NGL Mask Technology}},\ncategory = {IP3},\nkeywords = {dats},\nmonth = {April},\nnote = {Invited Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP3_paper.pdf},\ntitle = {Improving {OPC} {Q}uality {V}ia {I}nteractions {W}ithin the {D}esign-to-{M}anufacturing {F}low},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, C. -H. Park, P. Sharma, D. Sylvester, and J. Yang, &#8220;Joining the Design and Mask Flows for Better and Cheaper Masks,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2004  &#8211; <b>Invited Paper<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_238\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_238_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP2,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Sharma, P. and Sylvester, D. and Yang, J.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\ncategory = {IP2},\nkeywords = {dats},\nmonth = {September},\nnote = {Invited Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP2_paper.pdf},\ntitle = {Joining the {D}esign and {M}ask {F}lows for {B}etter and {C}heaper {M}asks},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip1b.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta and A. B. Kahng, &#8220;Manufacturing-Aware Physical Design,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2003  &#8211; <b>Embedded Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_237\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_237_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP1b,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {IP1b},\nkeywords = {mad},\nmonth = {November},\nnote = {Embedded Tutorial},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP1b_paper.pdf},\ntitle = {Manufacturing-{A}ware {P}hysical {D}esign},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Toward Performance-Driven Reduction of the Cost of RET-based Lithography Control,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2003  &#8211; <b>Invited Paper<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_226\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_226_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP1,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {IP1},\nkeywords = {dats},\nmonth = {February},\nnote = {Invited Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP1_paper.pdf},\ntitle = {Toward {P}erformance-{D}riven {R}eduction of the {C}ost of {RET}-based {L}ithography {C}ontrol},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n\n<hr class=\"wp-block-separator is-style-wide\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Books_and_Book_Chapters\"><\/span>Books and Book Chapters<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p> <ul class=\"papercite_bibliography\">          [B3]                            I. Alam, L. Dolecek, and P. Gupta, &#8220;Lightweight software-defined error correction for memories,&#8221; in <span style=\"font-style: italic\">Dependable Embedded Systems<\/span>, Springer, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_247\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_247_block\"><pre><code class=\"tex bibtex\">@incollection{B3,\nauthor = {Alam, Irina and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{Dependable Embedded Systems}},\npublisher = {Springer},\ntitle = {Lightweight Software-Defined Error Correction for Memories},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [B2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/b2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Lee and P. Gupta, <span style=\"font-style: italic\">Discrete circuit optimization: library based gate sizing and threshold voltage assignment<\/span>, Now Publishers, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_246\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_246_block\"><pre><code class=\"tex bibtex\">@book{B2,\nauthor = {Lee, J. and Gupta, P.},\nisbn = {978-1-60198-542-2},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/B2_paper.pdf},\npublisher = {Now Publishers},\ntitle = {Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [B1]                            P. Gupta and E. Papadopoulou, &#8220;Yield analysis and optimization,&#8221; in <span style=\"font-style: italic\">The Handbook of Algorithms for VLSI Physical Design Automation<\/span>, CRC Press, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_245\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_245_block\"><pre><code class=\"tex bibtex\">@incollection{B1,\nauthor = {P. Gupta and E. Papadopoulou},\nbooktitle = {{The Handbook of Algorithms for VLSI Physical Design Automation}},\npublisher = {CRC Press},\ntitle = {Yield Analysis and Optimization},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>  <\/p>\n\n\n\n<hr class=\"wp-block-separator is-style-wide\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Invited_Talks_and_Tutorials\"><\/span>Invited Talks and Tutorials<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>   <ul class=\"papercite_bibliography\">          [ITT33]                            P. Gupta, &#8220;Yield Modeling for Hybrid Bonding,&#8221; in <span style=\"font-style: italic\">IEEE Hybrid Bonding Symposium<\/span>,  2025  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_274\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_274_block\"><pre><code class=\"tex bibtex\">@conference{ITT33,\nauthor = {Gupta, Puneet},\nbooktitle = {{IEEE Hybrid Bonding Symposium}},\ntitle = {{Yield Modeling for Hybrid Bonding}},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [ITT32]                            P. Gupta, &#8220;Photonic Fourier Convolutional Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">IEEE Photonics Conference<\/span>,  2023  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_273\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_273_block\"><pre><code class=\"tex bibtex\">@conference{ITT32,\nauthor = {Gupta, Puneet},\nbooktitle = {{{IEEE Photonics Conference}}},\ntitle = {{Photonic Fourier Convolutional Neural Network Acceleration}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [IT29]                            S. Li and P. Gupta, &#8220;4F Optical Neural Network Acceleration: An Architectural Perspective,&#8221; in <span style=\"font-style: italic\">SPIE Photonics West Conference (AI and Optical Data Sciences)<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_248\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_248_block\"><pre><code class=\"tex bibtex\">@conference{IT29,\nauthor = {Li, Shurui and Gupta, Puneet},\nbooktitle = {{SPIE Photonics West Conference (AI and Optical Data Sciences)}},\nkeywords = {photonics, optical neural network},\nmonth = {February},\ntitle = {{4F Optical Neural Network Acceleration: An Architectural Perspective}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [ITT30]                            P. Gupta, &#8220;Design Technology Co-Optimization for EUV (Keynote Talk),&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Advanced Patterning Solutions<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_271\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_271_block\"><pre><code class=\"tex bibtex\">@conference{ITT30,\nauthor = {Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Advanced Patterning Solutions}},\nkeywords = {dats},\ntitle = {{Design Technology Co-Optimization for EUV (Keynote Talk)}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [ITT31]                            P. Gupta, &#8220;Software-Defined Memory Error Correction,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Silicon Lifecycle Management (SLM)<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_272\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_272_block\"><pre><code class=\"tex bibtex\">@conference{ITT31,\nauthor = {Gupta, Puneet},\nbooktitle = {{{IEEE International Workshop on Silicon Lifecycle Management (SLM)}}},\ntitle = {{Software-Defined Memory Error Correction}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [ITT28]                            P. Gupta, &#8220;Pathfinding and Design of Large-Scale Chiplet-Based Systems,&#8221; in <span style=\"font-style: italic\">MEPTEC Road to Chiplets: Architecture Workshop<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_269\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_269_block\"><pre><code class=\"tex bibtex\">@conference{ITT28,\nauthor = {Gupta, Puneet},\nbooktitle = {{{MEPTEC Road to Chiplets: Architecture Workshop}}},\ntitle = {{Pathfinding and Design of Large-Scale Chiplet-Based Systems}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [ITT26]                            P. Gupta, &#8220;Design technology co-optimization for disruptive patterning schemes,&#8221; in <span style=\"font-style: italic\">China Semiconductor Technology International Conference (CSTIC)<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_267\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_267_block\"><pre><code class=\"tex bibtex\">@conference{ITT26,\nauthor = {P. Gupta},\nbooktitle = {{China Semiconductor Technology International Conference (CSTIC)}},\nkeywords = {dats},\ntitle = {Design Technology Co-optimization for Disruptive Patterning Schemes},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [ITT27]                            P. Gupta and J. A. Torres, &#8220;Understanding design-patterning interactions for euv and dsa,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2017  &#8211; <b>Short Course<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_268\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_268_block\"><pre><code class=\"tex bibtex\">@conference{ITT27,\nauthor = {P. Gupta and J.A. Torres},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nnote = {Short Course},\ntitle = {Understanding Design-Patterning Interactions for EUV and DSA},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [ITT20]                            P. Gupta and J. A. Torres, &#8220;Understanding design-patterning interactions for euv and dsa,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2016  &#8211; <b>Short Course<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_261\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_261_block\"><pre><code class=\"tex bibtex\">@conference{ITT20,\nauthor = {P. Gupta and J.A. Torres},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nnote = {Short Course},\ntitle = {Understanding Design-Patterning Interactions for EUV and DSA},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [ITT21]                            P. Gupta, &#8220;Advancing cmos usage for high reliability markets,&#8221; in <span style=\"font-style: italic\">International Reliability Physics Symposium<\/span>,  2016  &#8211; <b>Panel Discussion<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_262\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_262_block\"><pre><code class=\"tex bibtex\">@conference{ITT21,\nauthor = {P. Gupta},\nbooktitle = {{International Reliability Physics Symposium}},\nnote = {Panel Discussion},\ntitle = {Advancing CMOS Usage for High Reliability Markets},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [ITT23]                            P. Gupta, &#8220;Cross-layer reliability monitoring, margining and mitigation,&#8221; in <span style=\"font-style: italic\">Design Technology Coupling Workshop, Munich<\/span>,  2016  &#8211; <b>Keynote Speaker<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_264\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_264_block\"><pre><code class=\"tex bibtex\">@conference{ITT23,\nauthor = {P. Gupta},\nbooktitle = {{Design Technology Coupling Workshop, Munich}},\nnote = {Keynote Speaker},\ntitle = {Cross-Layer Reliability Monitoring, Margining and Mitigation},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [ITT24]                            P. Gupta, &#8220;Design-technology co-optimization applications for dsa and euv,&#8221; in <span style=\"font-style: italic\">Lithography Workshop<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_265\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_265_block\"><pre><code class=\"tex bibtex\">@conference{ITT24,\nauthor = {P. Gupta},\nbooktitle = {{Lithography Workshop}},\ntitle = {Design-Technology Co-optimization Applications for DSA and EUV},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [ITT19]                            P. Gupta, A. Mallik, and J. A. Torres, &#8220;Patterning beyond multiple patterning,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2015  &#8211; <b>Embedded tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_259\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_259_block\"><pre><code class=\"tex bibtex\">@conference{ITT19,\nauthor = {P. Gupta and A. Mallik and J.A. Torres},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {dats},\nnote = {Embedded tutorial},\ntitle = {Patterning beyond multiple patterning},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [ITT17]                            R. Puri, N. Charudhattan, S. Saha, S. Rangarajan, R. Rao, and P. Gupta, &#8220;Design of deep sub-micron cmos circuit and design methodologies for high performance microprocessors,&#8221; in <span style=\"font-style: italic\"> IEEE International Conference on VLSI Design<\/span>,  2013  &#8211; <b>Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_257\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_257_block\"><pre><code class=\"tex bibtex\">@conference{ITT17,\nauthor = {R. Puri and N. Charudhattan and S. Saha and S. Rangarajan and R. Rao and P. Gupta},\nbooktitle = {{ IEEE International Conference on VLSI Design}},\nkeywords = {mad},\nnote = {Tutorial},\ntitle = {Design of Deep Sub-Micron CMOS Circuit and Design Methodologies for High Performance Microprocessors},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [ITT18]                            P. Gupta, A. Mallik, and J. A. Torres, &#8220;Design-patterning interactions,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2013  &#8211; <b>Half-Day tutorial.<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_258\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_258_block\"><pre><code class=\"tex bibtex\">@conference{ITT18,\nauthor = {P. Gupta and A. Mallik and J.A. Torres},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nnote = {Half-Day tutorial.},\ntitle = {Design-Patterning Interactions},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [ITT22]                            M. Shafique, P. Gupta, H. Patel, and S. Garg, &#8220;Cross-layer reliability modeling and optimization for embedded systems under process variations,&#8221; in <span style=\"font-style: italic\">Embedded Systems Week (ESWeek)<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_263\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_263_block\"><pre><code class=\"tex bibtex\">@conference{ITT22,\nauthor = {M. Shafique and P. Gupta and H. Patel and S. Garg},\nbooktitle = {{Embedded Systems Week (ESWeek)}},\ntitle = {Cross-Layer Reliability Modeling and Optimization for Embedded Systems under Process Variations},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [ITT25]                            P. Gupta, &#8220;Design for nanoscale patterning,&#8221; in <span style=\"font-style: italic\">IEEE Custom Integrated Circuits Conference (CICC)<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_266\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_266_block\"><pre><code class=\"tex bibtex\">@conference{ITT25,\nauthor = {P. Gupta},\nbooktitle = {{IEEE Custom Integrated Circuits Conference (CICC)}},\ntitle = {Design for Nanoscale Patterning},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [ITT15]                            P. Gupta, &#8220;Design-assisted semiconductor manufacturing,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2012  &#8211; <b>Short tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_255\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_255_block\"><pre><code class=\"tex bibtex\">@conference{ITT15,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\nkeywords = {mad},\nnote = {Short tutorial},\ntitle = {Design-Assisted Semiconductor Manufacturing},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [ITT16]                            P. Gupta, &#8220;Measuring and monitoring variability,&#8221; in <span style=\"font-style: italic\">IEEE International On-Line Test Symposium<\/span>,  2012  &#8211; <b>Invited Talk<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_256\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_256_block\"><pre><code class=\"tex bibtex\">@conference{ITT16,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International On-Line Test Symposium}},\nkeywords = {hsi},\nnote = {Invited Talk},\ntitle = { Measuring and Monitoring Variability},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [ITT12]                            P. Gupta, &#8220;Underdesigned and opportunistic computing machines,&#8221; in <span style=\"font-style: italic\">Nanosystem Design and Variability Workshop, EPFL<\/span>,  2011  &#8211; <b>Invited Talk<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_252\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_252_block\"><pre><code class=\"tex bibtex\">@conference{ITT12,\nauthor = {Gupta, P.},\nbooktitle = {{Nanosystem Design and Variability Workshop, EPFL}},\nkeywords = {hsi},\nnote = {Invited Talk},\ntitle = {Underdesigned and Opportunistic Computing Machines},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [ITT13]                            P. Gupta, &#8220;Designing for uncertainty: addressing process variations and aging issues in vlsi designs,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on VLSI Design, Automation and Test<\/span>,  2011  &#8211; <b>Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_253\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_253_block\"><pre><code class=\"tex bibtex\">@conference{ITT13,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International Symposium on VLSI Design, Automation and Test}},\nkeywords = {mad, hsi},\nnote = {Tutorial},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/vlsidat_11.pdf},\ntitle = {Designing for Uncertainty: Addressing Process Variations and Aging Issues in VLSI Designs},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [ITT14]                            P. Gupta, &#8220;Variability and reliability: will they get better or worse in future cmos technologies ?,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Design for Reliability and Variability<\/span>,  2011  &#8211; <b>Panel Discussion<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_254\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_254_block\"><pre><code class=\"tex bibtex\">@conference{ITT14,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE Workshop on Design for Reliability and Variability}},\nkeywords = {mad},\nnote = {Panel Discussion},\ntitle = { Variability and Reliability: Will they Get Better or Worse in Future CMOS Technologies ?},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [ITT11]                            P. Gupta, &#8220;Modeling performance impact of variability,&#8221; in <span style=\"font-style: italic\">NSF\/SRC The International Variability Characterization Workshop<\/span>,  2010  &#8211; <b>Invited Talk<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_251\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_251_block\"><pre><code class=\"tex bibtex\">@conference{ITT11,\nauthor = {Gupta, P.},\nbooktitle = {{NSF\/SRC The International Variability Characterization Workshop}},\nkeywords = {mad},\nnote = {Invited Talk},\ntitle = {Modeling Performance Impact of Variability},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [ITT10]                            P. Gupta, &#8220;Revisiting variation models and their reliability,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Workshop on Variability Modeling and Characterization<\/span>,  2009  &#8211; <b>Invited talk<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_249\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_249_block\"><pre><code class=\"tex bibtex\">@conference{ITT10,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE\/ACM Workshop on Variability Modeling and Characterization}},\nkeywords = {mad},\nnote = {Invited talk},\ntitle = {Revisiting Variation Models and Their Reliability},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [ITT10a]                            P. Gupta, &#8220;Design for ultra-low-k1 patterning and manufacturing,&#8221; in <span style=\"font-style: italic\">IEEE International Conference on Microelectronic Teststructures (ICMTS)<\/span>,  2009  &#8211; <b>Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_250\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_250_block\"><pre><code class=\"tex bibtex\">@conference{ITT10a,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International Conference on Microelectronic Teststructures (ICMTS)}},\nkeywords = {mad},\nnote = {Tutorial},\ntitle = { Design for Ultra-low-k1 Patterning and Manufacturing},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [ITT9]                            P. Gupta, &#8220;Design and Use of Tweakable Devices for Future Logic Implementation,&#8221; in <span style=\"font-style: italic\">IEEE International Electron Devices Meeting<\/span>,  2008, pp. 1-1  &#8211; <b>Invited Talk<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_280\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_280_block\"><pre><code class=\"tex bibtex\">@conference{ITT9,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International Electron Devices Meeting}},\ncategory = {ITT9},\nkeywords = {},\nmonth = {December},\nnote = {Invited Talk},\npages = {1-1},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/iedm08.pdf},\ntitle = {Design and {U}se of {T}weakable {D}evices for {F}uture {L}ogic {I}mplementation},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [ITT5]                            P. Gupta, &#8220;The Electrical Design Manufacturing Interface,&#8221; in <span style=\"font-style: italic\">Electronic Design Processes Workshop<\/span>,  2008  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_276\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_276_block\"><pre><code class=\"tex bibtex\">@conference{ITT5,\nauthor = {Gupta, P.},\nbooktitle = {{Electronic Design Processes Workshop}},\ncategory = {ITT5},\nkeywords = {mad, dats},\ntitle = {The {E}lectrical {D}esign {M}anufacturing {I}nterface},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [ITT6]                            P. Gupta and C. Wu, &#8220;Lithography and Memories: From Shapes to Electrical,&#8221; in <span style=\"font-style: italic\">IEEE VLSI Test Symposium<\/span>,  2008  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_277\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_277_block\"><pre><code class=\"tex bibtex\">@conference{ITT6,\nauthor = {Gupta, P. and Wu, C.},\nbooktitle = {{IEEE VLSI Test Symposium}},\ncategory = {ITT6},\nkeywords = {mad},\ntitle = {Lithography and {M}emories: {F}rom {S}hapes to {E}lectrical},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [ITT7]                            D. Chidambarrao, P. Gupta, P. Elakkumanan, L. Liebmann, D. Marculescu, and N. Tamarapalli, &#8220;DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2008  &#8211; <b>Full-day Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_278\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_278_block\"><pre><code class=\"tex bibtex\">@conference{ITT7,\nauthor = {Chidambarrao, D. and Gupta, P. and Elakkumanan, P. and Liebmann, L. and Marculescu, D. and Tamarapalli, N.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {ITT7},\nkeywords = {mad},\nnote = {Full-day Tutorial},\ntitle = {{DFM} {R}evisited: {A} {C}omprehensive {A}nalysis of {V}ariability at all {L}evels of {A}bstraction},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [ITT8]                            P. Gupta, &#8220;Challenges at 45nm and Beyond,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2008  &#8211; <b>Panel Discussion<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_279\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_279_block\"><pre><code class=\"tex bibtex\">@conference{ITT8,\nauthor = {Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {ITT8},\nkeywords = {mad, dats},\nnote = {Panel Discussion},\ntitle = {Challenges at 45nm and {B}eyond},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [ITT4]                            P. Gupta and R. Puri, &#8220;Impact of Variability On VLSI Circuits,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2007  &#8211; <b>Short Course<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_275\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_275_block\"><pre><code class=\"tex bibtex\">@conference{ITT4,\nauthor = {Gupta, P. and Puri, R.},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\ncategory = {ITT4},\nkeywords = {mad},\nnote = {Short Course},\ntitle = {Impact Of {V}ariability {O}n {VLSI} {C}ircuits},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [ITT2]                            P. Gupta and A. B. Kahng, &#8220;CMP and DFM,&#8221; in <span style=\"font-style: italic\">CMP-MIC<\/span>,  2005  &#8211; <b>Short Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_260\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_260_block\"><pre><code class=\"tex bibtex\">@conference{ITT2,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{CMP-MIC}},\ncategory = {ITT2},\nkeywords = {mad},\nnote = {Short Tutorial},\ntitle = {{CMP} and {DFM}},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [ITT3]                            P. Gupta, &#8220;DFM Fundamentals,&#8221; in <span style=\"font-style: italic\">WesCon<\/span>,  2005  &#8211; <b>Short Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_270\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_270_block\"><pre><code class=\"tex bibtex\">@conference{ITT3,\nauthor = {Gupta, P.},\nbooktitle = {{WesCon}},\ncategory = {ITT3},\nkeywords = {mad},\nnote = {Short Tutorial},\ntitle = {{DFM} {F}undamentals},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>  <\/p>\n\n\n\n<hr class=\"wp-block-separator is-style-wide\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Patents\"><\/span>Patents<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>    <ul class=\"papercite_bibliography\">          [P18]                            P. Gupta, A. Pan, and S. Wang, <span style=\"font-style: italic\">Memory write and read assistance using negative differential resistance devices<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_290\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_290_block\"><pre><code class=\"tex bibtex\">@misc{P18,\nauthor = {P. Gupta and A. Pan and S. Wang},\nhowpublished = {U.S. Patent No. 10,832,752},\ntitle = {Memory write and read assistance using negative differential resistance devices},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [P17]                            P. Gupta and R. S. Ghaida, <span style=\"font-style: italic\">Single-mask double-patterning lithography<\/span>, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_289\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_289_block\"><pre><code class=\"tex bibtex\">@misc{P17,\nauthor = {P. Gupta and R.S. Ghaida},\nhowpublished = {U.S. Patent No. 8,415,089},\ntitle = {Single-mask double-patterning lithography},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [P16]                            A. B. Kahng, P. Gupta, D. Sylvester, and J. Yang, <span style=\"font-style: italic\">Tool for modifying mask design layout<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_288\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_288_block\"><pre><code class=\"tex bibtex\">@misc{P16,\nauthor = {A.B. Kahng and P. Gupta and D. Sylvester and J. Yang},\nhowpublished = {U.S. Patent No. 8,103,981},\ntitle = {Tool for modifying mask design layout},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [P14]                            A. B. Kahng, P. Gupta, and S. Shah, <span style=\"font-style: italic\">System and method for performing transistor-level static performance analysis using cell-level static analysis tools<\/span>, 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_286\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_286_block\"><pre><code class=\"tex bibtex\">@misc{P14,\nauthor = {A.B. Kahng and P. Gupta and S. Shah},\nhowpublished = {U.S. Patent No. 7,865,856},\ntitle = {System and method for performing transistor-level static performance analysis using cell-level static analysis tools},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [P15]                            P. Gupta, A. B. Kahng, P. Sharma, and S. Muddu, <span style=\"font-style: italic\">Method and system for wafer topography-aware integrated circuit design analysis and optimization<\/span>, 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_287\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_287_block\"><pre><code class=\"tex bibtex\">@misc{P15,\nauthor = {P. Gupta and A.B. Kahng and P. Sharma and S. Muddu},\nhowpublished = {U.S. Patent No. 8,024,675},\ntitle = {Method and system for wafer topography-aware integrated circuit design analysis and optimization},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [P10]                            P. Gupta and A. B. Kahng, <span style=\"font-style: italic\">Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_282\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_282_block\"><pre><code class=\"tex bibtex\">@misc{P10,\nauthor = {Gupta, P. and Kahng, A.B.},\nhowpublished = {US Patent No. 7,743,349},\ntitle = {Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit },\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [P11]                            O. S. Nakagawa, A. B. Kahng, P. Wong, and P. Gupta, <span style=\"font-style: italic\">Arrangement of fill unit elements in an integrated circuit interconnect layer<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_283\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_283_block\"><pre><code class=\"tex bibtex\">@misc{P11,\nauthor = {O. S. Nakagawa and A.B. Kahng and P. Wong and P. Gupta},\nhowpublished = {U.S. Patent No. 7,745,239},\ntitle = {Arrangement of fill unit elements in an integrated circuit interconnect layer},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [P12]                            C. W. Moon, P. Gupta, P. J. Donehue, and A. B. Kahng, <span style=\"font-style: italic\">Method of designing a digital circuit by correlating different static timing analyzers<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_284\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_284_block\"><pre><code class=\"tex bibtex\">@misc{P12,\nauthor = {C.W. Moon and P. Gupta and P.J. Donehue and A.B. Kahng},\nhowpublished = {U.S. Patent No. 7,823,098},\ntitle = {Method of designing a digital circuit by correlating different static timing analyzers},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [P13]                            P. Gupta and A. B. Kahng, <span style=\"font-style: italic\">Method and system for topography-aware reticle enhancement<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_285\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_285_block\"><pre><code class=\"tex bibtex\">@misc{P13,\nauthor = {P. Gupta and A.B. Kahng},\nhowpublished = {U.S. Patent No. 7,814,456},\ntitle = {Method and system for topography-aware reticle enhancement },\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [P8]                            P. Gupta, A. B. Kahng, and S. Shah, <span style=\"font-style: italic\">Method and system for integrated circuit optimization by using an optimized standard-cell library<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_297\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_297_block\"><pre><code class=\"tex bibtex\">@misc{P8,\nauthor = {Gupta, P. and Kahng, A.B. and Shah, S.},\nhowpublished = {US Patent No. 7,716,612},\ntitle = {Method and system for integrated circuit optimization by using an optimized standard-cell library },\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [P9]                            P. Gupta, A. B. Kahng, and D. Reed, <span style=\"font-style: italic\">Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objective<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_298\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_298_block\"><pre><code class=\"tex bibtex\">@misc{P9,\nauthor = {Gupta, P. and Kahng, A.B. and Reed, D.},\nhowpublished = {US Patent No. 7,730,432},\ntitle = {Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objective},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [P5]                            P. Gupta and A. B. Kahng, <span style=\"font-style: italic\">System and method for varying the starting conditions for a resolution enhancement program to improve the probability that design goals will be met<\/span>, 2009.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_294\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_294_block\"><pre><code class=\"tex bibtex\">@misc{P5,\nauthor = {Gupta, P. and Kahng, A.B.},\ncategory = {P5},\nhowpublished = {US Patent No. 7,627,849},\ntitle = {System and method for varying the starting conditions for a resolution enhancement program to improve the probability that design goals will be met},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [P6]                            P. Gupta, A. B. Kahng, and P. C.-H., <span style=\"font-style: italic\">Method and system for placing layout objects in a standard-cell layout<\/span>, 2009.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_295\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_295_block\"><pre><code class=\"tex bibtex\">@misc{P6,\nauthor = {Gupta, P. and Kahng, A.B. and Park C.-H.},\ncategory = {P6},\nhowpublished = {US Patent No. 7,640,522},\ntitle = {Method and system for placing layout objects in a standard-cell layout},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [P7]                            P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, <span style=\"font-style: italic\">Method for correcting a mask design layout<\/span>, 2009.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_296\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_296_block\"><pre><code class=\"tex bibtex\">@misc{P7,\nauthor = {Gupta, P. and Kahng, A.B. and Sylvester, D. and Yang, J.},\ncategory = {P7},\nhowpublished = {US Patent No. 7,614,032},\ntitle = {Method for correcting a mask design layout},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [P3]                            P. Gupta, F. -L. Heng, and M. Lavin, <span style=\"font-style: italic\">Method of IC Fabrication, IC Mask Fabrication and Program Product<\/span>, 2008.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_292\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_292_block\"><pre><code class=\"tex bibtex\">@misc{P3,\nauthor = {Gupta, P. and Heng, F.-L. and Lavin, M.},\ncategory = {P3},\nhowpublished = {US Patent No. 7,353,492},\ntitle = {Method of {IC} {F}abrication, {IC} {M}ask {F}abrication and {P}rogram {P}roduct},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [P4]                            P. Gupta and A. B. Kahng, <span style=\"font-style: italic\">Gate-Length Biasing for Digital Circuit Optimization<\/span>, 2008.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_293\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_293_block\"><pre><code class=\"tex bibtex\">@misc{P4,\nauthor = {Gupta, P. and Kahng, A.B.},\ncategory = {P4},\nhowpublished = {US Patent No. 7,441,211},\ntitle = {Gate-{L}ength {B}iasing for {D}igital {C}ircuit {O}ptimization},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [P1]                            P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, <span style=\"font-style: italic\">Method for Correcting a Mask Design Layout<\/span>, 2006.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_281\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_281_block\"><pre><code class=\"tex bibtex\">@misc{P1,\nauthor = {Gupta, P. and Kahng, A.B. and Sylvester, D. and Yang, J.},\ncategory = {P1},\nhowpublished = {US Patent No. 7,149,999},\ntitle = {Method for {C}orrecting a {M}ask {D}esign {L}ayout},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [P2]                            P. Gupta, F. -L. Heng, D. S. Kung, and D. Ostapko, <span style=\"font-style: italic\">Integrated Circuit Logic with Self Compensating Block Delays<\/span>, 2006.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_291\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_291_block\"><pre><code class=\"tex bibtex\">@misc{P2,\nauthor = {Gupta, P. and Heng, F.-L. and Kung, D.S. and Ostapko, D.},\ncategory = {P2},\nhowpublished = {US Patent No. 7,084,476},\ntitle = {Integrated {C}ircuit {L}ogic with {S}elf {C}ompensating {B}lock {D}elays},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n\n<hr class=\"wp-block-separator is-style-wide\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Workshops_No_Published_Proceedings\"><\/span>Workshops (No Published Proceedings)<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>     <ul class=\"papercite_bibliography\">          [W27]                    <a href='http:\/\/dx.doi.org\/10.1117\/12.2692958' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        H. Yang, N. Pesericoa, S. Li, B. F. Motlagh, J. S. Virdi, P. Gupta, V. J. Sorger, and C. W. Wong, &#8220;Enhancing and up-scaling of integrated photonic 4F convolution neural networks,&#8221; in <span style=\"font-style: italic\">Smart Photonic and Optoelectronic Integrated Circuits 2024<\/span>,  2024, p. 1289003  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_317\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_317_block\"><pre><code class=\"tex bibtex\">@conference{W27,\nauthor = {Hangbo Yang and Nicola Pesericoa and Shurui Li and Benyamin Fallahi Motlagh and Jaskirat Singh Virdi and Puneet Gupta and Volker J. Sorger and Chee Wei Wong},\nbooktitle = {{Smart Photonic and Optoelectronic Integrated Circuits 2024}},\ndoi = {10.1117\/12.2692958},\neditor = {Sailing He and Laurent Vivien},\nkeywords = {Machine Learning, Convolution Neural Network, Integrated Photonics},\norganization = {International Society for Optics and Photonics},\npages = {1289003},\npublisher = {SPIE},\ntitle = {{Enhancing and up-scaling of integrated photonic 4F convolution neural networks}},\nurl = {https:\/\/doi.org\/10.1117\/12.2692958},\nvolume = {12890},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [W28]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w28.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Z. Chen, A. H. Hassan, S. Pamarti, C. K. Yang, and P. Gupta, &#8220;An Analysis of Power and Performance Improvements from Low-Temperature Operation of Processors using PROCEED-LT,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2024  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_318\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_318_block\"><pre><code class=\"tex bibtex\">@conference{W28,\nauthor = {Chen, Zhichao and Hassan, Ali H. and Pamarti, Sudhakar and Yang, Chih-Kong Ken and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {},\ntitle = {{An Analysis of Power and Performance Improvements from Low-Temperature Operation of Processors using PROCEED-LT}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [W22]                            J. Yang, W. Romaszkan, A. Graening, V. K. Jacob, T. Li, P. Gupta, and S. Pamarti, &#8220;A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2023  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_313\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_313_block\"><pre><code class=\"tex bibtex\">@conference{W22,\nauthor = {Yang, Jiyue and Romaszkan, Wojciech and Graening, Alexander and Jacob, Vinod Kurian and Li, Tianmu and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, event-based camera, accelerator},\ntitle = {{A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [W23]                            T. Li, W. Romaszkan, S. Pal, S. Pamarti, and P. Gupta, &#8220;REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2023  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_314\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_314_block\"><pre><code class=\"tex bibtex\">@conference{W23,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pal, Soumitra and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, CNN, neural networks},\ntitle = {{REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [W21]                            A. Graening, W. Romaszkan, S. Pamarti, and P. Gupta, &#8220;Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_312\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_312_block\"><pre><code class=\"tex bibtex\">@conference{W21,\nauthor = {Graening, Alexander and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, event-based camera, accelerator},\ntitle = {{Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [W25]                            J. Yang, T. Li, W. Romaszkan, P. Gupta, and S. Pamarti, &#8220;A 1.84-7.96TOPS\/W 65nm DAC\/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_316\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_316_block\"><pre><code class=\"tex bibtex\">@conference{W25,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, CNN, neural networks, accelerator},\ntitle = {{A 1.84-7.96TOPS\/W 65nm DAC\/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [W18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w18.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Miscuglio, Z. Hu, S. Li, J. K. George, R. Capanna, H. Dalir, P. M. Bardet, P. Gupta, and V. J. Sorger, &#8220;Massively-parallel Amplitude-only Fourier Optical Convolutional Neural Network,&#8221; in <span style=\"font-style: italic\">Conference on Lasers and Electro-Optics (CLEO)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_308\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_308_block\"><pre><code class=\"tex bibtex\">@conference{W18,\nauthor = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and George, Jonathan K. and Capanna, Roberto and Dalir, Hamed and Bardet, Philippe M. and Gupta, Puneet and Sorger, Volker J.},\nbooktitle = {{Conference on Lasers and Electro-Optics (CLEO)}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/ieeexplore.ieee.org\/abstract\/document\/9572872},\ntitle = {{Massively-parallel Amplitude-only Fourier Optical Convolutional Neural Network}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [W19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w19.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Miscuglio, Z. Hu, S. Li, P. Gupta, H. Dalir, and V. J. Sorger, &#8220;Fourier Optical Convolutional Neural Network Accelerator,&#8221; in <span style=\"font-style: italic\">Signal Processing in Photonic Communications<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_309\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_309_block\"><pre><code class=\"tex bibtex\">@conference{W19,\nauthor = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and Gupta, Puneet and Dalir, Hamed and Sorger, Volker J.},\nbooktitle = {{Signal Processing in Photonic Communications}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/opg.optica.org\/abstract.cfm?uri=SPPCom-2021-SpM5C.2},\ntitle = {{Fourier Optical Convolutional Neural Network Accelerator}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [W20]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w20.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Z. Hu, M. Solyanik-Gorgone, S. Li, P. Gupta, and V. J. Sorger, &#8220;High Throughput Multi-kernel Fourier Optic Classifier,&#8221; in <span style=\"font-style: italic\">Frontiers in Optics<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_311\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_311_block\"><pre><code class=\"tex bibtex\">@conference{W20,\nauthor = {Hu, Zibo and Solyanik-Gorgone, Maria and Li, Shurui and Gupta, Puneet and Sorger, Volker J.},\nbooktitle = {{Frontiers in Optics}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/opg.optica.org\/abstract.cfm?uri=fio-2021-FTh4C.5},\ntitle = {{High Throughput Multi-kernel Fourier Optic Classifier}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [W24]                            W. Romaszkan, T. Li, J. Yang, A. Lee, D. Wu, K. Wang, S. Pamarti, and P. Gupta, &#8220;Machine Learning at the Edge Using Spintronic Stochastic Computing,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_315\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_315_block\"><pre><code class=\"tex bibtex\">@conference{W24,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Yang, Jiyue and Lee, Albert and Wu, Di and Wang, Kang and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, CNN, neural networks},\ntitle = {{Machine Learning at the Edge Using Spintronic Stochastic Computing}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [W16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w16.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Miscuglio, Z. Hu, S. Li, J. Gu, A. Babakhani, P. Gupta, C. Wong, D. Pan, S. Bank, H. Dalir, and V. J. Sorger, &#8220;Million-channel Parallelism Fourier-optic Convolutional Filter and Neural Network Processor,&#8221; in <span style=\"font-style: italic\">CLEO: Applications and Technology<\/span>,  2020  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_306\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_306_block\"><pre><code class=\"tex bibtex\">@conference{W16,\nauthor = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and Gu, Jiaqi and Babakhani, Aydin and Gupta, Puneet and Wong, Chee-Wei and Pan, David and Bank, Seth and Dalir, Hamed and Sorger, Volker J.},\nbooktitle = {{CLEO: Applications and Technology}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/opg.optica.org\/abstract.cfm?uri=cleo_at-2020-JF3A.4},\ntitle = {{Million-channel Parallelism Fourier-optic Convolutional Filter and Neural Network Processor}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [W17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w17.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Z. Hu, M. Miscuglio, S. Li, J. K. George, P. Gupta, and V. J. Sorger, &#8220;Electro-Optical Hybrid Fouirer Neural Network with Amplitude-Only Modulation,&#8221; in <span style=\"font-style: italic\">Frontiers in Optics<\/span>,  2020  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_307\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_307_block\"><pre><code class=\"tex bibtex\">@conference{W17,\nauthor = {Hu, Zibo and Miscuglio, Mario and Li, Shurui and George, Jonathan K. and Gupta, Puneet and Sorger, Volker J.},\nbooktitle = {{Frontiers in Optics}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/opg.optica.org\/abstract.cfm?uri=FiO-2020-FM7D.3},\ntitle = {{Electro-Optical Hybrid Fouirer Neural Network with Amplitude-Only Modulation}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [W14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Parity++: Lightweight Error Correction for Last Level Caches,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2018  &#8211; <b>Best of SELSE<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_304\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_304_block\"><pre><code class=\"tex bibtex\">@conference{W14,\nauthor = {Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {memres,parity,ecc,memory,reliability,architecture,coding,systems,caches},\nnote = {Best of SELSE},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W14_paper.pdf},\ntitle = {{Parity++: Lightweight Error Correction for Last Level Caches}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [W15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam, S. Pal, and P. Gupta, &#8220;Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_305\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_305_block\"><pre><code class=\"tex bibtex\">@conference{W15,\nauthor = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {memres,compression,ecc,memory,reliability,architecture,coding,systems,stt_ram},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W15_paper.pdf},\ntitle = {{Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [W13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/w13_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               M. Gottscho, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Software-Defined Error-Correcting Codes,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2016  &#8211; <b>Best Paper Award<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_303\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_303_block\"><pre><code class=\"tex bibtex\">@conference{W13,\nauthor = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {memres,hsi,ecc,memory,reliability,architecture,coding,systems,dram,caches},\nnote = {Best Paper Award},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_slides.pptx},\ntitle = {{Software-Defined Error-Correcting Codes}},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [W12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/w12_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               S. Wang, H. Hu, H. Zheng, and P. Gupta, &#8220;MEMRES: A Fast Memory System Reliability Simulator,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_302\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_302_block\"><pre><code class=\"tex bibtex\">@conference{W12,\nauthor = {Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {hsi, MEMRES, memory faults},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W12_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W12_slides.pptx},\ntitle = {{MEMRES: A Fast Memory System Reliability Simulator}},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [W11]                            R. S. Ghaida, M. Gupta, and P. Gupta, &#8220;A framework for exploring the interaction between design rules and overlay control,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_301\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_301_block\"><pre><code class=\"tex bibtex\">@conference{W11,\nauthor = {Ghaida, R. S. and Gupta, M. and Gupta, P.},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W11},\nkeywords = {dats, dre, design rules, overlay, alignment, process, multiple-patterning, lithography},\ntitle = {A Framework for Exploring the Interaction Between Design Rules and Overlay Control},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [W10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/w10_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            J. Lee and P. Gupta, &#8220;Parametric hierarchy recovery for layout extracted netlists,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_300\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_300_block\"><pre><code class=\"tex bibtex\">@conference{W10,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W10},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W10_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W10_slides.pdf},\ntitle = {Parametric Hierarchy Recovery for Layout Extracted Netlists},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [W5]                            L. Cheng and P. Gupta, &#8220;A Levelized Variation Modeling Scheme,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_321\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_321_block\"><pre><code class=\"tex bibtex\">@conference{W5,\nauthor = {Cheng, L. and Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W5},\nkeywords = {stat},\ntitle = {{A Levelized Variation Modeling Scheme}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [W6]                            A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, &#8220;Design-aware Mask Inspection,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_322\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_322_block\"><pre><code class=\"tex bibtex\">@conference{W6,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W6},\nkeywords = {dats},\ntitle = {{D}esign-aware {M}ask {I}nspection},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [W7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/w7_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            J. Lee and P. Gupta, &#8220;Incremental gate sizing for late process changes,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_323\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_323_block\"><pre><code class=\"tex bibtex\">@conference{W7,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W7},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W7_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W7_slides.pdf},\ntitle = {Incremental Gate Sizing for Late Process Changes},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [W8]                            V. Popuri, P. Gupta, and S. Pamarti, &#8220;Bias-Driven Robust Analog Circuit Sizing Scheme,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_324\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_324_block\"><pre><code class=\"tex bibtex\">@conference{W8,\nauthor = {Popuri, V. and Gupta, P. and Pamarti, S.},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W8},\nkeywords = {dats},\ntitle = {{Bias-Driven Robust Analog Circuit Sizing Scheme}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [W9]                            T. -B. Chan, A. Pant, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring,&#8221; in <span style=\"font-style: italic\">SRC TECHCON&#8217;10<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_325\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_325_block\"><pre><code class=\"tex bibtex\">@conference{W9,\nauthor = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\nbooktitle = {{SRC TECHCON'10}},\ncategory = {W9},\nkeywords = {stat},\ntitle = {{D}esign {Dependent} {P}rocess {M}onitoring},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [W1]                            R. S. Ghaida and P. Gupta, &#8220;A Framework for Systematic Evaluation and Exploration of Design Rules,&#8221; in <span style=\"font-style: italic\">SRC TECHCON&#8217;09<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_299\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_299_block\"><pre><code class=\"tex bibtex\">@conference{W1,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{SRC TECHCON'09}},\ncategory = {W1},\nkeywords = {dats},\nmonth = {},\npages = {},\ntitle = {A {F}ramework for {S}ystematic {E}valuation and {E}xploration of {D}esign {R}ules},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [W2]                            A. Pant, P. Gupta, and M. van der Schaar, &#8220;Software Adaptation to Handle Manufacturing Variability and Relax Hardware Overdesign,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_310\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_310_block\"><pre><code class=\"tex bibtex\">@conference{W2,\nauthor = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W2},\nkeywords = {hsi-p1},\ntitle = {{S}oftware {A}daptation to {H}andle {M}anufacturing {Variability} and {R}elax {H}ardware {O}verdesign},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [W3]                            J. Sartori, A. Pant, P. Gupta, and R. Kumar, &#8220;On Performance Binning of Multicore Processors,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_319\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_319_block\"><pre><code class=\"tex bibtex\">@conference{W3,\nauthor = {Sartori, John and Pant, Aashish and Gupta, Puneet and Kumar, Rakesh},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W3},\nkeywords = {hsi-p2},\ntitle = {{O}n {P}erformance {B}inning of {M}ulticore {P}rocessors},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [W4]                            T. -B. Chan, P. Gupta, V. Balakrishnan, and Y. Cao, &#8220;Extended Burn-in for Reduced Vth Variation,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_320\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_320_block\"><pre><code class=\"tex bibtex\">@conference{W4,\nauthor = {Chan, T.-B. and Gupta, Puneet and Balakrishnan, Varsha and Cao, Yu},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W4},\nkeywords = {dats},\ntitle = {{E}xtended {B}urn-in for {R}educed {V}th {V}ariation},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>  <\/p>\n","protected":false},"excerpt":{"rendered":"<p>Journals [J88] Z. Chen and P. Gupta, &#8220;YAP+: pad-layout-aware yield modeling and simulation for hybrid bonding,&#8221; IEEE Transactions on Computer-Aided Design of Integrated Circuits and&hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":56,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-84","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/84","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=84"}],"version-history":[{"count":12,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/84\/revisions"}],"predecessor-version":[{"id":875,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/84\/revisions\/875"}],"up":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/56"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=84"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}