![\"\"](\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2020\/01\/self-2.jpg\")
<\/figure><\/div>\n\n\n\nProfessor,Vice-Chair, Computer Engineering<\/a>,
Electrical and Computer Engineering Department<\/a>, UCLA
\n Lab <\/strong>: NanoCAD Lab<\/a>
\nGoogle Scholar Profile<\/strong><\/a>
\nLinkedIn Profile<\/strong><\/a>
\n\n\n\n
Contact Info<\/h4>\n\n\n\n Office <\/strong> 6730C Boelter Hall, UCLA
\nEmail<\/strong>: puneetg at ucla dot edu
\nPhone<\/strong>: 310-825-1376
\n\n\n\nEducation<\/h4>\n\n\n\n- B. Tech, Electrical Engineering, Indian Institute of Technology, New Delhi, 2000.<\/li>
- Ph.D., Computer Engineering, University of California, San Diego. Thesis: “On Compensation of Systematic Manufacturing Variations in Physical Design”, 2007<\/li><\/ul>\n\n\n\n
Experience<\/h4>\n\n\n\n- VLSI Designer, Mindtree Technologies. 2000-2001.<\/li>
- Co-founder and Product Architect, Blaze DFM. 2004-2007. <\/li>
- Assistant Professor, EE Department, UCLA. 2007-2013<\/li>
- Associate Professor, EE Department, UCLA. 2013-2018<\/li>
- Professor, ECE Department, UCLA. 2018-present<\/li>
- Vice-chair, Computer Engineering, 2017-present<\/li><\/ul>\n\n\n\n
Professional Service<\/h4>\n\n\n\n- Program Co-Chair, IEEE SELSE Workshop, 2019<\/li>
- Associate Editor, IEEE Transactions on CAD, 2014-2018<\/li>
- Local Organization Chair, ISLPED, 2012<\/li>
- Program Chair: IEEE DFM&Y Workshop 2009-2011<\/li>
- Editor, IETE Technical Review, 2009-2010<\/li>
- Vice-Chair, ACM\/SIGDA CADathlon at ICCAD 2007<\/li>
- Technical program committee member (various years): DAC, ICCAD, ASPDAC, CASES, ISLPED, ICCD, ISQED, VLSI Design<\/li><\/ul>\n\n\n\n
Research interests (see publications here<\/a>)<\/h4>\n\n\n\n- Design-technology co-optimization<\/li>
- Variability and reliability-aware computer architecture<\/li>
- Electronic design automation<\/li>
- Technology-enabled machine learning systems<\/li><\/ul>\n\n\n\n
Current major projects <\/h4>\n\n\n\n- Packageless waferscale processing<\/a>. Supported by CHIPS <\/a>and CDEN <\/a>centers and Qualcomm Innovation Fellowship.<\/li>
- Machine learning at the edge using stochastic computing<\/a>. Supported by DARPA.<\/li><\/ul>\n\n\n\n
Honors and Awards<\/h4>\n\n\n\n- Qualcomm Innovation Fellowship: 2016, 2019.<\/li>
- Best paper nominations: DATE 2016<\/li>
- Best paper awards: SELSE 2016, CASES 2017, SELSE 2018, DATE 2012 (IP)<\/li>
- IBM Faculty Award, 2012<\/li>
- ACM\/SIGDA Outstanding New Faculty Award, 2010<\/li>
- SRC Inventor Recognition Award, 2009, 2010<\/li>
- \u000fNational Science Foundation (NSF) CAREER Award, 2009<\/li>
- European Design Automation Association (EDAA) outstanding dissertation award, 2008.<\/li>
- IBM Ph.D. Fellowship, 2004. <\/li><\/ul>\n\n\n\n
Teaching<\/h4>\n\n\n\n- ECE10: Circuit Theory I<\/li>
- ECE110: Circuit Theory II<\/li>
- ECEM116C: Computer Systems Architecture<\/li>
- ECE201A: VLSI Design Automation<\/li>
- ECE201D: Design in Nanoscale Technologies<\/li><\/ul>\n\n\n\n
Advice to prospective applicants to NanoCAD Lab<\/h4>\n\n\n\n- Undergraduate:<\/em> Junior and senior years are the best times to approach me for research. CE or CSE majors are preferred. You should have taken CS 31, CS32, ECEM16 and and done well in them. CS33, ECEM116C, ECE115C and ECEM146 are a plus. I require minimum of two consecutive quarter commitment. You will be engaged in open-ended research, so motivation and willingness to commit time is essential.<\/li>
- M.S.<\/em>: Please only approach me if you intend to do a M.S. thesis.<\/li>
- Ph.D.<\/em>: If you like work which regularly crosses disciplinary boundaries (devices, digital circuits, architectures, algorithms, machine learning) within ECE\/CSE, contact me before you apply to UCLA. All students in my group would end up working on multiple projects at any given time and we value intellectual breadth as much as depth.<\/li><\/ul>\n","protected":false},"excerpt":{"rendered":"
Professor, Vice-Chair, Computer Engineering, Electrical and Computer Engineering Department, UCLA Lab : NanoCAD Lab Google Scholar Profile LinkedIn Profile Contact Info Office 6730C Boelter Hall,…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-381","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/381","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=381"}],"version-history":[{"count":30,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/381\/revisions"}],"predecessor-version":[{"id":417,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/381\/revisions\/417"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=381"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
- B. Tech, Electrical Engineering, Indian Institute of Technology, New Delhi, 2000.<\/li>
- Ph.D., Computer Engineering, University of California, San Diego. Thesis: “On Compensation of Systematic Manufacturing Variations in Physical Design”, 2007<\/li><\/ul>\n\n\n\n
Experience<\/h4>\n\n\n\n
- VLSI Designer, Mindtree Technologies. 2000-2001.<\/li>
- Co-founder and Product Architect, Blaze DFM. 2004-2007. <\/li>
- Assistant Professor, EE Department, UCLA. 2007-2013<\/li>
- Associate Professor, EE Department, UCLA. 2013-2018<\/li>
- Professor, ECE Department, UCLA. 2018-present<\/li>
- Vice-chair, Computer Engineering, 2017-present<\/li><\/ul>\n\n\n\n
Professional Service<\/h4>\n\n\n\n
- Program Co-Chair, IEEE SELSE Workshop, 2019<\/li>
- Associate Editor, IEEE Transactions on CAD, 2014-2018<\/li>
- Local Organization Chair, ISLPED, 2012<\/li>
- Program Chair: IEEE DFM&Y Workshop 2009-2011<\/li>
- Editor, IETE Technical Review, 2009-2010<\/li>
- Vice-Chair, ACM\/SIGDA CADathlon at ICCAD 2007<\/li>
- Technical program committee member (various years): DAC, ICCAD, ASPDAC, CASES, ISLPED, ICCD, ISQED, VLSI Design<\/li><\/ul>\n\n\n\n
Research interests (see publications here<\/a>)<\/h4>\n\n\n\n
- Design-technology co-optimization<\/li>
- Variability and reliability-aware computer architecture<\/li>
- Electronic design automation<\/li>
- Technology-enabled machine learning systems<\/li><\/ul>\n\n\n\n
Current major projects <\/h4>\n\n\n\n
- Packageless waferscale processing<\/a>. Supported by CHIPS <\/a>and CDEN <\/a>centers and Qualcomm Innovation Fellowship.<\/li>
- Machine learning at the edge using stochastic computing<\/a>. Supported by DARPA.<\/li><\/ul>\n\n\n\n
Honors and Awards<\/h4>\n\n\n\n
- Qualcomm Innovation Fellowship: 2016, 2019.<\/li>
- Best paper nominations: DATE 2016<\/li>
- Best paper awards: SELSE 2016, CASES 2017, SELSE 2018, DATE 2012 (IP)<\/li>
- IBM Faculty Award, 2012<\/li>
- ACM\/SIGDA Outstanding New Faculty Award, 2010<\/li>
- SRC Inventor Recognition Award, 2009, 2010<\/li>
- \u000fNational Science Foundation (NSF) CAREER Award, 2009<\/li>
- European Design Automation Association (EDAA) outstanding dissertation award, 2008.<\/li>
- IBM Ph.D. Fellowship, 2004. <\/li><\/ul>\n\n\n\n
Teaching<\/h4>\n\n\n\n
- ECE10: Circuit Theory I<\/li>
- ECE110: Circuit Theory II<\/li>
- ECEM116C: Computer Systems Architecture<\/li>
- ECE201A: VLSI Design Automation<\/li>
- ECE201D: Design in Nanoscale Technologies<\/li><\/ul>\n\n\n\n
Advice to prospective applicants to NanoCAD Lab<\/h4>\n\n\n\n
- Undergraduate:<\/em> Junior and senior years are the best times to approach me for research. CE or CSE majors are preferred. You should have taken CS 31, CS32, ECEM16 and and done well in them. CS33, ECEM116C, ECE115C and ECEM146 are a plus. I require minimum of two consecutive quarter commitment. You will be engaged in open-ended research, so motivation and willingness to commit time is essential.<\/li>
- M.S.<\/em>: Please only approach me if you intend to do a M.S. thesis.<\/li>
- Ph.D.<\/em>: If you like work which regularly crosses disciplinary boundaries (devices, digital circuits, architectures, algorithms, machine learning) within ECE\/CSE, contact me before you apply to UCLA. All students in my group would end up working on multiple projects at any given time and we value intellectual breadth as much as depth.<\/li><\/ul>\n","protected":false},"excerpt":{"rendered":"
Professor, Vice-Chair, Computer Engineering, Electrical and Computer Engineering Department, UCLA Lab : NanoCAD Lab Google Scholar Profile LinkedIn Profile Contact Info Office 6730C Boelter Hall,…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-381","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/381","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=381"}],"version-history":[{"count":30,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/381\/revisions"}],"predecessor-version":[{"id":417,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/381\/revisions\/417"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=381"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
- M.S.<\/em>: Please only approach me if you intend to do a M.S. thesis.<\/li>
- Undergraduate:<\/em> Junior and senior years are the best times to approach me for research. CE or CSE majors are preferred. You should have taken CS 31, CS32, ECEM16 and and done well in them. CS33, ECEM116C, ECE115C and ECEM146 are a plus. I require minimum of two consecutive quarter commitment. You will be engaged in open-ended research, so motivation and willingness to commit time is essential.<\/li>
- Machine learning at the edge using stochastic computing<\/a>. Supported by DARPA.<\/li><\/ul>\n\n\n\n
- Packageless waferscale processing<\/a>. Supported by CHIPS <\/a>and CDEN <\/a>centers and Qualcomm Innovation Fellowship.<\/li>