{"id":266,"date":"2019-10-08T23:45:52","date_gmt":"2019-10-08T23:45:52","guid":{"rendered":"http:\/\/nanocad.ee.ucla.edu\/?page_id=266"},"modified":"2025-10-22T17:57:43","modified_gmt":"2025-10-22T17:57:43","slug":"machine-learning-at-the-edge","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=266","title":{"rendered":"Machine Learning at the Edge"},"content":{"rendered":"\n<div class=\"wp-block-image\"><figure class=\"aligncenter size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2021\/04\/ml_edge.png\" alt=\"\" class=\"wp-image-884\" width=\"405\" height=\"373\"\/><\/figure><\/div>\n\n\n\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=266\/#Stochastic_Spintronic_Dataflow_Computing\" >Stochastic Spintronic Dataflow Computing<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=266\/#SWIS_%E2%80%93_Shared_Weight_bIt-Sparsity_Quantization\" >SWIS &#8211; Shared Weight bIt-Sparsity Quantization<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=266\/#3PXNet_Pruned-Permuted-Packed_XNOR_Networks\" >3PXNet: Pruned-Permuted-Packed XNOR Networks<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=266\/#Publications\" >Publications<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"has-text-align-center wp-block-heading\"><span class=\"ez-toc-section\" id=\"Stochastic_Spintronic_Dataflow_Computing\"><\/span>Stochastic Spintronic Dataflow Computing<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<div class=\"wp-block-media-text alignwide has-media-on-the-right is-stacked-on-mobile\" style=\"grid-template-columns:auto 35%\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"1047\" height=\"630\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2021\/04\/sc_diag.png\" alt=\"\" class=\"wp-image-885\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-text-align-left\"><strong>Students: Tianmu Li, Wojciech Romaszkan<\/strong><\/p>\n\n\n\n<p>The SSDC project is a collaborative effort between three faculty of the UCLA Electrical and Computer Engineering department \u2013 <a href=\"https:\/\/www.ee.ucla.edu\/kang-wang\/\">Prof. Kang L. Wang<\/a> (Device Research Laboratory), <a href=\"http:\/\/www.seas.ucla.edu\/~puneet\/\">Prof. Puneet Gupta<\/a> (<a href=\"http:\/\/nanocad.ee.ucla.edu\">NanoCAD Laboratory<\/a>), and <a href=\"https:\/\/www.ee.ucla.edu\/sudhakar-pamarti\/\">Prof. Sudhakar Pamarti <\/a>(<a href=\"http:\/\/www.seas.ucla.edu\/spgroup\/\">Signal Processing &amp; Circuit Engineering Laboratory<\/a>) \u2013  who  are  experts  in  nanotechnology,  computing  systems, design automation, and integrated circuit design. Led  by  Prof.  Sudhakar  Pamarti,  it  brings  together  spin-based voltage-controlled magnetic memory technology (MeRAM) and an unconventional stochastic computing (SC)   paradigm   to   resolve   the   dreaded   \u201cmemory   bottleneck\u201d   problem.   The   memory   bottleneck   represents  the  limited  bandwidth  and  high  energy  cost  of  moving  data  between  the  processing  and memory units and is arguably the most important challenge confronting modern computing systems, especially in big data applications.<\/p>\n<\/div><\/div>\n\n\n\n<div class=\"wp-block-media-text alignwide is-stacked-on-mobile\" style=\"grid-template-columns:37% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"2343\" height=\"2713\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2021\/04\/acoustic_block.png\" alt=\"\" class=\"wp-image-887\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p>The SC employs a stochastic alternative to traditional number representation (using long random binary bit streams instead of fixed- or floating-point) to enable ultra compact processing hardware. The MeRAM, developed by Prof. Kang Wang\u2019s group exploits the voltage controlled magnetic anisotropy property to achieve the best reported combination of energy, speed, and density among existing and emerging non-volatile memory technologies.<br>The combination of ultra-compact SC hardware and the dense, non-volatile MeRAM integrated on the same Silicon die offers great energy and latency improvements. The SSDC project aims to demonstrate up to 60x energy reduction for example data intensive machine learning tasks.<br>This project is funded by the FRANC (Foundations Required for Novel Compute) program within DARPA\u2019s Electronics Resurgence Initiative (ERI) aimed at solving fundamental challenges confronting the growth of microelectronics long after Moore\u2019s law is over.<\/p>\n\n\n\n<p>Collaborators: <a href=\"http:\/\/www.seas.ucla.edu\/spgroup\/\">Professor Sudhakar Pamarti<\/a> (UCLA), <a href=\"http:\/\/drl.ee.ucla.edu\/\">Professor Kang L. Wang<\/a> (UCLA)<\/p>\n<\/div><\/div>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"has-text-align-center wp-block-heading\"><span class=\"ez-toc-section\" id=\"SWIS_%E2%80%93_Shared_Weight_bIt-Sparsity_Quantization\"><\/span>SWIS &#8211; Shared Weight bIt-Sparsity Quantization<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<div class=\"wp-block-media-text alignwide has-media-on-the-right is-stacked-on-mobile\" style=\"grid-template-columns:auto 38%\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"962\" height=\"437\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2021\/04\/swis_fig.png\" alt=\"\" class=\"wp-image-889\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p><strong>Students: Shurui Li, Wojciech Romaszkan, Alexander Graening<\/strong><\/p>\n\n\n\n<p class=\"has-normal-font-size\">Quantization is spearheading the increase in performance and efficiency of neural network computing systems, making headway into commodity hardware. SWIS (Shared Weight bItSparsity), is a quantization framework for efficient neural network inference acceleration delivering improved performance and storage compression through an offline weight decomposition and scheduling algorithm. SWIS can achieve up to 54.3% (19.8%) point accuracy improvement compared to weight truncation when quantizing MobileNet-v2 to 4 (2) bits post-training (with retraining) showing the strength of leveraging shared bit-sparsity in weights. SWIS accelerator gives up to 6\u00d7speedup and 1.9\u00d7energy improvement overstate of the art bit-serial architectures.<\/p>\n<\/div><\/div>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"has-text-align-center wp-block-heading\"><span class=\"ez-toc-section\" id=\"3PXNet_Pruned-Permuted-Packed_XNOR_Networks\"><\/span>3PXNet: Pruned-Permuted-Packed XNOR Networks <a href=\"https:\/\/github.com\/nanocad-lab\/3pxnet\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-github-4.svg\"><\/a> <span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<div class=\"wp-block-media-text alignwide is-stacked-on-mobile\" style=\"grid-template-columns:38% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"2217\" height=\"1762\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2021\/04\/3pxnet_algo.png\" alt=\"\" class=\"wp-image-891\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p><strong>Students: Tianmu Li, Wojciech Romaszkan<\/strong><\/p>\n\n\n\n<p>As the adoption of Neural Networks continues to proliferate different classes of applications and systems, edge devices have been left behind. Their strict energy and storage limitations make them unable to cope with the enormous sizes of commonly used models. While many compression methods, such as precision reduction and sparsity, have been proposed to alleviate this, they do not go quite far enough. To push size reduction to its absolute limits, we combine binarization with sparsity in Pruned-Permuted-Packed XNOR Networks (3PXNet), which can be efficiently implemented on even the smallest of embedded microcontrollers. 3PXNets can reduce model sizes by up to 38X and reduce runtime by up to 3X, compared with already compact conventional binarized implementations with less than 3% accuracy reduction. 3PXNet is released as an open-source library targeting edge devices. The library is complete with training methodology and model generating scripts, making it easy and fast to deploy.<\/p>\n\n\n\n<p>3PXNet is available at: <a href=\"https:\/\/github.com\/nanocad-lab\/3pxnet\">https:\/\/github.com\/nanocad-lab\/3pxnet<\/a><\/p>\n<\/div><\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Publications\"><\/span>Publications<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c121.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Yang, T. Li, W. Romaszkan, P. Gupta, and S. Pamarti, &#8220;A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor,&#8221; in <span style=\"font-style: italic\">IEEE Asian Solid-State Circuits Conference<\/span>,  2022, p. 2  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_5\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_5_block\"><pre><code class=\"tex bibtex\">@inproceedings{C121,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{IEEE Asian Solid-State Circuits Conference}},\ndoi = {},\nkeywords = {mledge},\nmonth = {November},\nnote = {},\npages = {2},\ntitle = {{A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c120.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           W. Romaszkan, T. Li, and P. Gupta, &#8220;SASCHA &#8211; Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2022, p. 12  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_4\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_4_block\"><pre><code class=\"tex bibtex\">@inproceedings{C120,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {October},\nnote = {Best paper nomination},\npages = {12},\ntitle = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j72.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           W. Romaszkan, T. Li, and P. Gupta, &#8220;SASCHA &#8211; Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,&#8221; , p. 12, 2022.  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_9\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_9_block\"><pre><code class=\"tex bibtex\">@article{J72,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {October},\nnote = {Best paper nomination},\npages = {12},\ntitle = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c119.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Li and P. Gupta, &#8220;Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors,&#8221; in <span style=\"font-style: italic\">Conference on Machine Learning and Systems (MLSys)<\/span>,  2022, p. 10  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_3\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_3_block\"><pre><code class=\"tex bibtex\">@inproceedings{C119,\nauthor = {Li, Shurui and Gupta, Puneet},\nbooktitle = {{Conference on Machine Learning and Systems (MLSys)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {August},\nnote = {},\npages = {10},\ntitle = {{Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j70.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           W. Romaszkan, T. Li, R. Garg, J. Yang, S. Pamarti, and P. Gupta, &#8221; A 4.4-75 TOPS\/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator,&#8221; <span style=\"font-style: italic\">IEEE Solid State Circuits Letters<\/span>, 2022.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_8\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_8_block\"><pre><code class=\"tex bibtex\">@article{J70,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Garg, Rahul and Yang, Jiyue and Pamarti, Sudhakar and Gupta, Puneet},\njournal = {{IEEE Solid State Circuits Letters}},\nkeywords = {mledge},\nmonth = {August},\npublisher = {{IEEE}},\ntitle = {{ A 4.4-75 TOPS\/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c113.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Li, W. Romaszkan, A. Graening, and P. Gupta, &#8220;SWIS &#8211; Shared Weight bIt Sparsity for Efficient Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">International Research Symposium on Tiny Machine Learning (tinyML)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_2\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_2_block\"><pre><code class=\"tex bibtex\">@inproceedings{C113,\nauthor = {Li, Shurui and Romaszkan, Wojciech and Graening, Alexander and Gupta, Puneet},\nbooktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},\ndoi = {},\nkeywords = {mledge, quantization, systolic array},\nmonth = {March},\nnote = {},\npages = {},\ntitle = {{SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c112.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. Li, W. Romaszkan, S. Pamarti, and P. Gupta, &#8220;GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_1\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_1_block\"><pre><code class=\"tex bibtex\">@inproceedings{C112,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {},\nkeywords = {mledge},\nmonth = {February},\nnote = {},\npages = {},\ntitle = {{GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c109.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>   <a href='http:\/\/dx.doi.org\/10.23919\/DATE48585.2020.9116289' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        W. Romaszkan, T. Li, T. Melton, S. Pamarti, and P. Gupta, &#8220;ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2020, pp. 768-773  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_0\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_0_block\"><pre><code class=\"tex bibtex\">@inproceedings{C109,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Melton, Tristan and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {10.23919\/DATE48585.2020.9116289},\nkeywords = {mledge},\nmonth = {March},\nnote = {Best paper nomination},\npages = {768-773},\ntitle = {{ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j63.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           W. Romaszkan, T. Li, and P. Gupta, &#8220;3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning,&#8221; <span style=\"font-style: italic\">ACM Transactions on Embedded Computing Systems (TECS)<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_7\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_7_block\"><pre><code class=\"tex bibtex\">@article{J63,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\njournal = {{ACM Transactions on Embedded Computing Systems (TECS)}},\nkeywords = {mledge, 3pxnet},\nmonth = {November},\npublisher = {ACM},\ntitle = {{3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c95.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Wang, S. Pal, T. Li, A. Pan, C. Grezes, K. P. Amiri, K. L. Wang, C. O. Chui, and P. Gupta, &#8220;Hybrid VC-MTJ\/CMOS Non-volatile Stochastic Logic for Efficient Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2017  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_6\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_6_block\"><pre><code class=\"tex bibtex\">@inproceedings{C95,\nauthor = {Wang, Shaodi and Pal, Saptadeep and Li, Tianmu and Pan, Andrew and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Chui, Chi On and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nkeywords = {mledge,Negative differential resistance, Magnetic tunnel junction, stochastic computing, stochastic bitstream generator, non-volatile computing},\nmonth = {March},\nnote = {Best paper nomination},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_slides.pdf},\ntitle = {{H}ybrid {VC-MTJ\/CMOS} {N}on-volatile {S}tochastic {L}ogic for {E}fficient {C}omputing},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>   <\/p>\n","protected":false},"excerpt":{"rendered":"<p>Stochastic Spintronic Dataflow Computing Students: Tianmu Li, Wojciech Romaszkan The SSDC project is a collaborative effort between three faculty of the UCLA Electrical and Computer&hellip;<\/p>\n","protected":false},"author":1,"featured_media":884,"parent":160,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-266","page","type-page","status-publish","has-post-thumbnail","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/266","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=266"}],"version-history":[{"count":10,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/266\/revisions"}],"predecessor-version":[{"id":897,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/266\/revisions\/897"}],"up":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/160"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/media\/884"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=266"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}