{"id":261,"date":"2019-10-08T23:42:41","date_gmt":"2019-10-08T23:42:41","guid":{"rendered":"http:\/\/nanocad.ee.ucla.edu\/?page_id=261"},"modified":"2025-10-22T17:57:56","modified_gmt":"2025-10-22T17:57:56","slug":"waferscale-integration","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=261","title":{"rendered":"Waferscale Integration"},"content":{"rendered":"\n

Students: Saptadeep Pal<\/strong><\/p>\n\n\n\n

With the emergence of new applications, new business models, and new data processing techniques (e.g., deep learning), the need for parallel hardware
has never been stronger. Unfortunately, there is an equally strong countervailing trend. Parallel hardware necessitates low overhead communication between different computing nodes. However, the overhead of communication has been increasing at an alarming pace and is expected to be worse in future as communication energy, latency, and bandwidth scale much worse than computation. As a result, increasing communication overhead is already threatening computer system scaling.<\/p>\n\n\n\n

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One approach to dramatically reduce communication overheads is waferscale (WS) processing, where a processor chip is of the size of an entire 300mm wafer. However, WS processors have been historically deemed impractical due to yield issues of building a large monolithic WS chip. Most yield loss in chipmaking comes from defects in the transistor layers or in the high-density lower metal layers.<\/p>\n\n\n\n

We take a different route towards realizing WS processors using the Silicon-Interconnection Fabric (Si-IF)<\/a> technology. Here smaller pre-manufactured dies are directly bonded onto a silicon wafer, enables one to build a WS system without the corresponding yield issues. The WS substrate only contains relatively low-density metal layers on the wafer, roughly the same density as the upper layers of a system on a chip<\/a>, and is only used for high-density inter-die interconnections.<\/p>\n<\/div><\/div>\n\n\n\n

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Related to Si-IF based WS-Processors, we specifically study and explore computer architecture solutions for massively parallel WS processors. We also develop system design solutions for dielet assembly on high performance interconnect substrates such as Si-IF, interposers etc. Our recent proposal of a waferscale-GPU can achieve up to 18.9x speedup and 143x EDP benefit compared against equivalent MCM-GPU based implementation on PCB. We are currently working on a massively parallel general purpose waferscale processor prototype built using ARM processors.<\/p>\n<\/div><\/div>\n\n\n\n

Collaborators: CHIPS-UCLA<\/a>, Rakesh Kumar (UIUC)<\/a><\/p>\n\n\n\n

Publications<\/h2>\n\n\n\n