{"id":25,"date":"2019-09-30T22:31:44","date_gmt":"2019-09-30T22:31:44","guid":{"rendered":"http:\/\/nanocad.ee.ucla.edu\/?page_id=25"},"modified":"2025-12-16T22:49:33","modified_gmt":"2025-12-16T22:49:33","slug":"members","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=25","title":{"rendered":"Members"},"content":{"rendered":"\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-1'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=25\/#Faculty_Principal_Investigator\" >Faculty (Principal Investigator)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-1'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=25\/#Post_Docs\" >Post Docs<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-1'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=25\/#PhD_Students\" >PhD Students<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-1'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=25\/#MS\" >M.S.<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-1'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=25\/#Alumni\" >Alumni<\/a><ul class='ez-toc-list-level-2' ><li class='ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=25\/#PhD\" >Ph.D.<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=25\/#MS-2\" >M.S.<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n<h1 class=\"wp-block-heading has-text-align-center\"><span class=\"ez-toc-section\" id=\"Faculty_Principal_Investigator\"><\/span><strong>Faculty (Principal Investigator)<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h1>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:24% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"488\" height=\"532\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/09\/puneetgupta_small.jpg\" alt=\"\" class=\"wp-image-26 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Professor Puneet Gupta <a href=\"https:\/\/www.linkedin.com\/in\/puneet-gupta-ucla\/\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\" width=\"30\" height=\"30\"><\/a>  <a href=\"https:\/\/scholar.google.com\/citations?user=H0Ny7DQAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" src=\"\/wp-content\/plugins\/papercite\/img\/icons8-google-scholar.svg\" width=\"30\" height=\"30\"><\/a><\/p>\n\n\n\n<p><strong>Homepage: <\/strong><a href=\"http:\/\/www.ee.ucla.edu\/~puneet\" target=\"_blank\" rel=\"noreferrer noopener\">http:\/\/www.ee.ucla.edu\/~puneet&nbsp;&nbsp;&nbsp;<\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong> &#x70;u&#x6e;&#101;&#x65;&#116; &#x41;&#84;&#x20;&#101;e&#x20;&#68;&#x4f;&#84; &#x75;c&#x6c;&#97;&#x20;&#x44;O&#x54;&#32;&#x65;&#100;u&#x20;\n\n\n\n<p><a href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=84\">Publications<\/a><\/p>\n<\/div><\/div>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n\n\n\n<h1 class=\"wp-block-heading has-text-align-center\"><span class=\"ez-toc-section\" id=\"Post_Docs\"><\/span>Post Docs<span class=\"ez-toc-section-end\"><\/span><\/h1>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"425\" height=\"567\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/Jooyeon-Jeong.jpg\" alt=\"\" class=\"wp-image-1346 size-full\" srcset=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/Jooyeon-Jeong.jpg 425w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/Jooyeon-Jeong-225x300.jpg 225w\" sizes=\"auto, (max-width: 425px) 100vw, 425px\" \/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Jooyeon Jeong <a href=\"https:\/\/www.linkedin.com\/in\/jooyeon-jeong\/\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a><a href=\"https:\/\/scholar.google.com\/citations?user=V6V-o1sAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noreferrer noopener\"> <\/a><a href=\"https:\/\/scholar.google.com\/citations?user=gsRRl5UAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/icons8-google-scholar.svg\"> <\/a><a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#109;&#x61;&#105;&#x6c;&#116;&#x6f;&#58;&#x73;&#104;&#x75;&#114;&#x75;&#105;&#x6c;&#105;&#x40;&#117;&#x63;&#108;&#x61;&#46;&#x65;&#100;&#x75;\"> <\/a> &#x20;&#106;&#111;&#x6f;&#x79;&#101;&#111;&#x6e;&#x33;&#55;&#64;&#x75;&#x63;&#108;&#97;&#x2e;&#x65;&#100;&#117;&#x20;\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e36f3b\"  tabindex=\"0\" title=\"NanoCAD Publications\"    >NanoCAD Publications<\/span><div id=\"target-id69f27e4e36f3b\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c138.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Yen, <span class=\"papercite_highlight\">J. Jeong<\/span>, and P. Gupta, &#8220;Link quality aware pathfinding for chiplet interconnects,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2026  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_0\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_0_block\"><pre><code class=\"tex bibtex\">@inproceedings{C138,\nauthor = {Yen, Aaron and Jeong, Jooyeon and Gupta, Puneet},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {},\nnumber = {},\npages = {},\ntitle = {Link Quality Aware Pathfinding for Chiplet Interconnects},\nvolume = {},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n\n\n\n<h1 class=\"wp-block-heading has-text-align-center\"><span class=\"ez-toc-section\" id=\"PhD_Students\"><\/span>PhD Students<span class=\"ez-toc-section-end\"><\/span><\/h1>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:26% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"2674\" height=\"2305\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2020\/09\/alexander_graening.jpg\" alt=\"\" class=\"wp-image-736 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Alexander Graening <a href=\"https:\/\/www.linkedin.com\/in\/alexander-graening-b66227139\/\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a><a href=\"https:\/\/scholar.google.com\/citations?user=V6V-o1sAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noreferrer noopener\"> <\/a><a href=\"https:\/\/scholar.google.com\/citations?user=ON9ErwUAAAAJ&amp;hl=en&amp;oi=ao\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/icons8-google-scholar.svg\"> <\/a> <a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#109;&#x61;i&#108;&#x74;o&#58;&#x73;h&#x75;&#x72;&#117;&#x69;l&#105;&#x40;u&#99;&#x6c;a&#x2e;&#x65;&#100;&#x75;\"> <\/a> &#32;&#x20;&#x61;g&#114;&#x61;e&#110;&#x69;&#x6e;g&#64;&#x75;c&#108;&#x61;&#x2e;e&#100;&#x75;  <\/p>\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e36f91\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e36f91\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c137.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    D. Ray, G. Karfakis, <span class=\"papercite_highlight\">A. Graening<\/span>, D. Ratchkov, and P. Gupta, &#8220;Thermally-aware system-technology co-optimization for ai systems,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2026  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_6\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_6_block\"><pre><code class=\"tex bibtex\">@inproceedings{C137,\nauthor = {Ray, Dedeepyo and Karfakis, George and Graening, Alexander and Ratchkov, David and Gupta, Puneet},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {},\nnumber = {},\npages = {},\ntitle = {Thermally-Aware System-Technology Co-Optimization for AI Systems},\nvolume = {},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j89.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">A. Graening<\/span>, P. Gupta, A. B. Kahng, B. Pramanik, and Z. Wang, &#8220;ChipletPart: cost-aware partitioning for 2.5D systems,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2026.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_10\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_10_block\"><pre><code class=\"tex bibtex\">@article{J89,\nauthor = {Graening, Alexander and Gupta, Puneet and Kahng, Andrew B. and Pramanik, Bodhi and Wang, Zhiang},\ndoi = {},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\ntitle = {{ChipletPart:} Cost-Aware Partitioning for {2.5D} Systems},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j84.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/JETCAS.2025.3595909' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        G. Karfakis, M. Bouzidi, Y. Im, <span class=\"papercite_highlight\">A. Graening<\/span>, S. K. Sitaraman, and P. Gupta, &#8220;Optimizing thermal performance in 2.5d systems using embedded isolators,&#8221; <span style=\"font-style: italic\">IEEE Journal on Emerging and Selected Topics in Circuits and Systems<\/span>, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_8\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_8_block\"><pre><code class=\"tex bibtex\">@article{J84,\nauthor = {Karfakis, George and Bouzidi, Myriam and Im, Yunhyeok and Graening, Alexander and Sitaraman, Suresh K. and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/JETCAS.2025.3595909},\njournal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},\ntitle = {Optimizing Thermal Performance in 2.5D Systems Using Embedded Isolators},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j85.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/TCAD.2025.3597570' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">A. Graening<\/span>, J. Talukdar, S. Pal, K. Chakrabarty, and P. Gupta, &#8220;CATCH: a cost analysis tool for co-optimization of chiplet-based heterogeneous systems,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_9\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_9_block\"><pre><code class=\"tex bibtex\">@article{J85,\nauthor = {Graening, Alexander and Talukdar, Jonti and Pal, Saptadeep and Chakrabarty, Krishnendu and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/TCAD.2025.3597570},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ntitle = {{CATCH}: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c131.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">A. Graening<\/span>, D. A. Patel, G. Sisto, E. Lenormand, M. Perumkunnil, N. Pantano, V. B. Y. Kumar, P. Gupta, and A. Mallik, &#8220;Cost-performance co-optimization for the chiplet era,&#8221; in <span style=\"font-style: italic\">IEEE Electronics Packaging Technology Conference (EPTC)<\/span>,  2024, p. 6  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_5\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_5_block\"><pre><code class=\"tex bibtex\">@inproceedings{C131,\nauthor = {Graening, Alexander and Patel, Darayus Adil and Sisto, Giuliano and Lenormand, Erwan and Perumkunnil, Manu and Pantano, Nicolas and Kumar, Vinay B.Y. and Gupta, Puneet and Mallik, Arindam},\nbooktitle = {{IEEE Electronics Packaging Technology Conference (EPTC)}},\ndoi = {},\nkeywords = {},\nmonth = {December},\nnumber = {},\npages = {6},\ntitle = {Cost-Performance Co-Optimization for the Chiplet Era},\nvolume = {},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c127.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, J. Yang, <span class=\"papercite_highlight\">A. Graening<\/span>, V. Jacob, J. Sen, S. Pamarti, and P. Gupta, &#8220;SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2024, p. 12  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_3\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_3_block\"><pre><code class=\"tex bibtex\">@inproceedings{C127,\nauthor = {Romaszkan, Wojciech and Yang, Jiyue and Graening, Alexander and Jacob, Vinod and Sen, Jishnu and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {},\nmonth = {September},\npages = {12},\ntitle = {{SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c128.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Yang, <span class=\"papercite_highlight\">A. Graening<\/span>, W. Romaszkan, V. K. Jacob, P. Gupta, and S. Pamarti, &#8220;A 278-514M Event\/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera,&#8221; in <span style=\"font-style: italic\">IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)<\/span>,  2024, p. 2  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_4\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_4_block\"><pre><code class=\"tex bibtex\">@inproceedings{C128,\nauthor = {Yang, Jiyue and Graening, Alexander and Romaszkan, Wojciech and Jacob, Vinod K. and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)}},\ndoi = {},\nkeywords = {},\nmonth = {June},\npages = {2},\ntitle = {{A 278-514M Event\/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip19.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Niemier, Z. Enciso, M. M. Sharifi, X. S. Hu, I. O&#8217;Conner, <span class=\"papercite_highlight\">A. Graening<\/span>, R. Sharma, P. Gupta, J. Castrillon, J. P. C. Lima, N. Afroze, A. Khan, and J. Ryckaert, &#8220;Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, &#038; Compilers,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2024, p. 10  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_7\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_7_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP19,\nauthor = {Niemier, Michael and Enciso, Zephan and Sharifi, Mohammed Mehdi and Hu, Xiaobo Sharon and O'Conner, Ian and Graening, Alexander and Sharma, Ravit and Gupta, Puneet and Castrillon, Jeronimo and Lima, J.P.C. and Afroze, Nashrah and Khan, Asif and Ryckaert, Julien},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {},\nkeywords = {chiplets,wsi},\nmonth = {March},\nnote = {},\npages = {10},\ntitle = {{Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c124.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">A. Graening<\/span>, S. Pal, and P. Gupta, &#8220;Chiplets: How Small is too Small?,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2023, p. 6  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_2\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_2_block\"><pre><code class=\"tex bibtex\">@inproceedings{C124,\nauthor = {Graening, Alexander and Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ndoi = {},\nkeywords = {chiplets,wsi},\nmonth = {July},\nnote = {},\npages = {6},\ntitle = {{Chiplets: How Small is too Small?}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [10]                            J. Yang, W. Romaszkan, <span class=\"papercite_highlight\">A. Graening<\/span>, V. K. Jacob, T. Li, P. Gupta, and S. Pamarti, &#8220;A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2023  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_12\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_12_block\"><pre><code class=\"tex bibtex\">@conference{W22,\nauthor = {Yang, Jiyue and Romaszkan, Wojciech and Graening, Alexander and Jacob, Vinod Kurian and Li, Tianmu and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, event-based camera, accelerator},\ntitle = {{A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [11]                            <span class=\"papercite_highlight\">A. Graening<\/span>, W. Romaszkan, S. Pamarti, and P. Gupta, &#8220;Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_11\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_11_block\"><pre><code class=\"tex bibtex\">@conference{W21,\nauthor = {Graening, Alexander and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, event-based camera, accelerator},\ntitle = {{Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c113.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Li, W. Romaszkan, <span class=\"papercite_highlight\">A. Graening<\/span>, and P. Gupta, &#8220;SWIS &#8211; Shared Weight bIt Sparsity for Efficient Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">International Research Symposium on Tiny Machine Learning (tinyML)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_1\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_1_block\"><pre><code class=\"tex bibtex\">@inproceedings{C113,\nauthor = {Li, Shurui and Romaszkan, Wojciech and Graening, Alexander and Gupta, Puneet},\nbooktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},\ndoi = {},\nkeywords = {mledge, quantization, systolic array},\nmonth = {March},\nnote = {},\npages = {},\ntitle = {{SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:21% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"600\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2023\/10\/George-Karfakis.jpg\" alt=\"\" class=\"wp-image-1020 size-full\" srcset=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2023\/10\/George-Karfakis.jpg 600w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2023\/10\/George-Karfakis-300x300.jpg 300w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2023\/10\/George-Karfakis-150x150.jpg 150w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">George Karfakis <a href=\"https:\/\/www.linkedin.com\/in\/george-karfakis-089726195\/\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a><a href=\"https:\/\/scholar.google.com\/citations?user=V6V-o1sAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noreferrer noopener\"> <\/a><a href=\"https:\/\/scholar.google.com\/citations?user=NarRLjIAAAAJ&amp;hl=en&amp;oi=ao\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/icons8-google-scholar.svg\"><\/a><a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#x6d;&#97;i&#x6c;&#116;&#111;&#x3a;&#x73;&#104;u&#x72;&#117;i&#x6c;&#x69;&#64;u&#x63;&#108;a&#x2e;&#x65;&#100;u\"> <\/a> &#x20; &#x67;&#101;&#x6f;&#x72;g&#x65;&#107;&#x61;&#x72;f&#x61;&#107;&#x69;&#x73;&#64;&#x75;&#99;&#x6c;&#x61;&#46;&#x65;&#100;&#x75;&#x20; <\/p>\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e36fc9\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e36fc9\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c137.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    D. Ray, <span class=\"papercite_highlight\">G. Karfakis<\/span>, A. Graening, D. Ratchkov, and P. Gupta, &#8220;Thermally-aware system-technology co-optimization for ai systems,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2026  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_13\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_13_block\"><pre><code class=\"tex bibtex\">@inproceedings{C137,\nauthor = {Ray, Dedeepyo and Karfakis, George and Graening, Alexander and Ratchkov, David and Gupta, Puneet},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {},\nnumber = {},\npages = {},\ntitle = {Thermally-Aware System-Technology Co-Optimization for AI Systems},\nvolume = {},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j84.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/JETCAS.2025.3595909' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">G. Karfakis<\/span>, M. Bouzidi, Y. Im, A. Graening, S. K. Sitaraman, and P. Gupta, &#8220;Optimizing thermal performance in 2.5d systems using embedded isolators,&#8221; <span style=\"font-style: italic\">IEEE Journal on Emerging and Selected Topics in Circuits and Systems<\/span>, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_14\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_14_block\"><pre><code class=\"tex bibtex\">@article{J84,\nauthor = {Karfakis, George and Bouzidi, Myriam and Im, Yunhyeok and Graening, Alexander and Sitaraman, Suresh K. and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/JETCAS.2025.3595909},\njournal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},\ntitle = {Optimizing Thermal Performance in 2.5D Systems Using Embedded Isolators},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:26% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"930\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2023\/10\/ZhichaoChen-1-1024x930.jpg\" alt=\"\" class=\"wp-image-1023 size-full\" srcset=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2023\/10\/ZhichaoChen-1-1024x930.jpg 1024w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2023\/10\/ZhichaoChen-1-300x273.jpg 300w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2023\/10\/ZhichaoChen-1-768x698.jpg 768w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2023\/10\/ZhichaoChen-1.jpg 1280w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Zhichao Chen <a href=\"https:\/\/www.linkedin.com\/in\/zhichao-chen\/\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a> <a href=\"https:\/\/scholar.google.com\/citations?user=V6V-o1sAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/icons8-google-scholar.svg\"><\/a><a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Homepage:\u00a0<\/strong><a href=\"https:\/\/chen-zhichao.github.io\/\" target=\"_blank\" rel=\"noreferrer noopener\">https:\/\/chen-zhichao.github.io\/<\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#x6d;&#x61;&#x69;&#x6c;&#116;&#111;&#58;sh&#x75;&#x72;&#x75;&#x69;&#x6c;&#105;&#64;&#117;cl&#x61;&#x2e;&#x65;&#x64;&#x75;\"> <\/a> &#x20; &#x7a;&#104;&#x69;&#99;h&#x61;&#111;&#x63;&#104;e&#x6e;&#64;&#x75;&#99;l&#x61;&#46;&#x65;&#100;&#x75;&#x20; <\/p>\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e36ff6\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e36ff6\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c139.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Bhoumik, <span class=\"papercite_highlight\">Z. Chen<\/span>, P. Gupta, and K. Chakrabarty, &#8220;DART: Dynamic Repair for Interconnect Fault Tolerance in Hybrid Bonding,&#8221; in <span style=\"font-style: italic\">44th IEEE VLSI Test Symposium<\/span>,  2026, p. 7  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_16\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_16_block\"><pre><code class=\"tex bibtex\">@inproceedings{C139,\nauthor = {Bhoumik, Partho and Chen, Zhichao and Gupta, Puneet and Chakrabarty, Krishnendu},\nbooktitle = {{{44th IEEE VLSI Test Symposium}}},\ndoi = {},\nkeywords = {chiplets},\nmonth = {April},\nnote = {},\npages = {7},\ntitle = {{DART: Dynamic Repair for Interconnect Fault Tolerance in Hybrid Bonding}},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j88.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/TCAD.2026.3657674' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">Z. Chen<\/span> and P. Gupta, &#8220;YAP+: pad-layout-aware yield modeling and simulation for hybrid bonding,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2026.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_18\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_18_block\"><pre><code class=\"tex bibtex\">@article{J88,\nauthor = {Chen, Zhichao and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/TCAD.2026.3657674},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ntitle = {{YAP+}: Pad-Layout-Aware Yield Modeling and Simulation for Hybrid Bonding},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c133.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/DAC63849.2025.11132483' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">Z. Chen<\/span> and P. Gupta, &#8220;YAP: Yield Modeling and Simulation for Advanced Packaging,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2025, p. 7  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_15\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_15_block\"><pre><code class=\"tex bibtex\">@inproceedings{C133,\nauthor = {Chen, Zhichao and Gupta, Puneet},\nbooktitle = {{{Proc. ACM\/IEEE Design Automation Conference (DAC)}}},\ndoi = {https:\/\/doi.org\/10.1109\/DAC63849.2025.11132483},\nkeywords = {chiplets},\nmonth = {June},\nnote = {},\npages = {7},\ntitle = {{YAP: Yield Modeling and Simulation for Advanced Packaging}},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j81.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1109\/TVLSI.2024.3508673' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">Z. Chen<\/span>, H. Hassan  A., R. Ramadhan, Y. Li, C. K. Yang, S. Pamarti, and P. Gupta, &#8220;A comparative analysis of low temperature and room temperature circuit operation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration (TVLSI) Systems<\/span>, 2024.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_17\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_17_block\"><pre><code class=\"tex bibtex\">@article{J81,\nauthor = {Chen, Z. and Hassan, A., H. and Ramadhan, R. and Li, Y. and Yang, C. K. and Pamarti, S. and Gupta, P.},\ndoi = {10.1109\/TVLSI.2024.3508673},\njournal = {{{IEEE Transactions on Very Large Scale Integration (TVLSI) Systems}}},\ntitle = {A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w28.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">Z. Chen<\/span>, A. H. Hassan, S. Pamarti, C. K. Yang, and P. Gupta, &#8220;An Analysis of Power and Performance Improvements from Low-Temperature Operation of Processors using PROCEED-LT,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2024  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_19\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_19_block\"><pre><code class=\"tex bibtex\">@conference{W28,\nauthor = {Chen, Zhichao and Hassan, Ali H. and Pamarti, Sudhakar and Yang, Chih-Kong Ken and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {},\ntitle = {{An Analysis of Power and Performance Improvements from Low-Temperature Operation of Processors using PROCEED-LT}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:18% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"413\" height=\"531\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/1537.jpg\" alt=\"\" class=\"wp-image-1322 size-full\" srcset=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/1537.jpg 413w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/1537-233x300.jpg 233w\" sizes=\"auto, (max-width: 413px) 100vw, 413px\" \/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dedeepyo Ray <a href=\"https:\/\/www.linkedin.com\/in\/dedeepyo-ray-aab1891a8\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a> <a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#x6d;&#97;&#105;&#x6c;&#x74;&#111;&#58;&#x73;&#x68;&#117;&#114;&#x75;&#x69;&#108;&#105;&#x40;&#x75;&#99;&#108;&#x61;&#x2e;&#101;&#100;&#x75;\"> <\/a> &#x20;&#x72;&#x61;&#x79;&#x32;&#x35;&#x64;&#x65;&#x64;&#x65;&#x65;&#x70;&#x79;&#x6f;&#x39;&#x39;&#x40;&#x75;&#x63;&#x6c;&#x61;&#x2e;&#101;&#100;&#117;&#32;\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e37020\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37020\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c137.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">D. Ray<\/span>, G. Karfakis, A. Graening, D. Ratchkov, and P. Gupta, &#8220;Thermally-aware system-technology co-optimization for ai systems,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2026  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_20\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_20_block\"><pre><code class=\"tex bibtex\">@inproceedings{C137,\nauthor = {Ray, Dedeepyo and Karfakis, George and Graening, Alexander and Ratchkov, David and Gupta, Puneet},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {},\nnumber = {},\npages = {},\ntitle = {Thermally-Aware System-Technology Co-Optimization for AI Systems},\nvolume = {},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"683\" height=\"1024\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/DSC04768_fix-683x1024.jpg\" alt=\"\" class=\"wp-image-1325 size-full\" srcset=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/DSC04768_fix-683x1024.jpg 683w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/DSC04768_fix-200x300.jpg 200w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/DSC04768_fix-768x1152.jpg 768w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/DSC04768_fix-1024x1536.jpg 1024w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/DSC04768_fix-1365x2048.jpg 1365w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/05\/DSC04768_fix-scaled.jpg 1707w\" sizes=\"auto, (max-width: 683px) 100vw, 683px\" \/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Aaron Yen <a href=\"https:\/\/www.linkedin.com\/in\/aaron-yen-b2701383?\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a> <a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#x6d;&#97;i&#x6c;&#x74;&#111;:&#x73;&#x68;&#117;r&#x75;&#105;l&#x69;&#x40;&#117;c&#x6c;&#x61;&#46;e&#x64;&#117;\"> <\/a> &#x20;&#x61;&#x61;&#x72;&#x6f;&#x6e;&#x68;&#121;&#101;&#110;&#64;&#117;cla&#46;&#x65;&#x64;&#x75;&#x20;\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e37046\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37046\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c138.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">A. Yen<\/span>, J. Jeong, and P. Gupta, &#8220;Link quality aware pathfinding for chiplet interconnects,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2026  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_21\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_21_block\"><pre><code class=\"tex bibtex\">@inproceedings{C138,\nauthor = {Yen, Aaron and Jeong, Jooyeon and Gupta, Puneet},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {},\nnumber = {},\npages = {},\ntitle = {Link Quality Aware Pathfinding for Chiplet Interconnects},\nvolume = {},\nyear = {2026}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"768\" height=\"1024\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/10\/ernest_wang-768x1024.jpg\" alt=\"\" class=\"wp-image-1357 size-full\" srcset=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/10\/ernest_wang-768x1024.jpg 768w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/10\/ernest_wang-225x300.jpg 225w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/10\/ernest_wang-1152x1536.jpg 1152w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/10\/ernest_wang-1536x2048.jpg 1536w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/10\/ernest_wang-scaled.jpg 1920w\" sizes=\"auto, (max-width: 768px) 100vw, 768px\" \/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Ernest Wang <a href=\"https:\/\/www.linkedin.com\/in\/ece-ernw\/\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a> <a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#x6d;a&#x69;&#108;t&#x6f;&#58;&#x73;&#104;u&#x72;&#117;&#x69;&#108;i&#x40;&#117;&#x63;&#x6c;a&#x2e;&#101;d&#x75;\"> <\/a> &#x20;&#101;r&#x6e;&#101;&#119;&#x32;&#x31;&#64;u&#x63;&#108;a&#x2e;&#x65;&#100;u&#x20;\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e37069\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37069\" class=\"collapseomatic_content \"><\/code><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n\n\n\n<h1 class=\"wp-block-heading has-text-align-center\"><span class=\"ez-toc-section\" id=\"MS\"><\/span>M.S.<span class=\"ez-toc-section-end\"><\/span><\/h1>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:25% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"1024\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/S1_Talk4_Lime_Yao-1024x1024.jpg\" alt=\"\" class=\"wp-image-1351 size-full\" srcset=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/S1_Talk4_Lime_Yao-1024x1024.jpg 1024w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/S1_Talk4_Lime_Yao-300x300.jpg 300w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/S1_Talk4_Lime_Yao-150x150.jpg 150w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/S1_Talk4_Lime_Yao-768x768.jpg 768w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/S1_Talk4_Lime_Yao.jpg 1168w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Lime Yao <a href=\"http:\/\/www.linkedin.com\/in\/lime-yao\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a><a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#x6d;&#97;i&#x6c;&#116;o&#x3a;&#115;h&#x75;&#114;u&#x69;&#108;i&#x40;&#x75;c&#x6c;&#x61;&#46;&#x65;&#x64;&#117;\"> <\/a> &#32;&#x79;&#97;&#x6f;e&#x38;8&#56;&#x40;&#117;&#x63;l&#x61;&#46;&#101;&#x64;&#117;&#x20;\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e37085\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37085\" class=\"collapseomatic_content \"><\/code><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:22% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"796\" height=\"1024\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/\uc774\ucc2c\ud76c1-796x1024.jpg\" alt=\"\" class=\"wp-image-1347 size-full\" srcset=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/\uc774\ucc2c\ud76c1-796x1024.jpg 796w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/\uc774\ucc2c\ud76c1-233x300.jpg 233w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/\uc774\ucc2c\ud76c1-768x988.jpg 768w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/\uc774\ucc2c\ud76c1-1195x1536.jpg 1195w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/\uc774\ucc2c\ud76c1.jpg 1200w\" sizes=\"auto, (max-width: 796px) 100vw, 796px\" \/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Chanhee Lee <a href=\"http:\/\/www.linkedin.com\/in\/chanhee-lee-b7a227314\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a><a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#x6d;&#x61;&#x69;&#108;&#116;o:&#x73;&#x68;&#x75;&#114;&#117;il&#x69;&#x40;&#x75;&#99;&#108;a&#46;&#x65;&#x64;&#x75;\"> <\/a> &#32;&#x63;&#104;&#x61;&#110;&#x68;&#101;&#x65;&#53;&#x32;&#55;&#x40;u&#x63;l&#x61;&#46;&#x65;d&#x75; \n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e3709f\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e3709f\" class=\"collapseomatic_content \"><\/code><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:22% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"480\" height=\"640\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/873efa471bd5a97805c548453de25337.jpg\" alt=\"\" class=\"wp-image-1354 size-full\" srcset=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/873efa471bd5a97805c548453de25337.jpg 480w, https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2025\/08\/873efa471bd5a97805c548453de25337-225x300.jpg 225w\" sizes=\"auto, (max-width: 480px) 100vw, 480px\" \/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Tianrun Gou <a href=\"http:\/\/www.linkedin.com\/in\/tianrun-gou-489b59288\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a><a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"mai&#108;&#116;&#111;&#58;&#x73;&#x68;&#x75;&#x72;&#x75;&#x69;&#x6c;i&#64;u&#99;&#108;&#97;&#46;&#101;&#x64;&#x75;\"> <\/a> &#x20;&#x74;&#x67;&#x6f;&#x75;&#64;&#117;&#99;&#108;a&#46;e&#x64;&#x75;&#x20;\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e370c0\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e370c0\" class=\"collapseomatic_content \"><\/code><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n\n\n\n<h1 class=\"wp-block-heading has-text-align-center\"><span class=\"ez-toc-section\" id=\"Alumni\"><\/span>Alumni<span class=\"ez-toc-section-end\"><\/span><\/h1>\n\n\n\n<h2 class=\"wp-block-heading has-text-align-center\"><span class=\"ez-toc-section\" id=\"PhD\"><\/span>Ph.D.<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:21% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"360\" height=\"340\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/shurui.jpg\" alt=\"\" class=\"wp-image-235 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Shurui Li <a href=\"https:\/\/www.linkedin.com\/in\/shurui-li-a2518b131\/\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a> <a href=\"https:\/\/scholar.google.com\/citations?user=dRIB5HEAAAAJ&amp;hl=en\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/icons8-google-scholar.svg\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"mailto:shuru&#105;&#108;&#105;&#64;&#117;&#99;&#108;&#97;&#46;&#101;&#100;&#117;\"> <\/a> &#x20; &#x73;&#104;&#x75;&#114;u&#x69;l&#x69;&#64;&#x75;&#99;l&#x61;&#46;&#x65;&#100;u&#x20; <\/p>\n\n\n\n<p><strong>Research interests<\/strong>: Optical Neural Network Accelerator, Lower-power Neural Network Inference<\/p>\n\n\n\n<p><strong>Industry experience<\/strong>:  Qualcomm<\/p>\n\n\n\n<p><strong>Last known coordinates: <\/strong>Waymo<\/p>\n\n\n\n<p><strong>PhD Thesis:<\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Li, &#8220;Architecture, modeling, and optimization of photonic neural network accelerators,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2024. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_22\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_22_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH14,\nauthor = {Li, Shurui},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {},\ntitle = {Architecture, Modeling, and Optimization of Photonic Neural Network Accelerators},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e370e5\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e370e5\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]                            H. Yang, N. Peserico, <span class=\"papercite_highlight\">S. Li<\/span>, X. Ma, R. L. Schwartz, M. Hosseini, A. Babakhani, C. W. Wong, P. Gupta, and V. J. Sorger, &#8220;Near-energy-free photonic fourier transformation for convolution operation acceleration,&#8221; <span style=\"font-style: italic\">Advanced Photonics<\/span>, vol. 7, iss. 5, p. 056007\u2013056007, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_32\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_32_block\"><pre><code class=\"tex bibtex\">@article{J86,\nauthor = {Yang, Hangbo and Peserico, Nicola and Li, Shurui and Ma, Xiaoxuan and Schwartz, Russell LT and Hosseini, Mostafa and Babakhani, Aydin and Wong, Chee Wei and Gupta, Puneet and Sorger, Volker J},\njournal = {{Advanced Photonics}},\nnumber = {5},\npages = {056007--056007},\npublisher = {Society of Photo-Optical Instrumentation Engineers},\ntitle = {Near-energy-free photonic Fourier transformation for convolution operation acceleration},\nvolume = {7},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Li<\/span>, &#8220;Architecture, modeling, and optimization of photonic neural network accelerators,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2024.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_33\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_33_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH14,\nauthor = {Li, Shurui},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {},\ntitle = {Architecture, Modeling, and Optimization of Photonic Neural Network Accelerators},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [3]                    <a href='http:\/\/dx.doi.org\/10.1117\/12.2692958' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        H. Yang, N. Pesericoa, <span class=\"papercite_highlight\">S. Li<\/span>, B. F. Motlagh, J. S. Virdi, P. Gupta, V. J. Sorger, and C. W. Wong, &#8220;Enhancing and up-scaling of integrated photonic 4F convolution neural networks,&#8221; in <span style=\"font-style: italic\">Smart Photonic and Optoelectronic Integrated Circuits 2024<\/span>,  2024, p. 1289003  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_39\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_39_block\"><pre><code class=\"tex bibtex\">@conference{W27,\nauthor = {Hangbo Yang and Nicola Pesericoa and Shurui Li and Benyamin Fallahi Motlagh and Jaskirat Singh Virdi and Puneet Gupta and Volker J. Sorger and Chee Wei Wong},\nbooktitle = {{Smart Photonic and Optoelectronic Integrated Circuits 2024}},\ndoi = {10.1117\/12.2692958},\neditor = {Sailing He and Laurent Vivien},\nkeywords = {Machine Learning, Convolution Neural Network, Integrated Photonics},\norganization = {International Society for Optics and Photonics},\npages = {1289003},\npublisher = {SPIE},\ntitle = {{Enhancing and up-scaling of integrated photonic 4F convolution neural networks}},\nurl = {https:\/\/doi.org\/10.1117\/12.2692958},\nvolume = {12890},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c125.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1145\/3613424.3623798.' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">S. Li<\/span>, H. Yang, C. W. Wong, V. J. Sorger, and P. Gupta, &#8220;ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM International Symposium on Microarchitecture (MICRO)<\/span>,  2023, p. 13  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_27\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_27_block\"><pre><code class=\"tex bibtex\">@inproceedings{C125,\nauthor = {Li, Shurui and Yang, Hangbo and Wong, Chee Wei and Sorger, Volker J. and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM International Symposium on Microarchitecture (MICRO)}},\ndoi = {https:\/\/doi.org\/10.1145\/3613424.3623798.},\nkeywords = {photonic neural network,deep learning, accelerator, photonics},\nmonth = {October},\nnote = {},\npages = {13},\ntitle = {{ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c122.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Li<\/span>, H. Yang, C. W. Wong, V. J. Sorger, and P. Gupta, &#8220;PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on High-Performance Computer Architecture (HPCA)<\/span>,  2023, p. 12  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_25\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_25_block\"><pre><code class=\"tex bibtex\">@inproceedings{C122,\nauthor = {Li, Shurui and Yang, Hangbo and Wong, Chee Wei and Sorger, Volker J. and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},\ndoi = {},\nkeywords = {photonics, neural network, accelerator},\nmonth = {February},\nnote = {},\npages = {12},\ntitle = {{PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c123.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c123_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. Li, <span class=\"papercite_highlight\">S. Li<\/span>, and P. Gupta, &#8220;Training Neural Networks for Execution on Approximate Hardware,&#8221; in <span style=\"font-style: italic\">International Research Symposium on Tiny Machine Learning (tinyML)<\/span>,  2023, p. 6  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_26\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_26_block\"><pre><code class=\"tex bibtex\">@inproceedings{C123,\nauthor = {Li, Tianmu and Li, Shurui and Gupta, Puneet},\nbooktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},\ndoi = {},\nkeywords = {approximate computing, neural networks, training},\nmonth = {March},\nnote = {},\npages = {6},\ntitle = {{Training Neural Networks for Execution on Approximate Hardware}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j71.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Z. Hu, <span class=\"papercite_highlight\">S. Li<\/span>, R. Schwartz, M. Solyanik-Gorgone, M. Miscuglio, P. Gupta, and V. Sorger, &#8220;High-Throughput Multichannel Parallelized Diffraction Convolutional Neural Network Accelerator,&#8221; <span style=\"font-style: italic\">Laser &#038; Photonics Reviews<\/span>, 2022.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_31\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_31_block\"><pre><code class=\"tex bibtex\">@article{J71,\nauthor = {Hu, Zibo and Li, Shurui and Schwartz, Russel and Solyanik-Gorgone, Maria and Miscuglio, Mario and Gupta, Puneet and Sorger, Volker},\njournal = {{Laser \\& Photonics Reviews}},\nmonth = {October},\npublisher = {{Wiley}},\ntitle = {{High-Throughput Multichannel Parallelized Diffraction Convolutional Neural Network Accelerator}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c119.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c119_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               <span class=\"papercite_highlight\">S. Li<\/span> and P. Gupta, &#8220;Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors,&#8221; in <span style=\"font-style: italic\">Conference on Machine Learning and Systems (MLSys)<\/span>,  2022, p. 10  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_24\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_24_block\"><pre><code class=\"tex bibtex\">@inproceedings{C119,\nauthor = {Li, Shurui and Gupta, Puneet},\nbooktitle = {{Conference on Machine Learning and Systems (MLSys)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {August},\nnote = {},\npages = {10},\ntitle = {{Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [9]                            <span class=\"papercite_highlight\">S. Li<\/span> and P. Gupta, &#8220;4F Optical Neural Network Acceleration: An Architectural Perspective,&#8221; in <span style=\"font-style: italic\">SPIE Photonics West Conference (AI and Optical Data Sciences)<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_29\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_29_block\"><pre><code class=\"tex bibtex\">@conference{IT29,\nauthor = {Li, Shurui and Gupta, Puneet},\nbooktitle = {{SPIE Photonics West Conference (AI and Optical Data Sciences)}},\nkeywords = {photonics, optical neural network},\nmonth = {February},\ntitle = {{4F Optical Neural Network Acceleration: An Architectural Perspective}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip18.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Li<\/span> and P. Gupta, &#8220;4F optical neural network acceleration: an architecture perspective,&#8221; in <span style=\"font-style: italic\">SPIE 12019, AI and Optical Data Sciences III<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_28\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_28_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP18,\nauthor = {Li, Shurui and Gupta, Puneet},\nbooktitle = {{{SPIE 12019, AI and Optical Data Sciences III}}},\nkeywords = {photonics},\ntitle = {{4F optical neural network acceleration: an architecture perspective}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c113.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Li<\/span>, W. Romaszkan, A. Graening, and P. Gupta, &#8220;SWIS &#8211; Shared Weight bIt Sparsity for Efficient Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">International Research Symposium on Tiny Machine Learning (tinyML)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_23\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_23_block\"><pre><code class=\"tex bibtex\">@inproceedings{C113,\nauthor = {Li, Shurui and Romaszkan, Wojciech and Graening, Alexander and Gupta, Puneet},\nbooktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},\ndoi = {},\nkeywords = {mledge, quantization, systolic array},\nmonth = {March},\nnote = {},\npages = {},\ntitle = {{SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w18.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Miscuglio, Z. Hu, <span class=\"papercite_highlight\">S. Li<\/span>, J. K. George, R. Capanna, H. Dalir, P. M. Bardet, P. Gupta, and V. J. Sorger, &#8220;Massively-parallel Amplitude-only Fourier Optical Convolutional Neural Network,&#8221; in <span style=\"font-style: italic\">Conference on Lasers and Electro-Optics (CLEO)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_36\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_36_block\"><pre><code class=\"tex bibtex\">@conference{W18,\nauthor = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and George, Jonathan K. and Capanna, Roberto and Dalir, Hamed and Bardet, Philippe M. and Gupta, Puneet and Sorger, Volker J.},\nbooktitle = {{Conference on Lasers and Electro-Optics (CLEO)}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/ieeexplore.ieee.org\/abstract\/document\/9572872},\ntitle = {{Massively-parallel Amplitude-only Fourier Optical Convolutional Neural Network}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w19.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Miscuglio, Z. Hu, <span class=\"papercite_highlight\">S. Li<\/span>, P. Gupta, H. Dalir, and V. J. Sorger, &#8220;Fourier Optical Convolutional Neural Network Accelerator,&#8221; in <span style=\"font-style: italic\">Signal Processing in Photonic Communications<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_37\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_37_block\"><pre><code class=\"tex bibtex\">@conference{W19,\nauthor = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and Gupta, Puneet and Dalir, Hamed and Sorger, Volker J.},\nbooktitle = {{Signal Processing in Photonic Communications}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/opg.optica.org\/abstract.cfm?uri=SPPCom-2021-SpM5C.2},\ntitle = {{Fourier Optical Convolutional Neural Network Accelerator}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w20.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Z. Hu, M. Solyanik-Gorgone, <span class=\"papercite_highlight\">S. Li<\/span>, P. Gupta, and V. J. Sorger, &#8220;High Throughput Multi-kernel Fourier Optic Classifier,&#8221; in <span style=\"font-style: italic\">Frontiers in Optics<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_38\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_38_block\"><pre><code class=\"tex bibtex\">@conference{W20,\nauthor = {Hu, Zibo and Solyanik-Gorgone, Maria and Li, Shurui and Gupta, Puneet and Sorger, Volker J.},\nbooktitle = {{Frontiers in Optics}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/opg.optica.org\/abstract.cfm?uri=fio-2021-FTh4C.5},\ntitle = {{High Throughput Multi-kernel Fourier Optic Classifier}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j67.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Miscuglio, Z. Hu, <span class=\"papercite_highlight\">S. Li<\/span>, J. George, R. Capanna, P. Bardet, P. Gupta, and V. Sorger, &#8220;Massively parallel amplitude-only Fourier neural network,&#8221; <span style=\"font-style: italic\">Optica<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_30\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_30_block\"><pre><code class=\"tex bibtex\">@article{J67,\nauthor = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and George, Jonathan and Capanna, Roberto and Bardet, Philippe and Gupta, Puneet and Sorger, Volker},\njournal = {{Optica}},\npublisher = {{OSA}},\ntitle = {{Massively parallel amplitude-only Fourier neural network}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w16.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Miscuglio, Z. Hu, <span class=\"papercite_highlight\">S. Li<\/span>, J. Gu, A. Babakhani, P. Gupta, C. Wong, D. Pan, S. Bank, H. Dalir, and V. J. Sorger, &#8220;Million-channel Parallelism Fourier-optic Convolutional Filter and Neural Network Processor,&#8221; in <span style=\"font-style: italic\">CLEO: Applications and Technology<\/span>,  2020  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_34\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_34_block\"><pre><code class=\"tex bibtex\">@conference{W16,\nauthor = {Miscuglio, Mario and Hu, Zibo and Li, Shurui and Gu, Jiaqi and Babakhani, Aydin and Gupta, Puneet and Wong, Chee-Wei and Pan, David and Bank, Seth and Dalir, Hamed and Sorger, Volker J.},\nbooktitle = {{CLEO: Applications and Technology}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/opg.optica.org\/abstract.cfm?uri=cleo_at-2020-JF3A.4},\ntitle = {{Million-channel Parallelism Fourier-optic Convolutional Filter and Neural Network Processor}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w17.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Z. Hu, M. Miscuglio, <span class=\"papercite_highlight\">S. Li<\/span>, J. K. George, P. Gupta, and V. J. Sorger, &#8220;Electro-Optical Hybrid Fouirer Neural Network with Amplitude-Only Modulation,&#8221; in <span style=\"font-style: italic\">Frontiers in Optics<\/span>,  2020  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_35\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_35_block\"><pre><code class=\"tex bibtex\">@conference{W17,\nauthor = {Hu, Zibo and Miscuglio, Mario and Li, Shurui and George, Jonathan K. and Gupta, Puneet and Sorger, Volker J.},\nbooktitle = {{Frontiers in Optics}},\nkeywords = {photonics, CNN, accelerator, Fourier, neural network},\npaperurl = {https:\/\/opg.optica.org\/abstract.cfm?uri=FiO-2020-FM7D.3},\ntitle = {{Electro-Optical Hybrid Fouirer Neural Network with Amplitude-Only Modulation}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:22% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"908\" height=\"1024\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/LiT_small-908x1024.jpg\" alt=\"\" class=\"wp-image-92 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Tianmu Li <a rel=\"noopener noreferrer\" href=\"https:\/\/www.linkedin.com\/in\/%E5%A4%A9%E7%89%A7-%E6%9D%8E-0525b4a6\/\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a><\/p>\n\n\n\n<p><strong>Contact: <\/strong> &#x20;&#x6c;&#x69;&#x74;&#x69;&#x61;&#x6e;&#x6d;&#x75;&#x31;&#x39;&#x39;&#x35;&#x40;&#x75;&#x63;&#x6c;&#x61;&#x2e;&#x65;&#x64;&#x75;&#x20; <\/p>\n\n\n\n<p><strong>Industry experience:<\/strong> ARM Ltd<\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Intel<\/p>\n\n\n\n<p><strong>PhD Thesis:<\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. Li, &#8220;Learned approximate computing for machine learning,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2023. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_40\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_40_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH13,\nauthor = {Li, Tianmu},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {},\ntitle = {Learned Approximate Computing for Machine Learning},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e37123\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37123\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j82.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1016\/j.msea.2025.148173' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        Y. Li, <span class=\"papercite_highlight\">T. Li<\/span>, L. Tang, S. Ma, Q. Wu, P. Gupta, and M. Bauchy, &#8220;ConvFeatNet ensemble: integrating microstructure and pre-defined features for enhanced prediction of porous material properties,&#8221; <span style=\"font-style: italic\">Materials Science and Engineering: A<\/span>, vol. 931, p. 148173, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_54\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_54_block\"><pre><code class=\"tex bibtex\">@article{J82,\nauthor = {Li ,Yuhai and Li, Tianmu and Tang, Longwen and Ma, Shiyu and Wu, Qinglin and Gupta, Puneet and Bauchy, Mathieu},\ndoi = {https:\/\/doi.org\/10.1016\/j.msea.2025.148173},\nissn = {0921-5093},\njournal = {{Materials Science and Engineering: A}},\npages = {148173},\ntitle = {{ConvFeatNet} ensemble: Integrating microstructure and pre-defined features for enhanced prediction of porous material properties},\nurl = {https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0921509325003971},\nvolume = {931},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j83.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/JSSC.2025.3554554' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        J. Yang, <span class=\"papercite_highlight\">T. Li<\/span>, W. Romaszkan, P. Gupta, and S. Pamarti, &#8220;A 65-nm digital stochastic compute-in-memory CNN processor with 8-bit precision,&#8221; <span style=\"font-style: italic\">IEEE Journal of Solid State Circuits<\/span>, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_55\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_55_block\"><pre><code class=\"tex bibtex\">@article{J83,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\ndoi = {https:\/\/doi.org\/10.1109\/JSSC.2025.3554554},\njournal = {{IEEE Journal of Solid State Circuits}},\ntitle = {A 65-nm Digital Stochastic Compute-in-Memory {CNN} Processor With 8-bit Precision},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j79.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    E. Glukhov, <span class=\"papercite_highlight\">T. Li<\/span>, V. Gupta, and P. Gupta, &#8220;Learned approximate computing: algorithm hardware co-optimization,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2024.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_53\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_53_block\"><pre><code class=\"tex bibtex\">@article{J79,\nauthor = {Egor Glukhov and Tianmu Li and Vaibhav Gupta and Puneet Gupta},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ntitle = {Learned Approximate Computing: Algorithm Hardware Co-optimization},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j74.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">T. Li<\/span>, W. Romaszkan, S. Pamarti, and P. Gupta, &#8220;REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_52\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_52_block\"><pre><code class=\"tex bibtex\">@article{J74,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nmonth = {June},\npublisher = {{IEEE}},\ntitle = {{REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c123.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c123_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">T. Li<\/span>, S. Li, and P. Gupta, &#8220;Training Neural Networks for Execution on Approximate Hardware,&#8221; in <span style=\"font-style: italic\">International Research Symposium on Tiny Machine Learning (tinyML)<\/span>,  2023, p. 6  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_46\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_46_block\"><pre><code class=\"tex bibtex\">@inproceedings{C123,\nauthor = {Li, Tianmu and Li, Shurui and Gupta, Puneet},\nbooktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},\ndoi = {},\nkeywords = {approximate computing, neural networks, training},\nmonth = {March},\nnote = {},\npages = {6},\ntitle = {{Training Neural Networks for Execution on Approximate Hardware}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">T. Li<\/span>, &#8220;Learned approximate computing for machine learning,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_56\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_56_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH13,\nauthor = {Li, Tianmu},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {},\ntitle = {Learned Approximate Computing for Machine Learning},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [7]                            J. Yang, W. Romaszkan, A. Graening, V. K. Jacob, <span class=\"papercite_highlight\">T. Li<\/span>, P. Gupta, and S. Pamarti, &#8220;A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2023  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_57\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_57_block\"><pre><code class=\"tex bibtex\">@conference{W22,\nauthor = {Yang, Jiyue and Romaszkan, Wojciech and Graening, Alexander and Jacob, Vinod Kurian and Li, Tianmu and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, event-based camera, accelerator},\ntitle = {{A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [8]                            <span class=\"papercite_highlight\">T. Li<\/span>, W. Romaszkan, S. Pal, S. Pamarti, and P. Gupta, &#8220;REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2023  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_58\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_58_block\"><pre><code class=\"tex bibtex\">@conference{W23,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pal, Soumitra and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, CNN, neural networks},\ntitle = {{REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c121.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Yang, <span class=\"papercite_highlight\">T. Li<\/span>, W. Romaszkan, P. Gupta, and S. Pamarti, &#8220;A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor,&#8221; in <span style=\"font-style: italic\">IEEE Asian Solid-State Circuits Conference<\/span>,  2022, p. 2  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_45\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_45_block\"><pre><code class=\"tex bibtex\">@inproceedings{C121,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{IEEE Asian Solid-State Circuits Conference}},\ndoi = {},\nkeywords = {mledge},\nmonth = {November},\nnote = {},\npages = {2},\ntitle = {{A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c120.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, <span class=\"papercite_highlight\">T. Li<\/span>, and P. Gupta, &#8220;SASCHA &#8211; Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2022, p. 12  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_44\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_44_block\"><pre><code class=\"tex bibtex\">@inproceedings{C120,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {October},\nnote = {Best paper nomination},\npages = {12},\ntitle = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j72.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, <span class=\"papercite_highlight\">T. Li<\/span>, and P. Gupta, &#8220;SASCHA &#8211; Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,&#8221; , p. 12, 2022.  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_51\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_51_block\"><pre><code class=\"tex bibtex\">@article{J72,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {October},\nnote = {Best paper nomination},\npages = {12},\ntitle = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j70.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, <span class=\"papercite_highlight\">T. Li<\/span>, R. Garg, J. Yang, S. Pamarti, and P. Gupta, &#8221; A 4.4-75 TOPS\/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator,&#8221; <span style=\"font-style: italic\">IEEE Solid State Circuits Letters<\/span>, 2022.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_50\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_50_block\"><pre><code class=\"tex bibtex\">@article{J70,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Garg, Rahul and Yang, Jiyue and Pamarti, Sudhakar and Gupta, Puneet},\njournal = {{IEEE Solid State Circuits Letters}},\nkeywords = {mledge},\nmonth = {August},\npublisher = {{IEEE}},\ntitle = {{ A 4.4-75 TOPS\/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c117.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    V. Gupta, <span class=\"papercite_highlight\">T. Li<\/span>, and P. Gupta, &#8220;LAC: Learned Approximate Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2022, p. 4  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_43\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_43_block\"><pre><code class=\"tex bibtex\">@inproceedings{C117,\nauthor = {Gupta, Vaibhav and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {},\nkeywords = {},\nmonth = {March},\nnote = {},\npages = {4},\ntitle = {{LAC: Learned Approximate Computing}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j69.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam, <span class=\"papercite_highlight\">T. Li<\/span>, S. Brock, and P. Gupta, &#8220;DRDebug: Automated Design Rule Debugging,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2022.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_49\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_49_block\"><pre><code class=\"tex bibtex\">@article{J69,\nauthor = {Alam, Irina and Li, Tianmu and Brock, Sean and Gupta, Puneet},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\npublisher = {{IEEE}},\ntitle = {{DRDebug: Automated Design Rule Debugging}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [15]                            J. Yang, <span class=\"papercite_highlight\">T. Li<\/span>, W. Romaszkan, P. Gupta, and S. Pamarti, &#8220;A 1.84-7.96TOPS\/W 65nm DAC\/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_60\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_60_block\"><pre><code class=\"tex bibtex\">@conference{W25,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, CNN, neural networks, accelerator},\ntitle = {{A 1.84-7.96TOPS\/W 65nm DAC\/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c112.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">T. Li<\/span>, W. Romaszkan, S. Pamarti, and P. Gupta, &#8220;GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_42\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_42_block\"><pre><code class=\"tex bibtex\">@inproceedings{C112,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {},\nkeywords = {mledge},\nmonth = {February},\nnote = {},\npages = {},\ntitle = {{GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [17]                            W. Romaszkan, <span class=\"papercite_highlight\">T. Li<\/span>, J. Yang, A. Lee, D. Wu, K. Wang, S. Pamarti, and P. Gupta, &#8220;Machine Learning at the Edge Using Spintronic Stochastic Computing,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_59\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_59_block\"><pre><code class=\"tex bibtex\">@conference{W24,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Yang, Jiyue and Lee, Albert and Wu, Di and Wang, Kang and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, CNN, neural networks},\ntitle = {{Machine Learning at the Edge Using Spintronic Stochastic Computing}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c109.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.23919\/DATE48585.2020.9116289' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        W. Romaszkan, <span class=\"papercite_highlight\">T. Li<\/span>, T. Melton, S. Pamarti, and P. Gupta, &#8220;ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2020, pp. 768-773  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_41\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_41_block\"><pre><code class=\"tex bibtex\">@inproceedings{C109,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Melton, Tristan and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {10.23919\/DATE48585.2020.9116289},\nkeywords = {mledge},\nmonth = {March},\nnote = {Best paper nomination},\npages = {768-773},\ntitle = {{ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j63.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, <span class=\"papercite_highlight\">T. Li<\/span>, and P. Gupta, &#8220;3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning,&#8221; <span style=\"font-style: italic\">ACM Transactions on Embedded Computing Systems (TECS)<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_48\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_48_block\"><pre><code class=\"tex bibtex\">@article{J63,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\njournal = {{ACM Transactions on Embedded Computing Systems (TECS)}},\nkeywords = {mledge, 3pxnet},\nmonth = {November},\npublisher = {ACM},\ntitle = {{3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [20]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c95.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c95_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            S. Wang, S. Pal, <span class=\"papercite_highlight\">T. Li<\/span>, A. Pan, C. Grezes, K. P. Amiri, K. L. Wang, C. O. Chui, and P. Gupta, &#8220;Hybrid VC-MTJ\/CMOS Non-volatile Stochastic Logic for Efficient Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2017  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_47\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_47_block\"><pre><code class=\"tex bibtex\">@inproceedings{C95,\nauthor = {Wang, Shaodi and Pal, Saptadeep and Li, Tianmu and Pan, Andrew and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Chui, Chi On and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nkeywords = {mledge,Negative differential resistance, Magnetic tunnel junction, stochastic computing, stochastic bitstream generator, non-volatile computing},\nmonth = {March},\nnote = {Best paper nomination},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_slides.pdf},\ntitle = {{H}ybrid {VC-MTJ\/CMOS} {N}on-volatile {S}tochastic {L}ogic for {E}fficient {C}omputing},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:22% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"918\" height=\"1024\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/romaszkan_w-918x1024.jpg\" alt=\"\" class=\"wp-image-93 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Wojciech Romaszkan <a rel=\"noopener noreferrer\" href=\"https:\/\/www.linkedin.com\/in\/wojciechromaszkan\/\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a>  <a rel=\"noopener noreferrer\" href=\"https:\/\/scholar.google.com\/citations?user=act0aLIAAAAJ&amp;hl=en\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/icons8-google-scholar.svg\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"mai&#108;&#116;&#111;&#58;&#x77;&#x72;&#x6f;&#x6d;&#x61;&#x73;&#x7a;kan&#64;&#117;&#99;&#108;&#97;&#x2e;&#x65;&#x64;&#x75;\"> <\/a> &#x20;&#119;r&#x6f;&#109;a&#x73;&#x7a;&#107;&#x61;&#x6e;&#64;u&#x63;&#108;a&#x2e;&#x65;&#100;&#x75;&#x20; <\/p>\n\n\n\n<p><strong>Research interests<\/strong>: Machine Learning at the Edge &#8211; low-latency and energy inference for heavily constrained devices.<\/p>\n\n\n\n<p><strong>Industry experience:<\/strong> Facebook, Imagination Technologies, UK; NEC, Japan <\/p>\n\n\n\n<p><strong>Last known coordinates<\/strong>: Amazon<\/p>\n\n\n\n<p><strong>PhD Thesis:<\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           W. Romaszkan, &#8220;Efficient machine learning acceleration at the edge,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2023. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_61\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_61_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH12,\nauthor = {Romaszkan, Wojciech},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {},\ntitle = {Efficient Machine Learning Acceleration at the Edge},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e37164\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37164\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j83.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/JSSC.2025.3554554' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        J. Yang, T. Li, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, P. Gupta, and S. Pamarti, &#8220;A 65-nm digital stochastic compute-in-memory CNN processor with 8-bit precision,&#8221; <span style=\"font-style: italic\">IEEE Journal of Solid State Circuits<\/span>, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_73\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_73_block\"><pre><code class=\"tex bibtex\">@article{J83,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\ndoi = {https:\/\/doi.org\/10.1109\/JSSC.2025.3554554},\njournal = {{IEEE Journal of Solid State Circuits}},\ntitle = {A 65-nm Digital Stochastic Compute-in-Memory {CNN} Processor With 8-bit Precision},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c127.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Romaszkan<\/span>, J. Yang, A. Graening, V. Jacob, J. Sen, S. Pamarti, and P. Gupta, &#8220;SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2024, p. 12  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_67\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_67_block\"><pre><code class=\"tex bibtex\">@inproceedings{C127,\nauthor = {Romaszkan, Wojciech and Yang, Jiyue and Graening, Alexander and Jacob, Vinod and Sen, Jishnu and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {},\nmonth = {September},\npages = {12},\ntitle = {{SCIMITAR: Stochastic Computing In-Memory In-situ Tracking ARchitecture for Event-Based Cameras}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c128.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Yang, A. Graening, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, V. K. Jacob, P. Gupta, and S. Pamarti, &#8220;A 278-514M Event\/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera,&#8221; in <span style=\"font-style: italic\">IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)<\/span>,  2024, p. 2  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_68\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_68_block\"><pre><code class=\"tex bibtex\">@inproceedings{C128,\nauthor = {Yang, Jiyue and Graening, Alexander and Romaszkan, Wojciech and Jacob, Vinod K. and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)}},\ndoi = {},\nkeywords = {},\nmonth = {June},\npages = {2},\ntitle = {{A 278-514M Event\/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera}},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j74.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Li, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, S. Pamarti, and P. Gupta, &#8220;REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_72\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_72_block\"><pre><code class=\"tex bibtex\">@article{J74,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nmonth = {June},\npublisher = {{IEEE}},\ntitle = {{REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Romaszkan<\/span>, &#8220;Efficient machine learning acceleration at the edge,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_74\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_74_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH12,\nauthor = {Romaszkan, Wojciech},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {},\ntitle = {Efficient Machine Learning Acceleration at the Edge},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [6]                            J. Yang, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, A. Graening, V. K. Jacob, T. Li, P. Gupta, and S. Pamarti, &#8220;A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2023  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_76\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_76_block\"><pre><code class=\"tex bibtex\">@conference{W22,\nauthor = {Yang, Jiyue and Romaszkan, Wojciech and Graening, Alexander and Jacob, Vinod Kurian and Li, Tianmu and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, event-based camera, accelerator},\ntitle = {{A 14nm Stochastic-Compute-in-Memory Accelerator with In-Situ Stochastic Number Generator for Object Tracking Applications}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [7]                            T. Li, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, S. Pal, S. Pamarti, and P. Gupta, &#8220;REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2023  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_77\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_77_block\"><pre><code class=\"tex bibtex\">@conference{W23,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pal, Soumitra and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, CNN, neural networks},\ntitle = {{REX-SC: Range-Extended Stochastic Computing for Neural Network Acceleration}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c121.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Yang, T. Li, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, P. Gupta, and S. Pamarti, &#8220;A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor,&#8221; in <span style=\"font-style: italic\">IEEE Asian Solid-State Circuits Conference<\/span>,  2022, p. 2  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_66\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_66_block\"><pre><code class=\"tex bibtex\">@inproceedings{C121,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{IEEE Asian Solid-State Circuits Conference}},\ndoi = {},\nkeywords = {mledge},\nmonth = {November},\nnote = {},\npages = {2},\ntitle = {{A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c120.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Romaszkan<\/span>, T. Li, and P. Gupta, &#8220;SASCHA &#8211; Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2022, p. 12  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_65\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_65_block\"><pre><code class=\"tex bibtex\">@inproceedings{C120,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {October},\nnote = {Best paper nomination},\npages = {12},\ntitle = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j72.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Romaszkan<\/span>, T. Li, and P. Gupta, &#8220;SASCHA &#8211; Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,&#8221; , p. 12, 2022.  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_71\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_71_block\"><pre><code class=\"tex bibtex\">@article{J72,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ndoi = {},\nkeywords = {mledge},\nmonth = {October},\nnote = {Best paper nomination},\npages = {12},\ntitle = {{SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j70.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Romaszkan<\/span>, T. Li, R. Garg, J. Yang, S. Pamarti, and P. Gupta, &#8221; A 4.4-75 TOPS\/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator,&#8221; <span style=\"font-style: italic\">IEEE Solid State Circuits Letters<\/span>, 2022.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_70\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_70_block\"><pre><code class=\"tex bibtex\">@article{J70,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Garg, Rahul and Yang, Jiyue and Pamarti, Sudhakar and Gupta, Puneet},\njournal = {{IEEE Solid State Circuits Letters}},\nkeywords = {mledge},\nmonth = {August},\npublisher = {{IEEE}},\ntitle = {{ A 4.4-75 TOPS\/W 14nm Programmable, Performance- and Precision-Tunable All-Digital Stochastic Computing Neural Network Inference Accelerator}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [12]                            A. Graening, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, S. Pamarti, and P. Gupta, &#8220;Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_75\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_75_block\"><pre><code class=\"tex bibtex\">@conference{W21,\nauthor = {Graening, Alexander and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, event-based camera, accelerator},\ntitle = {{Sparsity-Aware Processing of Event-Based Neuromorphic Data with Stochastic Computing}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [13]                            J. Yang, T. Li, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, P. Gupta, and S. Pamarti, &#8220;A 1.84-7.96TOPS\/W 65nm DAC\/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2022  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_79\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_79_block\"><pre><code class=\"tex bibtex\">@conference{W25,\nauthor = {Yang, Jiyue and Li, Tianmu and Romaszkan, Wojciech and Gupta, Puneet and Pamarti, Sudhakar},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, CNN, neural networks, accelerator},\ntitle = {{A 1.84-7.96TOPS\/W 65nm DAC\/ADC-Free Stochastic Compute-In-Memory CNN Accelerator with 8-bit Precision and Robust Operation Under 0.7V-1.05V Supply}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c112.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Li, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, S. Pamarti, and P. Gupta, &#8220;GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_63\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_63_block\"><pre><code class=\"tex bibtex\">@inproceedings{C112,\nauthor = {Li, Tianmu and Romaszkan, Wojciech and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {},\nkeywords = {mledge},\nmonth = {February},\nnote = {},\npages = {},\ntitle = {{GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c113.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Li, <span class=\"papercite_highlight\">W. Romaszkan<\/span>, A. Graening, and P. Gupta, &#8220;SWIS &#8211; Shared Weight bIt Sparsity for Efficient Neural Network Acceleration,&#8221; in <span style=\"font-style: italic\">International Research Symposium on Tiny Machine Learning (tinyML)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_64\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_64_block\"><pre><code class=\"tex bibtex\">@inproceedings{C113,\nauthor = {Li, Shurui and Romaszkan, Wojciech and Graening, Alexander and Gupta, Puneet},\nbooktitle = {{International Research Symposium on Tiny Machine Learning (tinyML)}},\ndoi = {},\nkeywords = {mledge, quantization, systolic array},\nmonth = {March},\nnote = {},\npages = {},\ntitle = {{SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [16]                            <span class=\"papercite_highlight\">W. Romaszkan<\/span>, T. Li, J. Yang, A. Lee, D. Wu, K. Wang, S. Pamarti, and P. Gupta, &#8220;Machine Learning at the Edge Using Spintronic Stochastic Computing,&#8221; in <span style=\"font-style: italic\">Government Microcircuit Applications and Critical Technology Conference (GOMACTech)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_78\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_78_block\"><pre><code class=\"tex bibtex\">@conference{W24,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Yang, Jiyue and Lee, Albert and Wu, Di and Wang, Kang and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{Government Microcircuit Applications and Critical Technology Conference (GOMACTech)}},\nkeywords = {stochastic computing, CNN, neural networks},\ntitle = {{Machine Learning at the Edge Using Spintronic Stochastic Computing}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c109.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.23919\/DATE48585.2020.9116289' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">W. Romaszkan<\/span>, T. Li, T. Melton, S. Pamarti, and P. Gupta, &#8220;ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2020, pp. 768-773  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_62\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_62_block\"><pre><code class=\"tex bibtex\">@inproceedings{C109,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Melton, Tristan and Pamarti, Sudhakar and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ndoi = {10.23919\/DATE48585.2020.9116289},\nkeywords = {mledge},\nmonth = {March},\nnote = {Best paper nomination},\npages = {768-773},\ntitle = {{ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j63.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Romaszkan<\/span>, T. Li, and P. Gupta, &#8220;3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning,&#8221; <span style=\"font-style: italic\">ACM Transactions on Embedded Computing Systems (TECS)<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_69\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_69_block\"><pre><code class=\"tex bibtex\">@article{J63,\nauthor = {Romaszkan, Wojciech and Li, Tianmu and Gupta, Puneet},\njournal = {{ACM Transactions on Embedded Computing Systems (TECS)}},\nkeywords = {mledge, 3pxnet},\nmonth = {November},\npublisher = {ACM},\ntitle = {{3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:23% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"1000\" height=\"856\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/Saptadeep_Pal.jpg\" alt=\"\" class=\"wp-image-89 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Saptadeep Pal <a rel=\"noopener noreferrer\" href=\"https:\/\/www.linkedin.com\/in\/saptadeeppal\/\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\"><\/a>  <a rel=\"noopener noreferrer\" href=\"https:\/\/scholar.google.com\/citations?user=uBnEf3EAAAAJ&amp;hl=en\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" width=\"30\" height=\"30\" src=\"\/wp-content\/plugins\/papercite\/img\/icons8-google-scholar.svg\"><\/a><\/p>\n\n\n\n<p><strong>Contact:<\/strong> &#x73;&#x61;&#x70;&#x74;&#x61;&#x64;&#x65;&#x65;&#112;&#64;&#117;&#99;&#108;&#97;&#46;edu\n\n\n\n<p><strong>Research interests<\/strong>: Design Methodologies and Architectures for System Integration on Next Generation Interconnects, Development of Silicon Interconnect Fabric, Stochastic Computing, Technology Optimization<\/p>\n\n\n\n<p><strong>Industry experience:<\/strong> Nvidia<\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Stealth Mode Startup<\/p>\n\n\n\n<p><strong>PhD Thesis:<\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Pal, &#8220;Scale-out packageless processing,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_80\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_80_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH11,\nauthor = {Pal, Saptadeep},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {November},\ntitle = {Scale-Out Packageless Processing},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e3719b\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e3719b\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j85.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/TCAD.2025.3597570' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        A. Graening, J. Talukdar, <span class=\"papercite_highlight\">S. Pal<\/span>, K. Chakrabarty, and P. Gupta, &#8220;CATCH: a cost analysis tool for co-optimization of chiplet-based heterogeneous systems,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2025.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_95\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_95_block\"><pre><code class=\"tex bibtex\">@article{J85,\nauthor = {Graening, Alexander and Talukdar, Jonti and Pal, Saptadeep and Chakrabarty, Krishnendu and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/TCAD.2025.3597570},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ntitle = {{CATCH}: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems},\nyear = {2025}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j80.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1038\/s44287-024-00078-x' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">S. Pal<\/span>, A. Mallik, and P. Gupta, &#8220;System technology co-optimization for advanced integration,&#8221; <span style=\"font-style: italic\">Nature Reviews Electrical Engineering<\/span>, 2024.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_94\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_94_block\"><pre><code class=\"tex bibtex\">@article{J80,\nauthor = {Pal, S. and Mallik, A. and Gupta, P},\ndoi = {10.1038\/s44287-024-00078-x},\njournal = {{Nature Reviews Electrical Engineering}},\ntitle = {System technology co-optimization for advanced integration},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c124.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Graening, <span class=\"papercite_highlight\">S. Pal<\/span>, and P. Gupta, &#8220;Chiplets: How Small is too Small?,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2023, p. 6  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_87\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_87_block\"><pre><code class=\"tex bibtex\">@inproceedings{C124,\nauthor = {Graening, Alexander and Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ndoi = {},\nkeywords = {chiplets,wsi},\nmonth = {July},\nnote = {},\npages = {6},\ntitle = {{Chiplets: How Small is too Small?}},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j77.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1145\/3635867' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        N. Ardalani, <span class=\"papercite_highlight\">S. Pal<\/span>, and P. Gupta, &#8220;Deepflow: a cross-stack pathfinding framework for distributed ai systems,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_93\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_93_block\"><pre><code class=\"tex bibtex\">@article{J77,\nauthor = {Newsha Ardalani and Saptadeep Pal and Puneet Gupta},\ndoi = {10.1145\/3635867},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\ntitle = {DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c116.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Pal<\/span>, J. Liu, I. Alam, N. Cebry, H. Suhail, S. Bu, S. S. Iyer, S. Pamarti, R. Kumar, and P. Gupta, &#8220;Designing a 2048-Chiplet, 14336-Core Waferscale Processor,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_86\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_86_block\"><pre><code class=\"tex bibtex\">@inproceedings{C116,\nauthor = {Pal, Saptadeep and Liu, Jingyang and Alam, Irina and Cebry, Nicholas and Suhail, Haris and Bu, Shi and Iyer, Subramanian S. and Pamarti, Sudhakar and Kumar, Rakesh and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ndoi = {},\nkeywords = {wsi},\nmonth = {December},\nnote = {},\npages = {},\ntitle = {{Designing a 2048-Chiplet, 14336-Core Waferscale Processor}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Pal<\/span>, &#8220;Scale-out packageless processing,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_97\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_97_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH11,\nauthor = {Pal, Saptadeep},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {November},\ntitle = {Scale-Out Packageless Processing},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c114.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Pal<\/span>, K. Sahoo, I. Alam, H. Suhail, R. Kumar, S. Pamarti, P. Gupta, and S. S. Iyer, &#8220;I\/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_85\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_85_block\"><pre><code class=\"tex bibtex\">@inproceedings{C114,\nauthor = {Pal, Saptadeep and Sahoo, Krutikesh and Alam, Irina and Suhail, Haris and Kumar, Rakesh and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {wsi},\nmonth = {June},\nnote = {},\npages = {},\ntitle = {{I\/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c111.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Pal<\/span> and P. Gupta, &#8220;Pathfinding for 2.5D Interconnect Technologies,&#8221; in <span style=\"font-style: italic\">System-Level Interconnect &#8211; Problems and Pathfinding Workshop<\/span>, New York, NY, USA,  2020  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_84\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_84_block\"><pre><code class=\"tex bibtex\">@inproceedings{C111,\naddress = {New York, NY, USA},\nauthor = {Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{System-Level Interconnect - Problems and Pathfinding Workshop}},\nkeywords = {wsi},\nlocation = {San Diego, California},\nmonth = {November},\nnumpages = {8},\npublisher = {ACM},\nseries = {SLIP '20},\ntitle = {{Pathfinding for 2.5D Interconnect Technologies}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j66.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/ieeexplore.ieee.org\/document\/8998304' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">S. Pal<\/span>, D. Petrisko, R. Kumar, and P. Gupta, &#8220;Design Space Exploration for Chiplet Assembly Based Processors,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_92\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_92_block\"><pre><code class=\"tex bibtex\">@article{J66,\nauthor = {Pal, Saptadeep and Petrisko, Daniel and Kumar, Rakesh and Gupta, Puneet},\ndoi = {https:\/\/ieeexplore.ieee.org\/document\/8998304},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {{2.5-D integration, chiplet assembly, micro-architectural design space exploration (DSE), multichiplet optimization, wsi}},\npublisher = {{IEEE}},\ntitle = {{Design Space Exploration for Chiplet Assembly Based Processors}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c108.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1145\/3357526.3357533' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        I. Alam, <span class=\"papercite_highlight\">S. Pal<\/span>, and P. Gupta, &#8220;Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories,&#8221; in <span style=\"font-style: italic\">Proceedings of the International Symposium on Memory Systems<\/span>, New York, NY, USA,  2019, p. 85\u2013100  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_83\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_83_block\"><pre><code class=\"tex bibtex\">@inproceedings{C108,\nacmid = {3357533},\naddress = {New York, NY, USA},\nauthor = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{Proceedings of the International Symposium on Memory Systems}},\ndoi = {10.1145\/3357526.3357533},\nisbn = {978-1-4503-7206-0},\nkeywords = {memres},\nlocation = {Washington, District of Columbia},\nmonth = {September},\nnumpages = {16},\npages = {85--100},\npublisher = {ACM},\nseries = {MEMSYS '19},\ntitle = {{Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},\nurl = {http:\/\/doi.acm.org\/10.1145\/3357526.3357533},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j61.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Pal<\/span>, E. Ebrahimi, A. Zulfiqar, Y. Fu, V. Zhang, S. Migacz, D. Nellans, and P. Gupta, &#8220;Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training,&#8221; <span style=\"font-style: italic\">IEEE Micro<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_91\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_91_block\"><pre><code class=\"tex bibtex\">@article{J61,\nauthor = {Pal, Saptadeep and Ebrahimi, Eiman and Zulfiqar, Arslan and Fu, Yaosheng and Zhang, Victor and Migacz, Szymon and Nellans, David and Gupta, Puneet},\njournal = {{{IEEE Micro}}},\nmonth = {September},\npublisher = {IEEE},\ntitle = {{Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c107.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1109\/HPCA.2019.00042' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">S. Pal<\/span>, D. Petrisko, M. Tomei, S. S. Iyer, P. Gupta, and R. Kumar, &#8220;Architecting Waferscale Processors &#8211; A GPU Case Study,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on High-Performance Computer Architecture (HPCA)<\/span>,  2019, pp. 250-263  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_82\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_82_block\"><pre><code class=\"tex bibtex\">@inproceedings{C107,\nauthor = {Pal, Saptadeep and Petrisko, Daniel and Tomei, Matthew and Iyer, Subramanian S. and Gupta, Puneet and Kumar, Rakesh},\nbooktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},\ndoi = {10.1109\/HPCA.2019.00042},\nissn = {1530-0897},\nkeywords = {wsi},\nmonth = {February},\npages = {250-263},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C106_paper.pdf},\ntitle = {{Architecting Waferscale Processors - A GPU Case Study}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c100.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Pal<\/span>, D. Petrisko, A. Bajwa, S. S. Iyer, R. Kumar, and P. Gupta, &#8220;A Case for Packageless Processors,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on High-Performance Computer Architecture (HPCA)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_81\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_81_block\"><pre><code class=\"tex bibtex\">@inproceedings{C100,\nauthor = {Pal, Saptadeep and Petrisko, Daniel and Bajwa, Adeel and Iyer, Subramanian S. and Kumar, Rakesh and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on High-Performance Computer Architecture (HPCA)}},\nkeywords = {wsi},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C100_paper.pdf},\ntitle = {{A Case for Packageless Processors}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam, <span class=\"papercite_highlight\">S. Pal<\/span>, and P. Gupta, &#8220;Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_98\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_98_block\"><pre><code class=\"tex bibtex\">@conference{W15,\nauthor = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {memres,compression,ecc,memory,reliability,architecture,coding,systems,stt_ram},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W15_paper.pdf},\ntitle = {{Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c96.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c96_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            S. Jangam, <span class=\"papercite_highlight\">S. Pal<\/span>, A. Bajwa, S. Pamarti, P. Gupta, and S. S. Iyer, &#8220;Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_89\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_89_block\"><pre><code class=\"tex bibtex\">@inproceedings{C96,\nauthor = {Jangam, SivaChandra and Pal, Saptadeep and Bajwa, Adeel and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\nkeywords = {Silicon Interconnect Fabric; Thermal Compression Bonding; Fine Pitch Interconnect, SuperCHIPS, wsi},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C96_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C96_slides.pdf},\ntitle = {{L}atency, {B}andwidth and {P}ower {B}enefits of the {S}uper{CHIPS} {I}ntegration {S}cheme},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c95.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c95_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            S. Wang, <span class=\"papercite_highlight\">S. Pal<\/span>, T. Li, A. Pan, C. Grezes, K. P. Amiri, K. L. Wang, C. O. Chui, and P. Gupta, &#8220;Hybrid VC-MTJ\/CMOS Non-volatile Stochastic Logic for Efficient Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2017  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_88\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_88_block\"><pre><code class=\"tex bibtex\">@inproceedings{C95,\nauthor = {Wang, Shaodi and Pal, Saptadeep and Li, Tianmu and Pan, Andrew and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Chui, Chi On and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nkeywords = {mledge,Negative differential resistance, Magnetic tunnel junction, stochastic computing, stochastic bitstream generator, non-volatile computing},\nmonth = {March},\nnote = {Best paper nomination},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_slides.pdf},\ntitle = {{H}ybrid {VC-MTJ\/CMOS} {N}on-volatile {S}tochastic {L}ogic for {E}fficient {C}omputing},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip17.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Pal<\/span>, S. S. Iyer, and P. Gupta, &#8220;Advanced packaging and heterogeneous integration to reboot computing,&#8221; in <span style=\"font-style: italic\">IEEE International Conference on Rebooting Computing<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_90\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_90_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP17,\nauthor = {Pal, Saptadeep and Iyer, Subramanian S. and Gupta, Puneet},\nbooktitle = {{IEEE International Conference on Rebooting Computing}},\nkeywords = {wsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP17_paper.pdf},\ntitle = {Advanced Packaging and Heterogeneous Integration to Reboot Computing},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/mstr13_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">S. Pal<\/span>, &#8220;Supervia: relieving routing congestion using double-height vias,&#8221; Department of Electrical Engineering, University of California Los Angeles 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_96\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_96_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR13,\nauthor = {Pal, Saptadeep},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR13_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR13_slides.pdf},\ntitle = {Supervia: Relieving Routing Congestion using Double-height Vias},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:19% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"450\" height=\"531\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/Irina_1.jpg\" alt=\"\" class=\"wp-image-91 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Irina Alam <\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"https:\/\/web.archive.org\/web\/20180627072512\/&#x6d;&#x61;&#105;&#108;t&#x6f;&#x3a;&#x77;&#101;ic&#x68;&#x65;&#119;&#97;n&#x67;&#x40;&#x75;&#99;la&#x2e;&#x65;&#100;&#117;\"> <\/a> &#x20;&#32;i&#x72;&#105;n&#x61;&#49;&#64;&#x75;&#99;l&#x61;&#46;e&#x64;&#117; &#x20; <\/p>\n\n\n\n<p><strong>Research interests:<\/strong> Opportunistic memory architecture for power and performance benefits, Exploring efficient memory error resilience techniques<\/p>\n\n\n\n<p><strong>Industry experience:<\/strong> Micron, Google<\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Apple<\/p>\n\n\n\n<p><strong>PhD Thesis:<\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           I. Alam, &#8220;Lightweight opportunistic memory resilience,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_99\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_99_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH10,\nauthor = {Alam, Irina},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {August},\ntitle = {Lightweight Opportunistic Memory Resilience},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<\/div><\/div>\n\n\n\n<p class=\"has-text-align-center\"><code><span class=\"collapseomatic \" id=\"id69f27e4e371d1\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e371d1\" class=\"collapseomatic_content \"><\/code><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j78.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">I. Alam<\/span> and P. Gupta, &#8220;Achieving dram-like pcm by trading off capacity for latency,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computers<\/span>, 2024.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_114\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_114_block\"><pre><code class=\"tex bibtex\">@article{J78,\nauthor = {Irina Alam and Puneet Gupta},\njournal = {{IEEE Transactions on Computers}},\ntitle = {Achieving DRAM-like PCM By Trading Off Capacity For Latency},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [2]                    <a href='http:\/\/dx.doi.org\/10.1109\/TED.2022.3228831' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        A. Lee, <span class=\"papercite_highlight\">I. Alam<\/span>, J. Yang, D. Wu, S. Pamarti, P. Gupta, and K. L. Wang, &#8220;Low-energy shared-current write schemes for voltage-controlled spin-orbit-torque memory,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electron Devices<\/span>, vol. 70, iss. 2, pp. 478-484, 2023.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_113\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_113_block\"><pre><code class=\"tex bibtex\">@article{J76,\nauthor = {Lee, Albert and Alam, Irina and Yang, Jiyue and Wu, Di and Pamarti, Sudhakar and Gupta, Puneet and Wang, Kang L.},\ndoi = {10.1109\/TED.2022.3228831},\njournal = {{IEEE Transactions on Electron Devices}},\nnumber = {2},\npages = {478-484},\ntitle = {Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory},\nvolume = {70},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c118.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">I. Alam<\/span> and P. Gupta, &#8220;COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors,&#8221; in <span style=\"font-style: italic\">IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)<\/span>,  2022, p. 13  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_108\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_108_block\"><pre><code class=\"tex bibtex\">@inproceedings{C118,\nauthor = {Alam, Irina and Gupta, Puneet},\nbooktitle = {{IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)}},\ndoi = {},\nkeywords = {},\nmonth = {June},\nnote = {},\npages = {13},\ntitle = {{COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j69.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">I. Alam<\/span>, T. Li, S. Brock, and P. Gupta, &#8220;DRDebug: Automated Design Rule Debugging,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2022.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_112\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_112_block\"><pre><code class=\"tex bibtex\">@article{J69,\nauthor = {Alam, Irina and Li, Tianmu and Brock, Sean and Gupta, Puneet},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\npublisher = {{IEEE}},\ntitle = {{DRDebug: Automated Design Rule Debugging}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c116.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal, J. Liu, <span class=\"papercite_highlight\">I. Alam<\/span>, N. Cebry, H. Suhail, S. Bu, S. S. Iyer, S. Pamarti, R. Kumar, and P. Gupta, &#8220;Designing a 2048-Chiplet, 14336-Core Waferscale Processor,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_107\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_107_block\"><pre><code class=\"tex bibtex\">@inproceedings{C116,\nauthor = {Pal, Saptadeep and Liu, Jingyang and Alam, Irina and Cebry, Nicholas and Suhail, Haris and Bu, Shi and Iyer, Subramanian S. and Pamarti, Sudhakar and Kumar, Rakesh and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ndoi = {},\nkeywords = {wsi},\nmonth = {December},\nnote = {},\npages = {},\ntitle = {{Designing a 2048-Chiplet, 14336-Core Waferscale Processor}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">I. Alam<\/span>, &#8220;Lightweight opportunistic memory resilience,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_116\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_116_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH10,\nauthor = {Alam, Irina},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {August},\ntitle = {Lightweight Opportunistic Memory Resilience},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c114.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal, K. Sahoo, <span class=\"papercite_highlight\">I. Alam<\/span>, H. Suhail, R. Kumar, S. Pamarti, P. Gupta, and S. S. Iyer, &#8220;I\/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor,&#8221; in <span style=\"font-style: italic\">IEEE Electronic Components and Technology Conference (ECTC)<\/span>,  2021  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_106\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_106_block\"><pre><code class=\"tex bibtex\">@inproceedings{C114,\nauthor = {Pal, Saptadeep and Sahoo, Krutikesh and Alam, Irina and Suhail, Haris and Kumar, Rakesh and Pamarti, Sudhakar and Gupta, Puneet and Iyer, Subramanian S.},\nbooktitle = {{IEEE Electronic Components and Technology Conference (ECTC)}},\ndoi = {},\nkeywords = {wsi},\nmonth = {June},\nnote = {},\npages = {},\ntitle = {{I\/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor}},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c110.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">I. Alam<\/span> and P. Gupta, &#8220;SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge,&#8221; in <span style=\"font-style: italic\">Proceedings of the International Symposium on Memory Systems<\/span>, New York, NY, USA,  2020  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_105\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_105_block\"><pre><code class=\"tex bibtex\">@inproceedings{C110,\naddress = {New York, NY, USA},\nauthor = {Alam, Irina and Gupta, Puneet},\nbooktitle = {{Proceedings of the International Symposium on Memory Systems}},\nkeywords = {memres},\nlocation = {Washington, District of Columbia},\nmonth = {September},\nnumpages = {13},\npublisher = {ACM},\nseries = {MEMSYS '20},\ntitle = {{SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [9]                            <span class=\"papercite_highlight\">I. Alam<\/span>, L. Dolecek, and P. Gupta, &#8220;Lightweight software-defined error correction for memories,&#8221; in <span style=\"font-style: italic\">Dependable Embedded Systems<\/span>, Springer, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_100\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_100_block\"><pre><code class=\"tex bibtex\">@incollection{B3,\nauthor = {Alam, Irina and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{Dependable Embedded Systems}},\npublisher = {Springer},\ntitle = {Lightweight Software-Defined Error Correction for Memories},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j62.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Schoeny, F. Sala, M. Gottscho, <span class=\"papercite_highlight\">I. Alam<\/span>, P. Gupta, and L. Dolecek, &#8220;Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Information Theory<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_111\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_111_block\"><pre><code class=\"tex bibtex\">@article{J62,\nauthor = {Schoeny, Clayton and Sala, Frederic and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},\njournal = {{IEEE Transactions on Information Theory}},\nkeywords = {memres},\nmonth = {October},\ntitle = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c108.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1145\/3357526.3357533' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">I. Alam<\/span>, S. Pal, and P. Gupta, &#8220;Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories,&#8221; in <span style=\"font-style: italic\">Proceedings of the International Symposium on Memory Systems<\/span>, New York, NY, USA,  2019, p. 85\u2013100  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_104\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_104_block\"><pre><code class=\"tex bibtex\">@inproceedings{C108,\nacmid = {3357533},\naddress = {New York, NY, USA},\nauthor = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{Proceedings of the International Symposium on Memory Systems}},\ndoi = {10.1145\/3357526.3357533},\nisbn = {978-1-4503-7206-0},\nkeywords = {memres},\nlocation = {Washington, District of Columbia},\nmonth = {September},\nnumpages = {16},\npages = {85--100},\npublisher = {ACM},\nseries = {MEMSYS '19},\ntitle = {{Compression with multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},\nurl = {http:\/\/doi.acm.org\/10.1145\/3357526.3357533},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c106.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Schoeny, <span class=\"papercite_highlight\">I. Alam<\/span>, M. Gottscho, P. Gupta, and L. Dolecek, &#8220;Error Correction and Detection for Computing Memories Using System Side Information,&#8221; in <span style=\"font-style: italic\">IEEE Information Theory Workshop (ITW)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_103\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_103_block\"><pre><code class=\"tex bibtex\">@inproceedings{C106,\nauthor = {Schoeny, Clayton and Alam, Irina and Gottscho, Mark and Gupta, Puneet and Dolecek, Lara},\nbooktitle = {{IEEE Information Theory Workshop (ITW)}},\nkeywords = {memres},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C108_paper.pdf},\ntitle = {{Error Correction and Detection for Computing Memories Using System Side Information}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c104.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">I. Alam<\/span>, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Parity++: Lightweight Error Correction for Last Level Caches,&#8221; in <span style=\"font-style: italic\">IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_102\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_102_block\"><pre><code class=\"tex bibtex\">@inproceedings{C104,\nauthor = {Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)}},\nkeywords = {memres},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C104_paper.pdf},\ntitle = {{Parity++: Lightweight Error Correction for Last Level Caches}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">I. Alam<\/span>, &#8220;Lightweight fault tolerance in sram based on-chip memories,&#8221; Department of Electrical and Computer Engineering, University of California Los Angeles 2018.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_115\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_115_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH4,\nauthor = {Alam, Irina},\ninstitution = {Department of Electrical and Computer Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH4_paper.pdf},\ntitle = {Lightweight Fault Tolerance in SRAM Based On-Chip Memories},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">I. Alam<\/span>, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Parity++: Lightweight Error Correction for Last Level Caches,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2018  &#8211; <b>Best of SELSE<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_117\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_117_block\"><pre><code class=\"tex bibtex\">@conference{W14,\nauthor = {Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {memres,parity,ecc,memory,reliability,architecture,coding,systems,caches},\nnote = {Best of SELSE},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W14_paper.pdf},\ntitle = {{Parity++: Lightweight Error Correction for Last Level Caches}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">I. Alam<\/span>, S. Pal, and P. Gupta, &#8220;Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_118\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_118_block\"><pre><code class=\"tex bibtex\">@conference{W15,\nauthor = {Alam, Irina and Pal, Saptadeep and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {memres,compression,ecc,memory,reliability,architecture,coding,systems,stt_ram},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W15_paper.pdf},\ntitle = {{Compression with Multi-ECC: Enhanced Error Resiliency for Magnetic Memories}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c101.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Schoeny, F. Sala, M. Gottscho, <span class=\"papercite_highlight\">I. Alam<\/span>, P. Gupta, and L. Dolecek, &#8220;Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories,&#8221; in <span style=\"font-style: italic\">IEEE Information Theory Workshop (ITW)<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_101\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_101_block\"><pre><code class=\"tex bibtex\">@inproceedings{C101,\nauthor = {Schoeny, Clayton and Sala, Fredric and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},\nbooktitle = {{IEEE Information Theory Workshop (ITW)}},\nkeywords = {memres},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C101_paper.pdf},\ntitle = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [18]               <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c98_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               M. Gottscho, <span class=\"papercite_highlight\">I. Alam<\/span>, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Low-Cost Memory Fault Tolerance for IoT Devices,&#8221; , 2017.  &#8211; <b>Best paper award<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_109\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_109_block\"><pre><code class=\"tex bibtex\">@article{C98,\nauthor = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},\nkeywords = {memres},\nmonth = {October},\nnote = {Best paper award},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J54_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C98_slides.pptx},\ntitle = {{Low-Cost Memory Fault Tolerance for IoT Devices}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j54.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Gottscho, <span class=\"papercite_highlight\">I. Alam<\/span>, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Low-Cost Memory Fault Tolerance for IoT Devices,&#8221; <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_110\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_110_block\"><pre><code class=\"tex bibtex\">@article{J54,\nauthor = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\njournal = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},\nkeywords = {memres},\nmonth = {October},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J54_paper.pdf},\ntitle = {{Low-Cost Memory Fault Tolerance for IoT Devices}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><code><\/div><\/code><\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:19% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"242\" height=\"280\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/weichewang.jpg\" alt=\"\" class=\"wp-image-94 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Wei-Che Wang<\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"https:\/\/web.archive.org\/web\/20180627072512\/&#x6d;&#x61;&#x69;&#x6c;&#116;&#111;:we&#x69;&#x63;&#x68;&#x65;&#119;&#97;ng&#64;&#x75;&#x63;&#x6c;&#x61;&#46;&#101;&#100;u\"> <\/a> &#32;&#x20;&#119;&#x65;i&#99;&#x68;&#101;&#x77;a&#x6e;g&#64;&#x75;&#99;&#x6c;a&#x2e;&#x65;&#100;&#x75; &#x20; <\/p>\n\n\n\n<p><strong>Research interests:<\/strong> Development of computational techniques and models for exploring and optimizing semiconductor technologies. <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Nvidia<\/p>\n\n\n\n<p><strong>PhD Thesis:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           W. Wang, &#8220;Hardware-enabled design for security (dfs) solutions,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2018. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_119\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_119_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH9,\nauthor = {Wang, Wei-Che},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH8_paper.pdf},\ntitle = {Hardware-Enabled Design for Security (DFS) Solutions},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>   <\/p>\n<\/div><\/div>\n\n\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37202\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37202\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j64.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/TCAD.2019.2957359' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        <span class=\"papercite_highlight\">W. Wang<\/span>, Y. Wu, and P. Gupta, &#8220;Reverse Engineering for 2.5D Split Manufactured ICs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_127\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_127_block\"><pre><code class=\"tex bibtex\">@article{J64,\nauthor = {Wang, Wei-Che and Wu, Yizhang and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/TCAD.2019.2957359},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\npublisher = {{IEEE}},\ntitle = {{Reverse Engineering for 2.5D Split Manufactured ICs}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j60.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Wang<\/span>, Y. Yona, Y. Wu, S. Diggavi, and P. Gupta, &#8220;SLATE: A Secure Lightweight Entity Authentication Hardware Primitive,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Information Forensics and Security<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_126\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_126_block\"><pre><code class=\"tex bibtex\">@article{J60,\nauthor = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Diggavi, Suhas and Gupta, Puneet},\njournal = {{{IEEE Transactions on Information Forensics and Security}}},\nmonth = {May},\npublisher = {IEEE},\ntitle = {{SLATE: A Secure Lightweight Entity Authentication Hardware Primitive}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j57.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Wang<\/span>, C. Zhao, and P. Gupta, &#8220;Assessing Layout Density Benefits of Vertical Channel Devices,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2018.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_125\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_125_block\"><pre><code class=\"tex bibtex\">@article{J57,\nauthor = {Wang, Wei-Che and Zhao, Charles and Gupta, Puneet},\nissue = {},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nmonth = {},\ntitle = {{Assessing Layout Density Benefits of Vertical Channel Devices}},\nvolume = {},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Wang<\/span>, &#8220;Hardware-enabled design for security (dfs) solutions,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2018.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_128\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_128_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH9,\nauthor = {Wang, Wei-Che},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH8_paper.pdf},\ntitle = {Hardware-Enabled Design for Security (DFS) Solutions},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j56.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Wang<\/span>, Y. Yona, S. Diggavi, and P. Gupta, &#8220;Design and Analysis of Stability-Guaranteed PUFs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Information Forensics and Security (TIFS)<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_124\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_124_block\"><pre><code class=\"tex bibtex\">@article{J56,\nauthor = {Wang, Wei-Che and Yona, Yair and Diggavi, Suhas and Gupta, Puneet},\njournal = {{IEEE Transactions on Information Forensics and Security (TIFS)}},\nmonth = {November},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J56_paper.pdf},\ntitle = {{Design and Analysis of Stability-Guaranteed PUFs}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c99.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Wang<\/span>, Y. Yona, Y. Wu, S. Hung, S. Diggavi, and P. Gupta, &#8220;Implementation of Stable PUFs Using Gate Oxide Breakdown,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST)<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_122\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_122_block\"><pre><code class=\"tex bibtex\">@inproceedings{C99,\nauthor = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Hung, Szu-Yao and Diggavi, Suhas and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST)}},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C99_paper.pdf},\ntitle = {{Implementation of Stable PUFs Using Gate Oxide Breakdown}},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c94.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Wang<\/span>, Y. Yona, S. Diggavi, and P. Gupta, &#8220;LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Hardware Oriented Security and Trust (HOST)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_121\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_121_block\"><pre><code class=\"tex bibtex\">@inproceedings{C94,\nauthor = {Wang, Wei-Che and Yona, Yair and Diggavi, Suhas and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Hardware Oriented Security and Trust (HOST)}},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C94_paper.pdf},\ntitle = {{LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity}},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j41.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Wang<\/span> and P. Gupta, &#8220;Efficient Layout Generation and Design Evaluation of Vertical Channel Devices,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_123\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_123_block\"><pre><code class=\"tex bibtex\">@article{J41,\nauthor = {Wang, Wei-Che and Gupta, Puneet},\nissue = {},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J41_paper.pdf},\ntitle = {{Efficient Layout Generation and Design Evaluation of Vertical Channel Devices}},\nvolume = {},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c81.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">W. Wang<\/span> and P. Gupta, &#8220;Efficient Layout Generation and Evaluation of Vertical Channel Devices,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_120\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_120_block\"><pre><code class=\"tex bibtex\">@inproceedings{C81,\nauthor = {Wang, Wei-Che and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C81},\nkeywords = {dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C81_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C81_slides.pdf},\ntitle = {{E}fficient {L}ayout {G}eneration and {E}valuation of {V}ertical {C}hannel {D}evices},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:19% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"217\" height=\"335\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/YasmineBadr.jpg\" alt=\"\" class=\"wp-image-133 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Yasmine Badr<\/p>\n\n\n\n<p><strong>Contact<\/strong>:   &#32;&#121;&#x62;&#x61;&#x64;r &#65;&#84;&#x20;&#x75;&#x63;l&#97;&#32;&#68;&#x4f;&#x54;&#x20;e&#100;&#117;&#x20;&#x20;  <\/p>\n\n\n\n<p><strong>Research interests<\/strong>: Algorithms and Computational methods for Design and Technology Co-optimization<\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Meta<\/p>\n\n\n\n<p><strong>PhD Thesis: <\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Badr, &#8220;Co-optimization of restrictive patterning technologies and design,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_129\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_129_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH8,\nauthor = {Badr, Yasmine},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH8_paper.pdf},\ntitle = {Co-optimization of Restrictive Patterning Technologies and Design},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n<\/div><\/div>\n\n\n<\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37230\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37230\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c102.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c102_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               A. Deng, <span class=\"papercite_highlight\">Y. Badr<\/span>, and P. Gupta, &#8220;Dynamic programming approach to adaptive slicing for optimization under a global volumetric error constraint,&#8221; in <span style=\"font-style: italic\">SPIE Laser 3D Manufacturing V<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_130\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_130_block\"><pre><code class=\"tex bibtex\">@inproceedings{C102,\nauthor = {Deng, Andrew and Badr, Yasmine and Gupta, Puneet},\nbooktitle = {{SPIE Laser 3D Manufacturing V}},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C102_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C102_slides.pptx},\ntitle = {Dynamic programming approach to adaptive slicing for optimization under a global volumetric error constraint},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c97.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">Y. Badr<\/span> and P. Gupta, &#8220;Technology Path-finding for Directed Self-assembly for Via Layers&#8221;,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_135\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_135_block\"><pre><code class=\"tex bibtex\">@inproceedings{C97,\nauthor = {Badr, Yasmine and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C97_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C97_slides.pdf},\ntitle = {{T}echnology {P}ath-finding for {D}irected {S}elf-assembly for {V}ia {L}ayers\"},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j52.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">Y. Badr<\/span> and P. Gupta, &#8220;Technology path-finding framework for directed-self assembly for via layers,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_140\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_140_block\"><pre><code class=\"tex bibtex\">@article{J52,\nauthor = {Badr, Yasmine and Gupta, Puneet},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J52_paper.pdf},\ntitle = {Technology path-finding framework for directed-self assembly for via layers},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">Y. Badr<\/span>, &#8220;Co-optimization of restrictive patterning technologies and design,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_141\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_141_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH8,\nauthor = {Badr, Yasmine},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH8_paper.pdf},\ntitle = {Co-optimization of Restrictive Patterning Technologies and Design},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j48.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">Y. Badr<\/span>, A. Torres, and P. Gupta, &#8220;Mask Assignment and Dsa Grouping for DSA-MP Hybrid Lithography for sub-7nm Contact\/Via Holes,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_139\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_139_block\"><pre><code class=\"tex bibtex\">@article{J48,\nauthor = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},\ncategory = {J48},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J48_paper.pdf},\ntitle = {{M}ask {A}ssignment and {D}SA {G}rouping for {DSA-MP} {H}ybrid {L}ithography for sub-7nm {C}ontact\/{V}ia {H}oles},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j45.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Zhu, <span class=\"papercite_highlight\">Y. Badr<\/span>, S. Wang, S. Iyer, and P. Gupta, &#8220;Assessing Benefits of a Buried Interconnect Layer in Digital Designs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_138\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_138_block\"><pre><code class=\"tex bibtex\">@article{J45,\nauthor = {Zhu, Liheng and Badr, Yasmine and Wang, Shaodi and Iyer, Subramanian and Gupta, Puneet},\ncategory = {J45},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J45_paper.pdf},\ntitle = {Assessing {B}enefits of a {B}uried {I}nterconnect {L}ayer in {D}igital {D}esigns},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c86.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c86_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">Y. Badr<\/span>, A. Torres, and P. Gupta, &#8220;Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts\/Vias,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_134\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_134_block\"><pre><code class=\"tex bibtex\">@inproceedings{C86,\nauthor = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C86_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C86_slides.pdf},\ntitle = { {M}ask {A}ssignment and {S}ynthesis of {DSA}-{MP} {H}ybrid {L}ithography for sub-7nm {C}ontacts\/{V}ias},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c85.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">Y. Badr<\/span>, A. Torres, and P. Gupta, &#8220;Incorporating DSA in multipatterning semiconductor manufacturing technologies,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_133\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_133_block\"><pre><code class=\"tex bibtex\">@inproceedings{C85,\nauthor = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C85_paper.pdf},\ntitle = { {I}ncorporating {DSA} in {m}ultipatterning {s}emiconductor {m}anufacturing {t}echnologies},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c78.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c78_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">Y. Badr<\/span>, K. Ma, and P. Gupta, &#8220;Layout Pattern-driven Design Rule Evaluation,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_132\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_132_block\"><pre><code class=\"tex bibtex\">@inproceedings{C78,\nauthor = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C78_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C78_slides.pdf},\ntitle = {{L}ayout {P}attern-driven {D}esign {R}ule {E}valuation},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c74.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c74_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, <span class=\"papercite_highlight\">Y. Badr<\/span>, M. Gupta, N. Jin, and P. Gupta, &#8220;Comprehensive Die-level Assessment of Design Rules and Layouts,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_131\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_131_block\"><pre><code class=\"tex bibtex\">@inproceedings{C74,\nauthor = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {dats,dre},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_slides.pdf},\ntitle = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip16.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, <span class=\"papercite_highlight\">Y. Badr<\/span>, and P. Gupta, &#8220;Pattern-restricted design at 10nm and beyond,&#8221; in <span style=\"font-style: italic\">Proc. IEEE International Conference on Computer Design<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_136\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_136_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP16,\nauthor = { Ghaida, Rani S. and Badr, Yasmine and Gupta, Puneet},\nbooktitle = {{Proc. IEEE International Conference on Computer Design}},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP16_paper.pdf},\ntitle = {Pattern-restricted design at 10nm and beyond},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j36.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">Y. Badr<\/span>, K. Ma, and P. Gupta, &#8220;Layout pattern-driven design rule evaluation,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_137\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_137_block\"><pre><code class=\"tex bibtex\">@article{J36,\nauthor = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J36_paper.pdf},\ntitle = {Layout Pattern-driven Design Rule Evaluation},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:19% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"2448\" height=\"3264\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/mark5.jpg\" alt=\"\" class=\"wp-image-189 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Mark Gottscho<\/p>\n\n\n\n<p><strong>Contact<\/strong>:  &#x20;&#32;&#x6d;&#x67;&#111;&#x74;&#x74;&#115;&#x63;&#x68;&#111;&#x40;&#x75;c&#x6c;&#x61;&#46;&#x65;&#100;u&#x20;&#32; <\/p>\n\n\n\n<p><strong>Research interests:<\/strong> Opportunistic memory architectures and systems in presence of variability.<\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> SambaNova Systems<\/p>\n\n\n\n<p><strong>PhD Thesis: <\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           M. W. Gottscho, &#8220;Opportunistic memory systems in presence of hardware variability,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_142\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_142_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH7,\nauthor = {Gottscho, Mark William},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {computer architecture, memory systems, variation-aware, hardware\/software interface, reliability, error-correcting codes, caches, scratchpads, SRAM, DRAM, supercomputers, IoT, embedded systems, electronic design auomation, CAD, EDA, operating systems, Linux, tools, benchmarks, resiliency, approximate computing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH7_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH7_slides.pdf},\ntitle = {Opportunistic Memory Systems in Presence of Hardware Variability},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>  <\/p>\n<\/div><\/div>\n\n\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e3726d\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e3726d\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j62.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Schoeny, F. Sala, <span class=\"papercite_highlight\">M. Gottscho<\/span>, I. Alam, P. Gupta, and L. Dolecek, &#8220;Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Information Theory<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_160\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_160_block\"><pre><code class=\"tex bibtex\">@article{J62,\nauthor = {Schoeny, Clayton and Sala, Frederic and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},\njournal = {{IEEE Transactions on Information Theory}},\nkeywords = {memres},\nmonth = {October},\ntitle = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c106.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Schoeny, I. Alam, <span class=\"papercite_highlight\">M. Gottscho<\/span>, P. Gupta, and L. Dolecek, &#8220;Error Correction and Detection for Computing Memories Using System Side Information,&#8221; in <span style=\"font-style: italic\">IEEE Information Theory Workshop (ITW)<\/span>,  2018  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_144\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_144_block\"><pre><code class=\"tex bibtex\">@inproceedings{C106,\nauthor = {Schoeny, Clayton and Alam, Irina and Gottscho, Mark and Gupta, Puneet and Dolecek, Lara},\nbooktitle = {{IEEE Information Theory Workshop (ITW)}},\nkeywords = {memres},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C108_paper.pdf},\ntitle = {{Error Correction and Detection for Computing Memories Using System Side Information}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c101.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Schoeny, F. Sala, <span class=\"papercite_highlight\">M. Gottscho<\/span>, I. Alam, P. Gupta, and L. Dolecek, &#8220;Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories,&#8221; in <span style=\"font-style: italic\">IEEE Information Theory Workshop (ITW)<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_143\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_143_block\"><pre><code class=\"tex bibtex\">@inproceedings{C101,\nauthor = {Schoeny, Clayton and Sala, Fredric and Gottscho, Mark and Alam, Irina and Gupta, Puneet and Dolecek, Lara},\nbooktitle = {{IEEE Information Theory Workshop (ITW)}},\nkeywords = {memres},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C101_paper.pdf},\ntitle = {{Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories}},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [4]               <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c98_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               <span class=\"papercite_highlight\">M. Gottscho<\/span>, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Low-Cost Memory Fault Tolerance for IoT Devices,&#8221; , 2017.  &#8211; <b>Best paper award<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_151\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_151_block\"><pre><code class=\"tex bibtex\">@article{C98,\nauthor = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},\nkeywords = {memres},\nmonth = {October},\nnote = {Best paper award},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J54_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C98_slides.pptx},\ntitle = {{Low-Cost Memory Fault Tolerance for IoT Devices}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j54.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">M. Gottscho<\/span>, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Low-Cost Memory Fault Tolerance for IoT Devices,&#8221; <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_159\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_159_block\"><pre><code class=\"tex bibtex\">@article{J54,\nauthor = {Gottscho, Mark and Alam, Irina and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\njournal = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS)}},\nkeywords = {memres},\nmonth = {October},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J54_paper.pdf},\ntitle = {{Low-Cost Memory Fault Tolerance for IoT Devices}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/phdth7_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            M. W. Gottscho, &#8220;Opportunistic memory systems in presence of hardware variability,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_162\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_162_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH7,\nauthor = {Gottscho, Mark William},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {computer architecture, memory systems, variation-aware, hardware\/software interface, reliability, error-correcting codes, caches, scratchpads, SRAM, DRAM, supercomputers, IoT, embedded systems, electronic design auomation, CAD, EDA, operating systems, Linux, tools, benchmarks, resiliency, approximate computing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH7_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH7_slides.pdf},\ntitle = {Opportunistic Memory Systems in Presence of Hardware Variability},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j46.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">M. Gottscho<\/span>, M. Shoaib, S. Govindan, B. Sharma, D. Wang, and P. Gupta, &#8220;Measuring the Impact of Memory Errors on Application Performance,&#8221; <span style=\"font-style: italic\">IEEE Computer Architecture Letters (CAL)<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_158\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_158_block\"><pre><code class=\"tex bibtex\">@article{J46,\nauthor = {Gottscho, Mark and Shoaib, Mohammed and Govindan, Sriram and Sharma, Bikash and Wang, Di and Gupta, Puneet},\nissue = {},\njournal = {{IEEE Computer Architecture Letters (CAL)}},\nkeywords = {memres},\nmonth = {August},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J46_paper.pdf},\ntitle = {{Measuring the Impact of Memory Errors on Application Performance}},\nvolume = {},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [8]                            <span class=\"papercite_highlight\">M. Gottscho<\/span>, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Software-Defined Error-Correcting Codes,&#8221; in <span style=\"font-style: italic\">IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_150\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_150_block\"><pre><code class=\"tex bibtex\">@conference{C93,\nauthor = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)}},\nkeywords = {ecc,memory,reliability,architecture,coding,systems,dram,caches,memres},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_slides.pptx},\ntitle = {{Software-Defined Error-Correcting Codes}},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c91.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c91_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">M. Gottscho<\/span>, S. Govindan, B. Sharma, M. Shoaib, and P. Gupta, &#8220;X-Mem: A Cross-Platform and Extensible Memory Characterization Tool for the Cloud,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_149\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_149_block\"><pre><code class=\"tex bibtex\">@inproceedings{C91,\nauthor = {Gottscho, Mark and Govindan, Sriram and Sharma, Bikash and Shoaib, Mohammed and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)}},\nkeywords = {},\nmonth = {April},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C91_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C91_slides.pdf},\ntitle = {{X}-{M}em: {A} {C}ross-{P}latform and {E}xtensible {M}emory {C}haracterization {T}ool for the {C}loud},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c89.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c89_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               Q. Zhang, L. Lai, <span class=\"papercite_highlight\">M. Gottscho<\/span>, and P. Gupta, &#8220;Multi-Story Power Distribution Networks for GPUs,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_148\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_148_block\"><pre><code class=\"tex bibtex\">@inproceedings{C89,\nauthor = {Zhang, Qixiang and Lai, Liangzhen and Gottscho, Mark and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C89_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C89_slides.pptx},\ntitle = {{M}ulti-{S}tory {P}ower {D}istribution {N}etworks for {GPU}s},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/w13_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               <span class=\"papercite_highlight\">M. Gottscho<\/span>, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Software-Defined Error-Correcting Codes,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2016  &#8211; <b>Best Paper Award<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_164\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_164_block\"><pre><code class=\"tex bibtex\">@conference{W13,\nauthor = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {memres,hsi,ecc,memory,reliability,architecture,coding,systems,dram,caches},\nnote = {Best Paper Award},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_slides.pptx},\ntitle = {{Software-Defined Error-Correcting Codes}},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j39.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">M. Gottscho<\/span>, A. BanaiyanMofrad, N. Dutt, A. Nicolau, and P. Gupta, &#8220;DPCS: Dynamic Power\/Capacity Scaling for SRAM Caches in the Nanoscale Era,&#8221; <span style=\"font-style: italic\">ACM Transactions on Architecture and Code Optimization (TACO)<\/span>, vol. 12, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_157\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_157_block\"><pre><code class=\"tex bibtex\">@article{J39,\nauthor = {Gottscho, Mark and BanaiyanMofrad, Abbas and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},\nissue = {3},\njournal = {{ACM Transactions on Architecture and Code Optimization (TACO)}},\nmonth = {August},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J39_paper.pdf},\ntitle = {{DPCS}: {D}ynamic {P}ower\/{C}apacity {S}caling for {SRAM} {C}aches in the {N}anoscale {E}ra},\nvolume = {12},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j38.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Wanner, L. Lai, A. Rahimi, <span class=\"papercite_highlight\">M. Gottscho<\/span>, P. Mercati, C. Huang, F. Sala, Y. Agarwal, L. Dolecek, N. Dutt, P. Gupta, R. Gupta, R. Jhala, R. Kumar, S. Lerner, M. Subhasish, A. Nicolau, T. S. Rosing, M. B. Srivastava, S. Swanson, D. Sylvester, and Y. Zhou, &#8220;NSF Expedition on Variability-Aware Software: Recent Results and Contributions,&#8221; <span style=\"font-style: italic\">De Gruyter Information Technology (it)<\/span>, vol. 57, pp. 181-198, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_156\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_156_block\"><pre><code class=\"tex bibtex\">@article{J38,\nauthor = {Wanner, Lucas and Lai, Liangzhen and Rahimi, Abbas and Gottscho, Mark and Mercati, Pietro and Huang, Chu-Hsiang and Sala, Frederic and Agarwal, Yuvraj and Dolecek, Lara and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh and Jhala, Ranjit and Kumar, Rakesh and Lerner, Sorin and Mitra Subhasish and Nicolau, Alexandru and Rosing, Tajana Simunic and Srivastava, Mani B. and Swanson, Steve and Sylvester, Dennis and Zhou, Yuanyuan},\nissue = {3},\njournal = {{De Gruyter Information Technology (it)}},\nmonth = {June},\npages = {181-198},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J38_paper.pdf},\ntitle = {{NSF} {E}xpedition on {V}ariability-{A}ware {S}oftware: {R}ecent {R}esults and {C}ontributions},\nvolume = {57},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j33.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">M. Gottscho<\/span>, L. A. D. Bathen, N. Dutt, A. Nicolau, and P. Gupta, &#8220;ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computers<\/span>, vol. 64, p. 1483\u20131496, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_155\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_155_block\"><pre><code class=\"tex bibtex\">@article{J33,\nauthor = {Gottscho, Mark and Bathen, Luis A. D. and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},\nissue = {5},\njournal = {{IEEE Transactions on Computers}},\nkeywords = {DRAM, variability, energy-aware systems, main memory, allocation\/deallocation strategies, operating systems},\nmonth = {May},\npages = {1483--1496},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J33_paper.pdf},\ntitle = {{V}i{P}{Z}on{E}: {H}ardware {P}ower {V}ariability-{A}ware {V}irtual {M}emory {M}anagement for {E}nergy {S}avings},\nvolume = {64},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c82.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c82_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            S. Elmalaki, <span class=\"papercite_highlight\">M. Gottscho<\/span>, P. Gupta, and M. Srivastava, &#8220;A Case for Battery Charging-Aware Power Management and Deferrable Task Scheduling in Smartphones,&#8221; in <span style=\"font-style: italic\">USENIX Workshop on Power-Aware Computing and Systems (HotPower)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_147\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_147_block\"><pre><code class=\"tex bibtex\">@inproceedings{C82,\nauthor = {Elmalaki, Salma and Gottscho, Mark and Gupta, Puneet and Srivastava, Mani},\nbooktitle = {{USENIX Workshop on Power-Aware Computing and Systems (HotPower)}},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C82_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C82_slides.pdf},\ntitle = {{A} {C}ase for {B}attery {C}harging-{A}ware {P}ower {M}anagement and {D}eferrable {T}ask {S}cheduling in {S}martphones},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c79.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c79_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">M. Gottscho<\/span>, A. Banaiyan  Mofrad, N. Dutt, A. Nicolau, and P. Gupta, &#8220;Power \/ Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_146\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_146_block\"><pre><code class=\"tex bibtex\">@inproceedings{C79,\nauthor = {Gottscho, Mark and Banaiyan, Mofrad, Abbas and Dutt, Nikil and Nicolau, Alex and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {memres},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C79_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C79_slides.pdf},\ntitle = {{P}ower \/ {C}apacity {S}caling: {E}nergy {S}avings {W}ith {S}imple {F}ault-{T}olerant {C}aches},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    N. Dutt, P. Gupta, A. Nicolau, A. BanaiyanMofrad, <span class=\"papercite_highlight\">M. Gottscho<\/span>, and M. Shoushtari, &#8220;Multi-Layer Memory Resiliency,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_153\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_153_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP14,\nauthor = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and BanaiyanMofrad, Abbas and Gottscho, Mark and Shoushtari, Majid},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP14_paper.pdf},\ntitle = {{M}ulti-{L}ayer {M}emory {R}esiliency},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/mstr10_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">M. Gottscho<\/span>, &#8220;ViPZonE: Exploiting DRAM Power Variability for Energy Savings in Linux x86-64,&#8221; Department of Electrical Engineering, University of California Los Angeles 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_161\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_161_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR10,\nauthor = {Gottscho, Mark},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR10_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR10_slides.pdf},\ntitle = {{V}i{P}{Z}on{E}: {E}xploiting {DRAM} {P}ower {V}ariability for {E}nergy {S}avings in {L}inux x86-64},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    N. Dutt, P. Gupta, A. Nicolau, L. Bathen, and <span class=\"papercite_highlight\">M. Gottscho<\/span>, &#8220;Variability-Aware Memory Management for Nanoscale Computing,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_152\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_152_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP10,\nauthor = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and Bathen, Luis and Gottscho, Mark},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {hsi, variability, memory, dram, uno},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP10_paper.pdf},\ntitle = {{V}ariability-{A}ware {M}emory {M}anagement for {N}anoscale {C}omputing},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [20]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c65.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Bathen, <span class=\"papercite_highlight\">M. Gottscho<\/span>, N. Dutt, P. Gupta, and A. Nicolau, &#8220;ViPZonE: OS-Level Memory Variability-Aware Physical Address Zoning for Energy Savings,&#8221; in <span style=\"font-style: italic\">ACM International Conference on Hardware\/Software Codesign and System Synthesis<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_145\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_145_block\"><pre><code class=\"tex bibtex\">@inproceedings{C65,\nauthor = {Bathen, Luis and Gottscho, Mark and Dutt, Nikil and Gupta, Puneet and Nicolau, Alex},\nbooktitle = {{ACM International Conference on Hardware\/Software Codesign and System Synthesis}},\ncategory = {C65},\nkeywords = {hsi, vipzone, os, variability, variability-aware, dram, memory, power, zone, zoning, allocation},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C65_paper.pdf},\ntitle = {{V}i{P}{Z}on{E}: {O}{S}-{L}evel {M}emory {V}ariability-{A}ware {P}hysical {A}ddress {Z}oning for {E}nergy {S}avings},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [21]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j20.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">M. Gottscho<\/span>, A. A. Kagalwalla, and P. Gupta, &#8220;Power Variability in Contemporary DRAMs,&#8221; <span style=\"font-style: italic\">IEEE Embedded Systems Letters<\/span>, vol. 4, p. 37\u201340, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_154\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_154_block\"><pre><code class=\"tex bibtex\">@article{J20,\nauthor = {Gottscho, Mark and Kagalwalla, Abde Ali and Gupta, Puneet},\nissue = {2},\njournal = {{IEEE Embedded Systems Letters}},\nkeywords = {DRAM, DDR3, power, variability, hsi},\npages = {37--40},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J20_paper.pdf},\ntitle = {{P}ower {V}ariability in {C}ontemporary {DRAM}s},\nvolume = {4},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [22]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ug5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">M. Gottscho<\/span>, &#8220;Analyzing power variability of ddr3 dual inline memory modules,&#8221; University of California, Los Angeles 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_163\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_163_block\"><pre><code class=\"tex bibtex\">@techreport{UG5,\nauthor = {Gottscho, Mark},\ninstitution = {University of California, Los Angeles},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/UG2_paper.pdf},\ntitle = {Analyzing Power Variability of DDR3 Dual Inline Memory Modules},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:19% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"278\" height=\"340\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/shaodi_crop.jpg\" alt=\"\" class=\"wp-image-195 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Shaodi Wang<\/p>\n\n\n\n<p><strong>Contact:<\/strong>  &#x20;&#x20;&#x73;&#x68;&#97;&#111;&#100;iw&#x61;&#x6e;&#x67;&#x20;&#x41;&#84;&#32;&#103; D&#x4f;&#x54;&#x20;&#x75;&#x63;&#108;&#97;&#32;DO&#x54;&#x20;&#x65;&#x64;&#x75;&#32;&#32;&#32; <\/p>\n\n\n\n<p><strong>Research interests:<\/strong> Design for manufacturing modeling, novel device modeling and circuit analysis. <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong>  <\/p>\n\n\n\n<p><strong>PhD Thesis: <\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Wang, &#8220;Design, evaluation and co-optimization of emerging devices and circuits,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_165\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_165_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH6,\nauthor = {Wang, Shaodi},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {emerging technology, emerging device, emerging memory, MRAM, TFET, negative differential resistance, optimization, evaluation, stochastic computing, non-volatile memory, memory reliability},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH6_paper.pdf},\ntitle = {Design, Evaluation and Co-optimization of Emerging Devices and Circuits},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n<\/div><\/div>\n\n\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e372b5\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e372b5\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]                            P. Gupta, A. Pan, and <span class=\"papercite_highlight\">S. Wang<\/span>, <span style=\"font-style: italic\">Memory write and read assistance using negative differential resistance devices<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_182\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_182_block\"><pre><code class=\"tex bibtex\">@misc{P18,\nauthor = {P. Gupta and A. Pan and S. Wang},\nhowpublished = {U.S. Patent No. 10,832,752},\ntitle = {Memory write and read assistance using negative differential resistance devices},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [2]                            H. Lee, A. Lee, <span class=\"papercite_highlight\">S. Wang<\/span>, F. Ebrahimi, P. Gupta, P. K. Amiri, and K. L. Wang, &#8220;Analysis and Compact Modeling of Magnetic Tunner Junctions Using Voltage-Controlled Magnetic Anisotropy,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Magnetics<\/span>, 2018.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_180\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_180_block\"><pre><code class=\"tex bibtex\">@article{J58,\nauthor = {H. Lee and A. Lee and S. Wang and F. Ebrahimi and P. Gupta and P.K. Amiri and K.L. Wang},\njournal = {{IEEE Transactions on Magnetics}},\ntitle = {{Analysis and Compact Modeling of Magnetic Tunner Junctions Using Voltage-Controlled Magnetic Anisotropy}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j59.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Wang<\/span>, H. Lee, C. Grezes, K. P. Amiri, K. L. Wang, and P. Gupta, &#8220;Adaptive MRAM Write and Read with MTJ Variation Monitor,&#8221; <span style=\"font-style: italic\">Transactions on Emerging Topics in Computing<\/span>, 2018.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_181\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_181_block\"><pre><code class=\"tex bibtex\">@article{J59,\nauthor = {Wang, Shaodi and Lee, Hochul and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Gupta, Puneet},\njournal = {{Transactions on Emerging Topics in Computing}},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J59_paper.pdf},\ntitle = {{Adaptive MRAM Write and Read with MTJ Variation Monitor}},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c95.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c95_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">S. Wang<\/span>, S. Pal, T. Li, A. Pan, C. Grezes, K. P. Amiri, K. L. Wang, C. O. Chui, and P. Gupta, &#8220;Hybrid VC-MTJ\/CMOS Non-volatile Stochastic Logic for Efficient Computing,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2017  &#8211; <b>Best paper nomination<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_168\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_168_block\"><pre><code class=\"tex bibtex\">@inproceedings{C95,\nauthor = {Wang, Shaodi and Pal, Saptadeep and Li, Tianmu and Pan, Andrew and Grezes, Cecile and Amiri, P. Khalili and Wang, Kang L. and Chui, Chi On and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nkeywords = {mledge,Negative differential resistance, Magnetic tunnel junction, stochastic computing, stochastic bitstream generator, non-volatile computing},\nmonth = {March},\nnote = {Best paper nomination},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C95_slides.pdf},\ntitle = {{H}ybrid {VC-MTJ\/CMOS} {N}on-volatile {S}tochastic {L}ogic for {E}fficient {C}omputing},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j51.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    H. Lee, A. Lee, <span class=\"papercite_highlight\">S. Wang<\/span>, F. Ebrahimi, P. Gupta, K. P. Amiri, and K. L. Wang, &#8220;A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_178\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_178_block\"><pre><code class=\"tex bibtex\">@article{J51,\nauthor = {Lee, Hochul and Lee, Albert and Wang, Shaodi and Ebrahimi, Farbod and Gupta, Puneet and Amiri, P. Khalili and Wang, Kang L.},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {},\nmonth = {March},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J51_paper.pdf},\ntitle = {{A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j49.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Wang<\/span>, A. Pan, C. O. Chui, and P. Gupta, &#8220;Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electronic Devices<\/span>, vol. 64, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_176\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_176_block\"><pre><code class=\"tex bibtex\">@article{J49,\nauthor = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},\nissue = {1},\njournal = {{IEEE Transactions on Electronic Devices}},\nkeywords = {Negative differential resistance, Magnetic tunnel junction, Magnetic random access memory, MRAM, read, write termination},\nmonth = {1},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J49_paper.pdf},\ntitle = {{Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operation}},\nvolume = {64},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j50.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    C. Grezes, H. Lee, A. Lee, <span class=\"papercite_highlight\">S. Wang<\/span>, F. Ebrahimi, X. Li, K. Wong, Q. Hu, P. Gupta, K. P. Amiri, and K. L. Wang, &#8220;Write Error Rate and Read Disturbance in Electric-Field-Controlled MRAM,&#8221; <span style=\"font-style: italic\">IEEE Magnetic Letters<\/span>, vol. 8, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_177\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_177_block\"><pre><code class=\"tex bibtex\">@article{J50,\nauthor = {Grezes, Cecile and Lee, Hochul and Lee, Albert and Wang, Shaodi and Ebrahimi, Farbod and Li, Xiang and Wong, Kin and Hu, Qi and Gupta, Puneet and Amiri, P. Khalili and Wang, Kang L.},\njournal = {{IEEE Magnetic Letters}},\nkeywords = {},\nmonth = {},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J50_paper.pdf},\ntitle = {{Write Error Rate and Read Disturbance in Electric-Field-Controlled MRAM}},\nvolume = {8},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j55.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Wang<\/span>, A. Pan, C. Grezes, P. Amiri, C. O. Chui, and P. Gupta, &#8220;Leveraging NMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electronic Devices<\/span>, vol. PP, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_179\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_179_block\"><pre><code class=\"tex bibtex\">@article{J55,\nauthor = {Wang, Shaodi and Pan, Andrew and Grezes, Cecile and Amiri, Pedram and Chui, Chi On and Gupta, Puneet},\njournal = {{IEEE Transactions on Electronic Devices}},\nkeywords = {Negative differential resistance, Magnetic tunnel junction, Magnetic random access memory, MRAM, read, write termination},\nmonth = {8},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J55_paper.pdf},\ntitle = {{Leveraging NMOS Negative Differential Resistance\nfor Low Power, High Reliability Magnetic Memory}},\nvolume = {PP},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Wang<\/span>, &#8220;Design, evaluation and co-optimization of emerging devices and circuits,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_183\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_183_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH6,\nauthor = {Wang, Shaodi},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {emerging technology, emerging device, emerging memory, MRAM, TFET, negative differential resistance, optimization, evaluation, stochastic computing, non-volatile memory, memory reliability},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH6_paper.pdf},\ntitle = {Design, Evaluation and Co-optimization of Emerging Devices and Circuits},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j47.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Wang<\/span>, H. Hu, H. Zheng, and P. Gupta, &#8220;MEMRES: A Fast Memory System Reliability Simulator,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Reliability<\/span>, vol. 65, pp. 1783-1797, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_175\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_175_block\"><pre><code class=\"tex bibtex\">@article{J47,\nauthor = { Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},\nissue = {4},\njournal = {{IEEE Transactions on Reliability}},\nkeywords = {Memory fault, memory reliability, simulator, reliability management, memory page retirement, sparing, memory mirroring, STT-RAM, MRAM, write error, retention error},\nmonth = {October},\npages = {1783-1797},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J47_paper.pdf},\ntitle = {{MEMRES}: {A} {F}ast {M}emory {S}ystem {R}eliability {S}imulator},\nvolume = {65},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c92.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c92_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">S. Wang<\/span>, H. Lee, C. Grezes, P. Khalili, K. L. Wang, and P. Gupta, &#8220;MTJ Variation Monitor-assisted Adaptive MRAM Write,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_167\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_167_block\"><pre><code class=\"tex bibtex\">@inproceedings{C92,\nauthor = {Wang, Shaodi and Lee, Hochul and Grezes, Cecile and Khalili, Pedram and Wang, Kang L. and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {MRAM},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C92_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C92_slides.pdf},\ntitle = { {MTJ} {V}ariation {M}onitor-assisted {A}daptive {MRAM} {W}rite},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j42.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Wang<\/span>, H. Lee, F. Ebrahimi, K. P. Amiri, K. L. Wang, and P. Gupta, &#8220;Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory,&#8221; <span style=\"font-style: italic\">IEEE Journal on Emerging and Selected Topics in Circuits and Systems<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_172\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_172_block\"><pre><code class=\"tex bibtex\">@article{J42,\nauthor = {Wang, Shaodi and Lee, Hochul and Ebrahimi, Farbod and Amiri, P. Khalili and Wang, Kang L. and Gupta, Puneet},\njournal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},\nkeywords = {STT-RAM, MeRAM, MTJ, process variation, write error rate, MTJ Model},\nmonth = {June},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J42_paper.pdf},\ntitle = {{C}omparative {E}valuation of {S}pin-{T}ransfer-{T}orque and {M}agnetoelectric {R}andom {A}ccess {M}emory},\nvolume = {},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j45.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Zhu, Y. Badr, <span class=\"papercite_highlight\">S. Wang<\/span>, S. Iyer, and P. Gupta, &#8220;Assessing Benefits of a Buried Interconnect Layer in Digital Designs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_174\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_174_block\"><pre><code class=\"tex bibtex\">@article{J45,\nauthor = {Zhu, Liheng and Badr, Yasmine and Wang, Shaodi and Iyer, Subramanian and Gupta, Puneet},\ncategory = {J45},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J45_paper.pdf},\ntitle = {Assessing {B}enefits of a {B}uried {I}nterconnect {L}ayer in {D}igital {D}esigns},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j40.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    G. Leung, <span class=\"papercite_highlight\">S. Wang<\/span>, A. Pan, P. Gupta, and C. O. Chui, &#8220;An Evaluation Framework for Nanotransfer Printing Based Feature-Level Heterogeneous Integration in VLSI Circuits,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_171\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_171_block\"><pre><code class=\"tex bibtex\">@article{J40,\nauthor = {Leung, Greg and Wang, Shaodi and Pan, Andrew and Gupta, Puneet and Chui, Chi On},\nissue = {},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J40_paper.pdf},\ntitle = {{A}n {E}valuation {F}ramework for {N}anotransfer {P}rinting {B}ased {F}eature-{L}evel {H}eterogeneous {I}ntegration in {VLSI} {C}ircuits},\nvolume = {},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j43.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    H. Lee, C. Grezes, <span class=\"papercite_highlight\">S. Wang<\/span>, K. P. Amiri, P. Gupta, and K. L. Wang, &#8220;A Source Line Sensing (SLS) Scheme in Magnetoelectric Random Access Memory (MeRAM) for Reducing Read Disturbance and Improving Sensing Margin,&#8221; <span style=\"font-style: italic\">IEEE Magnetics Letters<\/span>, vol. 7, 2016.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_173\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_173_block\"><pre><code class=\"tex bibtex\">@article{J43,\nauthor = { Lee, Hochul and Grezes, Cecile and Wang, Shaodi and Amiri, P. Khalili and Gupta, Puneet and Wang, Kang L.},\njournal = {{IEEE Magnetics Letters}},\nkeywords = {MeRAM, MTJ, read disturbance, source line sensing, sensing scheme},\nmonth = {},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J43_paper.pdf},\ntitle = {A {S}ource {L}ine {S}ensing ({SLS}) {S}cheme in {M}agnetoelectric {R}andom {A}ccess {M}emory ({MeRAM}) for {R}educing {R}ead {D}isturbance and {I}mproving {S}ensing {M}argin},\nvolume = {7},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j37.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Wang<\/span>, A. Pan, C. O. Chui, and P. Gupta, &#8220;Proceed: a pareto optimization-based circuit-level evaluator for emerging devices,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_170\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_170_block\"><pre><code class=\"tex bibtex\">@article{J37,\nauthor = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {Emerging device, evaluator, proceed },\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J37_paper.pdf},\ntitle = {PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/w12_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               <span class=\"papercite_highlight\">S. Wang<\/span>, H. Hu, H. Zheng, and P. Gupta, &#8220;MEMRES: A Fast Memory System Reliability Simulator,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_184\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_184_block\"><pre><code class=\"tex bibtex\">@conference{W12,\nauthor = {Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {hsi, MEMRES, memory faults},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W12_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W12_slides.pptx},\ntitle = {{MEMRES: A Fast Memory System Reliability Simulator}},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c75.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c75_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               <span class=\"papercite_highlight\">S. Wang<\/span>, A. Pan, C. O. Chui, and P. Gupta, &#8220;PROCEED: a Pareto Optimization-based Circuit-level Evaluator for Emerging Devices,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_166\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_166_block\"><pre><code class=\"tex bibtex\">@inproceedings{C75,\nauthor = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {dats,proceed},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C75_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C75_slides.pptx},\ntitle = {{PROCEED:} A {P}areto {O}ptimization-based {C}ircuit-level {E}valuator for {E}merging {D}evices},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j29.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Wang<\/span>, G. Leung, A. Pan, C. O. Chui, and P. Gupta, &#8220;Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless Finfet Technologies,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electronic Devices<\/span>, vol. 60, iss. 7, pp. 2186-2193, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_169\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_169_block\"><pre><code class=\"tex bibtex\">@article{J29,\nauthor = {Wang, Shaodi and Leung, Greg and Pan, Andrew and Chui, Chi On and Gupta, Puneet},\njournal = {{IEEE Transactions on Electronic Devices}},\nkeywords = {variability},\nmonth = {July },\nnumber = {7},\npages = {2186 - 2193},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J29_paper.pdf},\ntitle = {{E}valuation of {D}igital {C}ircuit-{L}evel {V}ariability in {I}nversion-{M}ode and {J}unctionless {F}inFET {T}echnologies},\nvolume = {60},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"171\" height=\"225\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/liangzhen_bio.png\" alt=\"\" class=\"wp-image-196 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Liangzhen Lai<\/p>\n\n\n\n<p><strong>Contact:<\/strong>    liangzhen &#65;&#84;&#32;&#117;&#99;&#108;&#97;&#32;&#68;&#79;&#84;&#32;&#101;&#100;&#117;&#x20;&#x20;&#x20; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Facebook\n\n<\/p>\n\n\n\n<p><strong>PhD Thesis: <\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Lai, &#8220;Cross-layer approaches for monitoring, margining and mitigation of circuit variability,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2015. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_185\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_185_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH5,\nauthor = {Lai, Liangzhen},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH5_paper.pdf},\ntitle = {Cross-Layer Approaches for Monitoring, Margining and Mitigation of Circuit Variability},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n<\/div><\/div>\n\n\n<\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e372ed\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e372ed\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j53.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Lai<\/span> and P. Gupta, &#8220;System-level Dynamic Variation Margining in Presence of Monitoring and Actuation,&#8221; <span style=\"font-style: italic\">IEEE Embedded System Letters<\/span>, 2017.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_198\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_198_block\"><pre><code class=\"tex bibtex\">@article{J53,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\njournal = {{IEEE Embedded System Letters}},\nkeywords = {Monitoring, Temperature measurement, Temperature sensors, Actuators, Power system dynamics, Aging, Clocks},\nmonth = {June},\nnumber = {},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J53_paper.pdf},\ntitle = {{System-level Dynamic Variation Margining in Presence of Monitoring and Actuation}},\nvolume = {},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c89.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c89_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               Q. Zhang, <span class=\"papercite_highlight\">L. Lai<\/span>, M. Gottscho, and P. Gupta, &#8220;Multi-Story Power Distribution Networks for GPUs,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_190\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_190_block\"><pre><code class=\"tex bibtex\">@inproceedings{C89,\nauthor = {Zhang, Qixiang and Lai, Liangzhen and Gottscho, Mark and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C89_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C89_slides.pptx},\ntitle = {{M}ulti-{S}tory {P}ower {D}istribution {N}etworks for {GPU}s},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c90.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c90_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               <span class=\"papercite_highlight\">L. Lai<\/span> and P. Gupta, &#8220;Hardware Reliability Margining for the Dark Silicon Era,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_191\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_191_block\"><pre><code class=\"tex bibtex\">@inproceedings{C90,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {hsi},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C90_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C90_slides.pptx},\ntitle = {{H}ardware {R}eliability {M}argining for the {D}ark {S}ilicon {E}ra},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c88.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c88_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">L. Lai<\/span>, V. Chandra, and P. Gupta, &#8220;Evaluating and Exploiting Impacts of Dynamic Power Management Schemes on System Reliability,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_189\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_189_block\"><pre><code class=\"tex bibtex\">@inproceedings{C88,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)}},\nkeywords = {hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C88_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C88_slides.pdf},\ntitle = {{E}valuating and {E}xploiting {I}mpacts of {D}ynamic {P}ower {M}anagement {S}chemes on {S}ystem {R}eliability},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j38.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Wanner, <span class=\"papercite_highlight\">L. Lai<\/span>, A. Rahimi, M. Gottscho, P. Mercati, C. Huang, F. Sala, Y. Agarwal, L. Dolecek, N. Dutt, P. Gupta, R. Gupta, R. Jhala, R. Kumar, S. Lerner, M. Subhasish, A. Nicolau, T. S. Rosing, M. B. Srivastava, S. Swanson, D. Sylvester, and Y. Zhou, &#8220;NSF Expedition on Variability-Aware Software: Recent Results and Contributions,&#8221; <span style=\"font-style: italic\">De Gruyter Information Technology (it)<\/span>, vol. 57, pp. 181-198, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_197\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_197_block\"><pre><code class=\"tex bibtex\">@article{J38,\nauthor = {Wanner, Lucas and Lai, Liangzhen and Rahimi, Abbas and Gottscho, Mark and Mercati, Pietro and Huang, Chu-Hsiang and Sala, Frederic and Agarwal, Yuvraj and Dolecek, Lara and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh and Jhala, Ranjit and Kumar, Rakesh and Lerner, Sorin and Mitra Subhasish and Nicolau, Alexandru and Rosing, Tajana Simunic and Srivastava, Mani B. and Swanson, Steve and Sylvester, Dennis and Zhou, Yuanyuan},\nissue = {3},\njournal = {{De Gruyter Information Technology (it)}},\nmonth = {June},\npages = {181-198},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J38_paper.pdf},\ntitle = {{NSF} {E}xpedition on {V}ariability-{A}ware {S}oftware: {R}ecent {R}esults and {C}ontributions},\nvolume = {57},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Lai<\/span>, &#8220;Cross-layer approaches for monitoring, margining and mitigation of circuit variability,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2015.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_199\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_199_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH5,\nauthor = {Lai, Liangzhen},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH5_paper.pdf},\ntitle = {Cross-Layer Approaches for Monitoring, Margining and Mitigation of Circuit Variability},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j34.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Lai<\/span>, V. Chandra, R. Aitken, and P. Gupta, &#8220;SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, vol. 33, iss. 8, pp. 1168-1179, 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_196\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_196_block\"><pre><code class=\"tex bibtex\">@article{J34,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {hsi},\nmonth = {Aug},\nnumber = {8},\npages = {1168-1179},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J34_paper.pdf},\ntitle = {{S}lack{P}robe: {A} {F}lexible and {E}fficient {I}n {S}itu {T}iming {S}lack {M}onitoring {M}ethodology},\nvolume = {33},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j32.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Lai<\/span>, V. Chandra, R. Aitken, and P. Gupta, &#8220;BTI-Gater: An Aging-Resilient Clock Gating Methodology,&#8221; <span style=\"font-style: italic\">IEEE Journal on Emerging and Selected Topics in Circuits and Systems<\/span>, vol. 4, iss. 2, pp. 180-189, 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_195\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_195_block\"><pre><code class=\"tex bibtex\">@article{J32,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},\njournal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},\nkeywords = {hsi, NBTI},\nmonth = {June},\nnumber = {2},\npages = {180-189},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J32_paper.pdf},\ntitle = {{B}{T}{I}-{G}ater: {A}n {A}ging-{R}esilient {C}lock {G}ating {M}ethodology},\nvolume = {4},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Lai<\/span> and P. Gupta, &#8220;Accurate and inexpensive performance monitoring for variability-aware systems,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014, pp. 467-473  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_192\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_192_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP13,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {hsi},\nmonth = {Jan},\npages = {467-473},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP13_paper.pdf},\ntitle = {Accurate and inexpensive performance monitoring for variability-aware systems},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [10]                            Y. Agarwal, A. Bishop, T. Chan, M. Fotjik, P. Gupta, A. Kahng, <span class=\"papercite_highlight\">L. Lai<\/span>, P. Martin, M. Srivastava, D. Sylvester, L. Wanner, and B. Zhang, &#8220;Redcooper: hardware sensor enabled variability software testbed for lifetime energy constrained application,&#8221;  2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_200\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_200_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP1,\nauthor = {Agarwal, Yuvraj and Bishop, Alex and Chan, Tuck-Boon and Fotjik, Matt and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen and Martin, Paul and Srivastava, Mani and Sylvester, Dennis and Wanner, Lucas and Zhang, Bing},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/1c21g217},\ntitle = {Redcooper: Hardware sensor enabled variability software testbed for lifetime energy constrained application},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [11]                            <span class=\"papercite_highlight\">L. Lai<\/span>, C. Chang, and P. Gupta, &#8220;Exploring total power saving from high temperature of server operations,&#8221;  2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_201\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_201_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP2,\nauthor = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/5898p020},\ntitle = {Exploring Total Power Saving from High Temperature of Server Operations},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [12]                            <span class=\"papercite_highlight\">L. Lai<\/span> and P. Gupta, &#8220;A case study of logic delay fault behaviors on general-purpose embedded processor under voltage overscaling,&#8221;  2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_202\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_202_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP3,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/3967v8hw},\ntitle = {A Case Study of Logic Delay Fault Behaviors on General-Purpose Embedded Processor Under Voltage Overscaling},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [13]                            <span class=\"papercite_highlight\">L. Lai<\/span>, C. Chang, and P. Gupta, &#8220;Exploring total power saving from high temperature of server operations,&#8221; , 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_203\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_203_block\"><pre><code class=\"tex bibtex\">@article{TR1,\nauthor = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},\nkeywords = {hsi},\npaperurl = {http:\/\/escholarship.org\/uc\/item\/5898p020},\ntitle = {Exploring Total Power Saving from High Temperature of Server Operations},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c70.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Wanner, S. Elmalaki, <span class=\"papercite_highlight\">L. Lai<\/span>, P. Gupta, and M. Srivastava, &#8220;VarEMU: An Emulation Testbed for Variability-Aware Software,&#8221; in <span style=\"font-style: italic\">ACM International Conference on Hardware\/Software Codesign and System Synthesis<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_188\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_188_block\"><pre><code class=\"tex bibtex\">@inproceedings{C70,\nauthor = {Wanner, Lucas and Elmalaki, Salma and Lai, Liangzhen and Gupta, Puneet and Srivastava, Mani},\nbooktitle = {{ACM International Conference on Hardware\/Software Codesign and System Synthesis}},\ncategory = {C70},\nkeywords = {hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C70_paper.pdf},\ntitle = {{V}ar{E}{M}{U}: {A}n {E}mulation {T}estbed for {V}ariability-{A}ware {S}oftware},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c68.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c68_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">L. Lai<\/span>, V. Chandra, R. Aitken, and P. Gupta, &#8220;SlackProbe: a low overhead in situ on-line timing slack monitoring methodology,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_187\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_187_block\"><pre><code class=\"tex bibtex\">@inproceedings{C68,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\ncatetory = {C68},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C68_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C68_slides.pdf},\ntitle = {{S}lack{P}robe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j31.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Chan, P. Gupta, A. B. Kahng, and <span class=\"papercite_highlight\">L. Lai<\/span>, &#8220;Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_194\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_194_block\"><pre><code class=\"tex bibtex\">@article{J31,\nauthor = {Chan, Tuck-Boon and Gupta, Puneet and Kahng, A. B. and Lai, Liangzhen},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi, DDRO},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J31_paper.pdf},\ntitle = {{S}ynthesis and {A}nalysis of {D}esign-{D}ependent {R}ing {O}scillator ({D}{D}{R}{O}) {P}erformance {M}onitors},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j22.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    G. Leung, <span class=\"papercite_highlight\">L. Lai<\/span>, P. Gupta, and C. O. Chui, &#8220;Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32nm Finfet Technologies,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Electronic Devices<\/span>, vol. 59, iss. 8, pp. 2057-2063, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_193\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_193_block\"><pre><code class=\"tex bibtex\">@article{J22,\nauthor = {Leung, Greg and Lai, Liangzhen and Gupta, Puneet and Chui, Chi On},\njournal = {{IEEE Transactions on Electronic Devices}},\nkeywords = {variability},\nmonth = {aug. },\nnumber = {8},\npages = {2057 -2063},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J22_paper.pdf},\ntitle = {{D}evice- and {C}ircuit-{L}evel {V}ariability {C}aused\nby {L}ine {E}dge {R}oughness for {S}ub-32nm {F}inFET {T}echnologies},\nvolume = {59},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c60.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c60_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. B. Chan, P. Gupta, A. Kahng, and <span class=\"papercite_highlight\">L. Lai<\/span>, &#8220;DDRO: a Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,&#8221; in <span style=\"font-style: italic\">ISQED<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_186\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_186_block\"><pre><code class=\"tex bibtex\">@inproceedings{C60,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen},\nbooktitle = {{ISQED}},\ncategory = {C60},\nkeywords = {hsi, DDRO},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C60_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C60_slides.pdf},\ntitle = {{DDRO}: A {N}ovel {P}erformance {M}onitoring {M}ethodology {B}ased on {D}esign-{D}ependent {R}ing {O}scillators},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"738\" height=\"914\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/abdeali_bigsur_crop.jpg\" alt=\"\" class=\"wp-image-197 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Abde Ali Kagalwalla<\/p>\n\n\n\n<p><strong>Contact:<\/strong>  &#x20;&#32;a&#x62;&#100;e&#x61;&#108;i&#x20;&#65;T&#x20;&#117;c&#x6c;&#97; &#x44;&#79;T&#x20;&#101;d&#x75;&#32; &#x20; <\/p>\n\n\n\n<p><strong>Research interests:<\/strong> Computer-Aided Design of VLSI Systems, Design-for-Manufacturability,  Layout Optimization, Lithography  <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Intel  \n\n<\/p>\n\n\n\n<p><strong>Phd Thesis: <\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. A. Kagalwalla, &#8220;Computational methods for design-assisted mask flows,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_204\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_204_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH4,\nauthor = {Kagalwalla, Abde Ali},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH4_paper.pdf},\ntitle = {Computational Methods for Design-Assisted Mask Flows},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n<\/div><\/div>\n\n\n<\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37322\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37322\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j44.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. B. Chan, P. Gupta, K. Han, A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, and A. B. Kahng, &#8220;Benchmarking of Mask Fracturing Heuristics,&#8221; in <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_219\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_219_block\"><pre><code class=\"tex bibtex\">@inproceedings{J44,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. },\nbooktitle = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ncategory = {J44},\nkeywords = {dats},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J44_paper.pdf},\ntitle = {Benchmarking of {M}ask {F}racturing {H}euristics},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c87.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>       <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c87_slides.pptx\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PP Slides]\"\/><\/a>               A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span> and P. Gupta, &#8220;Effective Model-Based Mask Fracturing for Mask Cost Reduction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2015  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_212\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_212_block\"><pre><code class=\"tex bibtex\">@inproceedings{C87,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C87_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C87_slides.pptx},\ntitle = { {E}ffective {M}odel-{B}ased {M}ask {F}racturing for {M}ask {C}ost {R}eduction},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c80.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. B. Chan, P. Gupta, K. Han, A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, A. B. Kahng, and E. Sahouria, &#8220;Benchmarking of Mask Fracturing Heuristics,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_211\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_211_block\"><pre><code class=\"tex bibtex\">@inproceedings{C80,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. and Sahouria, Emile},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C80},\nkeywords = {dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C80_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C80_slides.pdf},\ntitle = {Benchmarking of {M}ask {F}racturing {H}euristics},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c77.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c77_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span> and P. Gupta, &#8220;Comprehensive Defect Avoidance Framework for Mitigating EUV Mask Defects,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_210\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_210_block\"><pre><code class=\"tex bibtex\">@inproceedings{C77,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C77_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C77_slides.pdf},\ntitle = {{C}omprehensive {D}efect {A}voidance {F}ramework for {M}itigating {EUV} {M}ask {D}efects},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c73.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c73_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, M. Lam, K. Adam, and P. Gupta, &#8220;EUV-CDA: Pattern Shift Aware Critical Density Analysis for EUV Mask Layouts,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_209\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_209_block\"><pre><code class=\"tex bibtex\">@inproceedings{C73,\nauthor = {Kagalwalla, Abde Ali and Lam, Michael and Adam, Kostas and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C73_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C73_slides.pdf},\ntitle = {{EUV-CDA}: {P}attern {S}hift {A}ware {C}ritical {D}ensity {A}nalysis for {EUV} {M}ask {L}ayouts},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j35.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/10.1117\/1.JMM.13.4.043005' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span> and P. Gupta, &#8220;Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, vol. 13, iss. 4, p. 43005, 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_218\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_218_block\"><pre><code class=\"tex bibtex\">@article{J35,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\ndoi = {10.1117\/1.JMM.13.4.043005},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\nnumber = {4},\npages = {043005},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J35_paper.pdf},\ntitle = {Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects},\nvolume = {13},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, &#8220;Computational methods for design-assisted mask flows,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_221\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_221_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH4,\nauthor = {Kagalwalla, Abde Ali},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH4_paper.pdf},\ntitle = {Computational Methods for Design-Assisted Mask Flows},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j28.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span> and P. Gupta, &#8220;Design-Aware Defect-Avoidance Floorplanning of EUV Masks,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, vol. 26, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_217\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_217_block\"><pre><code class=\"tex bibtex\">@article{J28,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\nissue = {1},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J28_paper.pdf},\ntitle = {{Design-Aware Defect-Avoidance Floorplanning of EUV Masks}},\nvolume = {26},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c62.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta, &#8220;Design-of-Experiments Based Design Rule Optimization,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_208\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_208_block\"><pre><code class=\"tex bibtex\">@inproceedings{C62,\nauthor = {Kagalwalla, Abde Ali and Muddu, Swamy and Capodieci, Luigi and Zelnik, Coby and Gupta, Puneet },\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C62},\nkeywords = {Design Rules, DOE, dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C62_paper.pdf},\ntitle = {{D}esign-of-{E}xperiments {B}ased {D}esign {R}ule {O}ptimization},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j18.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, P. Gupta, C. Progler, and S. McDonald, &#8220;Design-Aware Mask Inspection,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_215\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_215_block\"><pre><code class=\"tex bibtex\">@article{J18,\nauthor = {Kagalwalla, Abde Ali and Puneet Gupta and Progler, Chris and McDonald, Steve},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J18_paper.pdf},\ntitle = {Design-{A}ware {M}ask {I}nspection},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j20.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    M. Gottscho, A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, and P. Gupta, &#8220;Power Variability in Contemporary DRAMs,&#8221; <span style=\"font-style: italic\">IEEE Embedded Systems Letters<\/span>, vol. 4, p. 37\u201340, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_216\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_216_block\"><pre><code class=\"tex bibtex\">@article{J20,\nauthor = {Gottscho, Mark and Kagalwalla, Abde Ali and Gupta, Puneet},\nissue = {2},\njournal = {{IEEE Embedded Systems Letters}},\nkeywords = {DRAM, DDR3, power, variability, hsi},\npages = {37--40},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J20_paper.pdf},\ntitle = {{P}ower {V}ariability in {C}ontemporary {DRAM}s},\nvolume = {4},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c57.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, P. Gupta, D. Hur, and C. Park, &#8220;Defect-aware Reticle Floorplanning for EUV Masks,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_207\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_207_block\"><pre><code class=\"tex bibtex\">@inproceedings{C57,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet and Hur, Duck-Hyung and Park, Chul-Hong },\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C57},\nkeywords = {EUV, floorplanning, dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C57_paper.pdf},\ntitle = {{D}efect-aware {R}eticle {F}loorplanning for {EUV} {M}asks},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [13]                            A. R. Neureuther, J. Rubinstein, M. Miller, Y. K. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T. -J. K. Liu, X. Sun, K. Jeong, P. and Gupta, A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, R. S. Ghaida, and T. -B. Chan, &#8220;Collaborative research on emerging technologies and design,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Photomask and Next-Generation Lithography Mask Technology<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_213\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_213_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP7,\nauthor = {A.R. Neureuther and J. Rubinstein and M. Miller and K. Yamazoeand E. Chin and C. Levy and L. Wang and N. Xu and C. Spanos and K. Qian and K. Poolla and J. Ghan and A. Subramanian and T.-J. K. Liu and X. Sun and K. Jeong and and P. Gupta and Kagalwalla, Abde Ali and Ghaida, R. S. and T.-B. Chan},\nbooktitle = {{Proc. SPIE Photomask and Next-Generation Lithography Mask Technology}},\ncategory = {IP7},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/pmj11.pdf},\ntitle = {Collaborative research on emerging technologies and design},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. B. Chan, A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, and P. Gupta, &#8220;Measurement and Optimization of Electrical Process Window,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_214\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_214_block\"><pre><code class=\"tex bibtex\">@article{J15,\nauthor = {Chan, T.B. and Kagalwalla, Abde Ali and Gupta, P. },\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J15_paper.pdf},\ntitle = {{M}easurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, &#8220;Design-aware mask manufacturing,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_220\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_220_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH2,\nauthor = {Kagalwalla, Abde Ali},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH2_paper.pdf},\ntitle = {Design-Aware Mask Manufacturing},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c52.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c52_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, P. Gupta, C. Progler, and S. McDonald, &#8220;Design-aware Mask Inspection,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_206\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_206_block\"><pre><code class=\"tex bibtex\">@inproceedings{C52,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C52},\nkeywords = {mask manufacturing, inspection, dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C52_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C52_slides.pdf},\ntitle = {{D}esign-aware {M}ask {I}nspection},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c46.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c46_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, and P. Gupta, &#8220;Measurement and Optimization of Electrical Process Window,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_205\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_205_block\"><pre><code class=\"tex bibtex\">@inproceedings{C46,\nauthor = {Chan, T.-B. and Kagalwalla, Abde Ali and Gupta, P.},\nbooktitle = {{Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration}},\ncategory = {C46},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C46_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C46_slides.pdf},\ntitle = {Measurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [18]                            A. <span class=\"papercite_highlight\">A. Kagalwalla<\/span>, P. Gupta, C. Progler, and S. McDonald, &#8220;Design-aware Mask Inspection,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_222\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_222_block\"><pre><code class=\"tex bibtex\">@conference{W6,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W6},\nkeywords = {dats},\ntitle = {{D}esign-aware {M}ask {I}nspection},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"124\" height=\"152\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/rani.jpg\" alt=\"\" class=\"wp-image-198 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Rani S. Ghaida<\/p>\n\n\n\n<p><strong>Contact: <\/strong> &#x20;&#32;r&#x61;&#110;i&#x67;&#104;a&#x69;&#100;a&#x20;&#65;T&#x20;&#x75;c&#x6c;&#x61;&#32;&#x44;&#x4f;&#84;&#x20;&#x65;&#100;u&#x20;&#32; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Xilinx  <\/p>\n\n\n\n<p><strong>Phd Thesis: <\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, &#8220;Design enablement and design-centric assessment of future semiconductor technologies,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_223\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_223_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH3,\nauthor = {Ghaida, R. S.},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH3_paper.pdf},\ntitle = {Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n<\/div><\/div>\n\n\n<\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37359\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37359\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c74.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c74_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, Y. Badr, M. Gupta, N. Jin, and P. Gupta, &#8220;Comprehensive Die-level Assessment of Design Rules and Layouts,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_231\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_231_block\"><pre><code class=\"tex bibtex\">@inproceedings{C74,\nauthor = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {dats,dre},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_slides.pdf},\ntitle = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip16.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, Y. Badr, and P. Gupta, &#8220;Pattern-restricted design at 10nm and beyond,&#8221; in <span style=\"font-style: italic\">Proc. IEEE International Conference on Computer Design<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_233\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_233_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP16,\nauthor = { Ghaida, Rani S. and Badr, Yasmine and Gupta, Puneet},\nbooktitle = {{Proc. IEEE International Conference on Computer Design}},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP16_paper.pdf},\ntitle = {Pattern-restricted design at 10nm and beyond},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j30.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, M. Gupta, and P. Gupta, &#8220;Framework for exploring the interaction between design rules and overlay control,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, vol. 12, iss. 3, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_241\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_241_block\"><pre><code class=\"tex bibtex\">@article{J30,\nauthor = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {variability},\nmonth = {August },\nnumber = {3},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J30_paper.pdf},\ntitle = {Framework for exploring the interaction between design rules and overlay control},\nvolume = {12},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c69.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, M. Gupta, and P. Gupta, &#8220;A Framework for Exploring the Interaction between Design Rules and Overlay Control,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_230\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_230_block\"><pre><code class=\"tex bibtex\">@inproceedings{C69,\nauthor = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C69},\nkeywords = {overlay, design rules, dre, alignment},\nmonth = {Feburary},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C69_paper.pdf},\ntitle = {A {F}ramework for {E}xploring the {I}nteraction between {D}esign {R}ules and {O}verlay {C}ontrol},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [5]                            <span class=\"papercite_highlight\">R. S. Ghaida<\/span> and P. Gupta, &#8220;Role of design in multiple patterning: technology development, design enablement and process control,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_232\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_232_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP11,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/mp_and_design_date13.pdf},\ntitle = {Role of Design in Multiple Patterning: Technology\nDevelopment, Design Enablement and Process Control},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c64.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c64_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, T. Sahu, P. Kulkarni, and P. Gupta, &#8220;A methodology for the early exploration of design rules for multiple-patterning technologies,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_229\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_229_block\"><pre><code class=\"tex bibtex\">@inproceedings{C64,\nauthor = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C64},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_slides.pdf},\ntitle = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/ip9_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, &#8220;O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,&#8221; in <span style=\"font-style: italic\">Intl. Conf. on IC Design and Technology<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_236\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_236_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP9,\nauthor = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},\nbooktitle = {{Intl. Conf. on IC Design and Technology}},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/ip9_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/ip9_slides.pdf},\ntitle = {O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c63.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, K. Agarwal, L. Liebmann, S. R. Nassif, and P. Gupta, &#8220;A Novel Methodology for Triple\/Multiple-Patterning Layout Decomposition,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_228\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_228_block\"><pre><code class=\"tex bibtex\">@inproceedings{C63,\nauthor = {Ghaida, R. S. and Agarwal, K. and Liebmann, L. and Nassif, S. R. and Gupta, P.},\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C63},\nkeywords = {triple patterning, double patterning, dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C63_paper.pdf},\ntitle = {{A} {N}ovel {M}ethodology for {T}riple\/{M}ultiple-{P}atterning {L}ayout {D}ecomposition},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j19.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">R. S. Ghaida<\/span> and P. Gupta, &#8220;DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_239\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_239_block\"><pre><code class=\"tex bibtex\">@article{J19,\nauthor = {Ghaida, R. S. and Gupta, P.},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {design rules, technology assessment, dre, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J19_paper.pdf},\ntitle = {{DRE}: a {F}ramework for {E}arly {C}o-{E}valuation of {D}esign {R}ules, {T}echnology {C}hoices, and {L}ayout {M}ethodologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j27.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, &#8220;Layout Decomposition and Legalization for Double-Patterning Technology,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_240\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_240_block\"><pre><code class=\"tex bibtex\">@article{J27,\nauthor = {Ghaida, R. S. and Agarwal, K. B. and Nassif, S. R. and Yuan, X. and Liebmann, L. W. and Gupta, P.},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi, multiple-patterning},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J27_paper.pdf},\ntitle = {{L}ayout {D}ecomposition and {L}egalization for {D}ouble-{P}atterning {T}echnology},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, &#8220;Design enablement and design-centric assessment of future semiconductor technologies,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_242\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_242_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH3,\nauthor = {Ghaida, R. S.},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH3_paper.pdf},\ntitle = {Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [12]                            <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, M. Gupta, and P. Gupta, &#8220;A framework for exploring the interaction between design rules and overlay control,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_244\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_244_block\"><pre><code class=\"tex bibtex\">@conference{W11,\nauthor = {Ghaida, R. S. and Gupta, M. and Gupta, P.},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W11},\nkeywords = {dats, dre, design rules, overlay, alignment, process, multiple-patterning, lithography},\ntitle = {A Framework for Exploring the Interaction Between Design Rules and Overlay Control},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c59.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c59_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, &#8220;A Framework for Double Patterning-Enabled Design,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_227\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_227_block\"><pre><code class=\"tex bibtex\">@inproceedings{C59,\nauthor = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C59},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C59_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C59_slides.pdf},\ntitle = {A {F}ramework for {D}ouble {P}atterning-{E}nabled {D}esign},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [14]                            A. R. Neureuther, J. Rubinstein, M. Miller, Y. K. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T. -J. K. Liu, X. Sun, K. Jeong, P. and Gupta, A. A. Kagalwalla, <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, and T. -B. Chan, &#8220;Collaborative research on emerging technologies and design,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Photomask and Next-Generation Lithography Mask Technology<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_235\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_235_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP7,\nauthor = {A.R. Neureuther and J. Rubinstein and M. Miller and K. Yamazoeand E. Chin and C. Levy and L. Wang and N. Xu and C. Spanos and K. Qian and K. Poolla and J. Ghan and A. Subramanian and T.-J. K. Liu and X. Sun and K. Jeong and and P. Gupta and Kagalwalla, Abde Ali and Ghaida, R. S. and T.-B. Chan},\nbooktitle = {{Proc. SPIE Photomask and Next-Generation Lithography Mask Technology}},\ncategory = {IP7},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/pmj11.pdf},\ntitle = {Collaborative research on emerging technologies and design},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/ip6_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, and P. Gupta, &#8220;Electrical Modeling of Lithographic Imperfections,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2010  &#8211; <b>Embedded Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_234\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_234_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP6,\nauthor = {Chan, T.-B. and Ghaida, R. S. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {IP6},\nkeywords = {mad},\nnote = {Embedded Tutorial},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP6_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP6_slides.pdf},\ntitle = {{E}lectrical {M}odeling of {L}ithographic {I}mperfections},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">R. S. Ghaida<\/span> and P. Gupta, &#8220;Within-Layer Overlay Impact for Design in Metal Double Patterning,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_237\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_237_block\"><pre><code class=\"tex bibtex\">@article{J10,\nauthor = {Ghaida, R. S. and Gupta, P.},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {double patterning, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J10_paper.pdf},\ntitle = {Within-{L}ayer {O}verlay {I}mpact for {D}esign in {M}etal {D}ouble {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, G. Torres, and P. Gupta, &#8220;Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_238\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_238_block\"><pre><code class=\"tex bibtex\">@article{J13,\nauthor = {Ghaida, R. S. and Torres, G. and Gupta, P.},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {double patterning, stdpl, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J13_paper.pdf},\ntitle = {{S}ingle-{M}ask {D}ouble-{P}atterning {L}ithography for {R}educed {C}ost and {I}mproved {O}verlay {C}ontrol},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c44.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c44_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">R. S. Ghaida<\/span> and P. Gupta, &#8220;A Framework for Early and Systematic Evaluation of Design Rules,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_226\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_226_block\"><pre><code class=\"tex bibtex\">@inproceedings{C44,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C44},\nkeywords = {dats, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C44_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C44_slides.pdf},\ntitle = {A {F}ramework for {E}arly and {S}ystematic {E}valuation of {D}esign {R}ules},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c41.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c41_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">R. S. Ghaida<\/span>, G. Torres, and P. Gupta, &#8220;Single-Mask Double-Patterning Lithography,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_225\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_225_block\"><pre><code class=\"tex bibtex\">@inproceedings{C41,\nauthor = {Ghaida, R. S. and Torres, G. and Gupta, P.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\nkeywords = {dats},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C41_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C41_slides.pdf},\ntitle = {Single-{M}ask {D}ouble-{P}atterning {L}ithography},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [20]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c40.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c40_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">R. S. Ghaida<\/span> and P. Gupta, &#8220;Design-Overlay Interactions in Metal Double Patterning,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_224\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_224_block\"><pre><code class=\"tex bibtex\">@inproceedings{C40,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {double patterning, test pattern, dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C40_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C40_slides.pdf},\ntitle = {Design-{O}verlay {I}nteractions in {M}etal {D}ouble {P}atterning},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [21]                            <span class=\"papercite_highlight\">R. S. Ghaida<\/span> and P. Gupta, &#8220;A Framework for Systematic Evaluation and Exploration of Design Rules,&#8221; in <span style=\"font-style: italic\">SRC TECHCON&#8217;09<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_243\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_243_block\"><pre><code class=\"tex bibtex\">@conference{W1,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{SRC TECHCON'09}},\ncategory = {W1},\nkeywords = {dats},\nmonth = {},\npages = {},\ntitle = {A {F}ramework for {S}ystematic {E}valuation and {E}xploration of {D}esign {R}ules},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"119\" height=\"145\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/john_lee.jpg\" alt=\"\" class=\"wp-image-199 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. John Lee<\/p>\n\n\n\n<p><strong>Contact:<\/strong>  &#32;&#x6c;&#x65;e&#32;&#x61;t&#32;&#x65;&#x65; &#100;&#x6f;t&#32;&#x75;&#x63;l&#97;&#x20; &#32; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> KPMG     <\/p>\n\n\n\n<p><strong>Phd Thesis: <\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Lee, &#8220;Implications of modern semiconductor technologies on gate sizing,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_245\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_245_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH2,\nauthor = {Lee, John},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH2_paper.pdf},\ntitle = {Implications of Modern Semiconductor Technologies on Gate Sizing},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<\/div><\/div>\n\n\n<\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e3738d\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e3738d\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c67.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c67_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">J. Lee<\/span> and P. Gupta, &#8220;Impact of range and precision in technology on cell-based design,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_252\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_252_block\"><pre><code class=\"tex bibtex\">@inproceedings{C67,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C67},\nkeywords = {sizing},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C67_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C67_slides.pdf},\ntitle = {Impact of Range and Precision in Technology on Cell-Based Design},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c66.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c66_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">J. Lee<\/span>, P. Gupta, and F. Pikus, &#8220;Parametric hierarchy recovery in layout extracted netlists,&#8221; in <span style=\"font-style: italic\">Proc. IEEE Computer Society Annual Symposium on VLSI<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_251\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_251_block\"><pre><code class=\"tex bibtex\">@inproceedings{C66,\nauthor = {Lee, John and Gupta, Puneet and Pikus, Fedor},\nbooktitle = {{Proc. IEEE Computer Society Annual Symposium on VLSI}},\ncategory = {C66},\nkeywords = {variability-aware},\nmonth = {August},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C66_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C66_slides.pdf},\ntitle = {Parametric Hierarchy Recovery in Layout Extracted Netlists},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/b2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">J. Lee<\/span> and P. Gupta, <span style=\"font-style: italic\">Discrete circuit optimization: library based gate sizing and threshold voltage assignment<\/span>, Now Publishers, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_246\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_246_block\"><pre><code class=\"tex bibtex\">@book{B2,\nauthor = {Lee, J. and Gupta, P.},\nisbn = {978-1-60198-542-2},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/B2_paper.pdf},\npublisher = {Now Publishers},\ntitle = {Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j24.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">J. Lee<\/span> and P. Gupta, &#8220;ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_254\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_254_block\"><pre><code class=\"tex bibtex\">@article{J24,\nauthor = {John Lee and Puneet Gupta},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J24_paper.pdf},\ntitle = {{ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes}},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j25.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Mok, <span class=\"papercite_highlight\">J. Lee<\/span>, and P. Gupta, &#8220;Discrete sizing for leakage power optimization in physical design: a comparative study,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_255\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_255_block\"><pre><code class=\"tex bibtex\">@article{J25,\nauthor = {Santiago Mok and John Lee and Puneet Gupta},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J25_paper.pdf},\ntitle = {Discrete Sizing for Leakage Power Optimization in Physical Design: A Comparative Study},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">J. Lee<\/span>, &#8220;Implications of modern semiconductor technologies on gate sizing,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_256\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_256_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH2,\nauthor = {Lee, John},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH2_paper.pdf},\ntitle = {Implications of Modern Semiconductor Technologies on Gate Sizing},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/w10_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">J. Lee<\/span> and P. Gupta, &#8220;Parametric hierarchy recovery for layout extracted netlists,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_257\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_257_block\"><pre><code class=\"tex bibtex\">@conference{W10,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W10},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W10_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W10_slides.pdf},\ntitle = {Parametric Hierarchy Recovery for Layout Extracted Netlists},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Cong, P. Gupta, and <span class=\"papercite_highlight\">J. Lee<\/span>, &#8220;Evaluating Statistical Power Optimization,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, vol. 29, iss. 11, p. 1750\u20131762, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_253\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_253_block\"><pre><code class=\"tex bibtex\">@article{J12,\nauthor = {Cong, J. and Gupta, P. and Lee, John},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {sizing, mad},\nmonth = {Nov},\nnumber = {11},\npages = {1750--1762},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J12_paper.pdf},\ntitle = {{Evaluating Statistical Power Optimization}},\nvolume = {29},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c51.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c51_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">J. Lee<\/span> and P. Gupta, &#8220;Incremental Gate Sizing for Late Process Changes,&#8221; in <span style=\"font-style: italic\">Proc. IEEE International Conference on Computer Design<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_250\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_250_block\"><pre><code class=\"tex bibtex\">@inproceedings{C51,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{Proc. IEEE International Conference on Computer Design}},\ncategory = {C51},\nkeywords = {sizing, mad},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C51_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C51_slides.pdf},\ntitle = {{I}ncremental {G}ate {S}izing for {L}ate {P}rocess {C}hanges},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/w7_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">J. Lee<\/span> and P. Gupta, &#8220;Incremental gate sizing for late process changes,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_258\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_258_block\"><pre><code class=\"tex bibtex\">@conference{W7,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W7},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W7_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W7_slides.pdf},\ntitle = {Incremental Gate Sizing for Late Process Changes},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c38.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c38_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            J. Cong, P. Gupta, and <span class=\"papercite_highlight\">J. Lee<\/span>, &#8220;On the Futlity of Statistical Power Optimization,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_249\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_249_block\"><pre><code class=\"tex bibtex\">@inproceedings{C38,\nauthor = {Cong, J. and Gupta, P. and Lee, John},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C38},\nkeywords = {sizing, mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C38_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C38_slides.pdf},\ntitle = {On the {F}utlity of {S}tatistical {P}ower {O}ptimization},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c21.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, F. -L. Heng, and J. -F. Lee, &#8220;Toward Through-Process Layout Quality Metrics,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2005  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_248\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_248_block\"><pre><code class=\"tex bibtex\">@inproceedings{C21,\nauthor = {Gupta, P. and Heng, F.-L. and Lee, J.-F. },\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C21},\nkeywords = {mad},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C21_paper.pdf},\ntitle = {Toward {T}hrough-{P}rocess {L}ayout {Q}uality {M}etrics},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, F. -L. Heng, R. L. Gordon, K. Lai, and <span class=\"papercite_highlight\">J. Lee<\/span>, &#8220;Taming Focus Variation in VLSI Design,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2004  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_247\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_247_block\"><pre><code class=\"tex bibtex\">@inproceedings{C12,\nauthor = {Gupta, P. and Heng, F.-L. and Gordon, R.L. and Lai, K. and Lee, J. },\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C12},\nkeywords = {mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C12_paper.pdf},\ntitle = {Taming {F}ocus {V}ariation in {VLSI} {D}esign},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"168\" height=\"210\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/lerong_pic2.png\" alt=\"\" class=\"wp-image-200 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Dr. Lerong Cheng<\/p>\n\n\n\n<p><strong>Contact:<\/strong>  &#32;l&#x65;r&#x6f;n&#x67; &#x41;T&#x20;u&#x63;&#108;&#x61;&#32;&#x44;&#79;&#x54;&#32;&#x65;&#100;&#x75;&#32;&#x20;&#32; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Google\n\n<\/p>\n\n\n\n<p> <strong>Phd Thesis: <\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Cheng, &#8220;Statistical analysis and optimization for timing and power of vlsi circuits,&#8221; PhD Thesis, 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_259\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_259_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH1,\nauthor = {Cheng, Lerong},\ncategory = {PT1},\nkeywords = {stat},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH1_paper.pdf},\nschool = {Department of Electrical Engineering, University of California Los Angeles },\ntitle = {Statistical Analysis and Optimization for Timing and Power of VLSI Circuits},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>    <\/p>\n<\/div><\/div>\n\n\n<\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e373bb\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e373bb\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j21.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Chan, A. Pant, <span class=\"papercite_highlight\">L. Cheng<\/span>, and P. Gupta, &#8220;Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_265\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_265_block\"><pre><code class=\"tex bibtex\">@article{J21,\nauthor = {Chan, Tuck-Boon and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {Process monitoring, wafer pruning, variability},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J21_paper.pdf},\ntitle = {{D}esign {D}ependent {P}rocess {M}onitoring for {W}afer {M}anufacturing and {T}est {C}ost {R}eduction},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c53.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c53_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, A. Pant, <span class=\"papercite_highlight\">L. Cheng<\/span>, and P. Gupta, &#8220;Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_263\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_263_block\"><pre><code class=\"tex bibtex\">@inproceedings{C53,\nauthor = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C53},\nkeywords = {process variation, process monitoring, dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_slides.pdf},\ntitle = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c47.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Cheng<\/span>, P. Gupta, and L. He, &#8220;On Confidence in Characterization and Application of Variation Models,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_262\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_262_block\"><pre><code class=\"tex bibtex\">@inproceedings{C47,\nauthor = {Cheng, L. and Gupta, P. and He, L.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C47},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C47_paper.pdf},\ntitle = {On {C}onfidence in {C}haracterization and {A}pplication of {V}ariation {M}odels},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Cheng<\/span>, P. Gupta, C. J. Spanos, K. Qian, and L. He, &#8220;Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_264\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_264_block\"><pre><code class=\"tex bibtex\">@article{J14,\nauthor = {Cheng, L. and Gupta, P. and Spanos, C. J. and Qian, K. and He, L.},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J14_paper.pdf},\ntitle = {{P}hysically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Cheng<\/span>, &#8220;Statistical analysis and optimization for timing and power of vlsi circuits,&#8221; PhD Thesis, 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_267\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_267_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH1,\nauthor = {Cheng, Lerong},\ncategory = {PT1},\nkeywords = {stat},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH1_paper.pdf},\nschool = {Department of Electrical Engineering, University of California Los Angeles },\ntitle = {Statistical Analysis and Optimization for Timing and Power of VLSI Circuits},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [6]                            <span class=\"papercite_highlight\">L. Cheng<\/span> and P. Gupta, &#8220;A Levelized Variation Modeling Scheme,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_268\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_268_block\"><pre><code class=\"tex bibtex\">@conference{W5,\nauthor = {Cheng, L. and Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W5},\nkeywords = {stat},\ntitle = {{A Levelized Variation Modeling Scheme}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [7]                            T. -B. Chan, A. Pant, <span class=\"papercite_highlight\">L. Cheng<\/span>, and P. Gupta, &#8220;Design Dependent Process Monitoring,&#8221; in <span style=\"font-style: italic\">SRC TECHCON&#8217;10<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_269\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_269_block\"><pre><code class=\"tex bibtex\">@conference{W9,\nauthor = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\nbooktitle = {{SRC TECHCON'10}},\ncategory = {W9},\nkeywords = {stat},\ntitle = {{D}esign {Dependent} {P}rocess {M}onitoring},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c39.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Cheng<\/span>, P. Gupta, and L. He, &#8220;Accounting for Non-linear Dependence Using Function Driven Component Analysis,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_260\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_260_block\"><pre><code class=\"tex bibtex\">@inproceedings{C39,\nauthor = {Cheng, L. and Gupta, P. and He, L.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C39},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C39_paper.pdf},\ntitle = {Accounting for {N}on-linear {D}ependence {U}sing {F}unction {D}riven {C}omponent {A}nalysis},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [9]                            <span class=\"papercite_highlight\">L. Cheng<\/span>, P. Gupta, K. Qian, C. Spanos, and L. He, &#8220;Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_261\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_261_block\"><pre><code class=\"tex bibtex\">@inproceedings{C43,\nauthor = {Cheng, L. and Gupta, P. and Qian, K. and Spanos, C. and He, L.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C43},\nkeywords = {mad},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C43_paper.pdf},\ntitle = {Physically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">L. Cheng<\/span>, P. Gupta, and L. He, &#8220;Efficient Additive Statistical Leakage Estimation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2009.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_266\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_266_block\"><pre><code class=\"tex bibtex\">@article{J9,\nauthor = {Cheng, L. and Gupta, P. and He, L.},\ncategory = {J9},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J9_paper.pdf},\ntitle = {Efficient {A}dditive {S}tatistical {L}eakage {E}stimation},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n\n\n\n<h2 class=\"wp-block-heading has-text-align-center\"><span class=\"ez-toc-section\" id=\"MS-2\"><\/span>M.S.<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:15% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"625\" height=\"1056\" src=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2020\/09\/ananya_lab_photo.jpg\" alt=\"\" class=\"wp-image-746 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Ananya Ravikumar <a href=\"https:\/\/www.linkedin.com\/in\/ananya-ravikumar-61679116b\/\" target=\"_blank\" rel=\"noreferrer noopener\"><img loading=\"lazy\" decoding=\"async\" src=\"\/wp-content\/plugins\/papercite\/img\/iconmonstr-linkedin-4.svg\" width=\"30\" height=\"30\"><\/a>  <\/p>\n\n\n\n<p><strong>Contact:<\/strong><a href=\"&#109;&#x61;&#105;&#x6c;&#116;&#x6f;&#58;&#x73;&#104;&#x75;&#114;&#x75;i&#x6c;i&#x40;u&#x63;l&#x61;&#46;&#x65;d&#117;\"> <\/a> &#x20;&#32;&#x61;&#x6e;a&#x6e;&#121;a&#x72;&#97;v&#x69;&#107;&#x75;&#x6d;a&#x72;&#64;u&#x63;&#108;a&#x2e;&#101;&#x64;&#x75;&#32; <\/p>\n\n\n\n<p><strong>Research interests<\/strong>: Modelling interconnect impact on performance<\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Micron Technology Inc.<\/p>\n<\/div><\/div>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Yizhang Wu<\/p>\n\n\n\n<p><strong>Contact:<\/strong>  &#x20;&#119;&#x75;&#x79;&#105;&#x7a;&#x68;&#97;&#x6e;&#x67;&#32;&#x41;&#x54; &#x75;&#x63;l&#x61;&#32;D&#x4f;&#84; &#x65;&#100;u&#x20;&#32; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Micron\n\n<\/p>\n\n\n\n<p><strong>MS Thesis:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Wu, &#8220;Pin assignment for 2.5d dielet assembly,&#8221; Department of Electrical and Computer Engineering, University of California Los Angeles 2019. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_270\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_270_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH6,\nauthor = {Wu, Yizhang},\ninstitution = {Department of Electrical and Computer Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH6_paper.pdf},\ntitle = {Pin Assignment for 2.5D Dielet Assembly},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e373ea\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e373ea\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j64.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>            <a href='http:\/\/dx.doi.org\/https:\/\/doi.org\/10.1109\/TCAD.2019.2957359' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        W. Wang, <span class=\"papercite_highlight\">Y. Wu<\/span>, and P. Gupta, &#8220;Reverse Engineering for 2.5D Split Manufactured ICs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2020.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_273\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_273_block\"><pre><code class=\"tex bibtex\">@article{J64,\nauthor = {Wang, Wei-Che and Wu, Yizhang and Gupta, Puneet},\ndoi = {https:\/\/doi.org\/10.1109\/TCAD.2019.2957359},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\npublisher = {{IEEE}},\ntitle = {{Reverse Engineering for 2.5D Split Manufactured ICs}},\nyear = {2020}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j60.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang, Y. Yona, <span class=\"papercite_highlight\">Y. Wu<\/span>, S. Diggavi, and P. Gupta, &#8220;SLATE: A Secure Lightweight Entity Authentication Hardware Primitive,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Information Forensics and Security<\/span>, 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_272\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_272_block\"><pre><code class=\"tex bibtex\">@article{J60,\nauthor = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Diggavi, Suhas and Gupta, Puneet},\njournal = {{{IEEE Transactions on Information Forensics and Security}}},\nmonth = {May},\npublisher = {IEEE},\ntitle = {{SLATE: A Secure Lightweight Entity Authentication Hardware Primitive}},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">Y. Wu<\/span>, &#8220;Pin assignment for 2.5d dielet assembly,&#8221; Department of Electrical and Computer Engineering, University of California Los Angeles 2019.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_274\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_274_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH6,\nauthor = {Wu, Yizhang},\ninstitution = {Department of Electrical and Computer Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH6_paper.pdf},\ntitle = {Pin Assignment for 2.5D Dielet Assembly},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c99.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang, Y. Yona, <span class=\"papercite_highlight\">Y. Wu<\/span>, S. Hung, S. Diggavi, and P. Gupta, &#8220;Implementation of Stable PUFs Using Gate Oxide Breakdown,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST)<\/span>,  2017  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_271\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_271_block\"><pre><code class=\"tex bibtex\">@inproceedings{C99,\nauthor = {Wang, Wei-Che and Yona, Yair and Wu, Yizhang and Hung, Szu-Yao and Diggavi, Suhas and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST)}},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C99_paper.pdf},\ntitle = {{Implementation of Stable PUFs Using Gate Oxide Breakdown}},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"1080\" height=\"1349\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/yoojin.jpg\" alt=\"\" class=\"wp-image-206 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Yoo-Jin Chae<\/p>\n\n\n\n<p><strong>Contact:<\/strong>  &#32;&#x79;&#111;&#x6f;j&#x69;n&#99;&#x68;&#97;&#x65;&#32;&#x41;T&#x20;u&#99;&#x6c;&#97;&#x20;D&#x4f;T&#x20;&#x65;&#100;&#x75;&#32;&#x20; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Google   <\/p>\n\n\n\n<p><strong>MS Thesis:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Chae, &#8220;Defect avoidance for extreme ultraviolet mask defects using intentional pattern deformation,&#8221; Department of Electrical and Computer Engineering, University of California Los Angeles 2018. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_275\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_275_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH5,\nauthor = {Chae, Yoo-Jin},\ninstitution = {Department of Electrical and Computer Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH5_paper.pdf},\ntitle = {Defect Avoidance for Extreme Ultraviolet Mask Defects using Intentional Pattern Deformation},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n<\/div><\/div>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Vishesh Dokania<\/p>\n\n\n\n<p><strong>Contact:<\/strong>  &#x20;&#x20;&#x76;&#x64;&#x6f;&#x6b;&#x61;&#x6e;&#x69;&#x61;&#x20;&#x41;&#x54;&#x20;&#x75;&#x63;&#x6c;&#x61;&#x20;&#x44;&#x4f;&#x54;&#32;&#101;&#100;&#117;&#32;&#32;&#32; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Cadence  <\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           V. Dokania, &#8220;Intrusive routing for improved standard cell pin access,&#8221; Department of Electrical Engineering, University of California Los Angeles 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_276\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_276_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR12,\nauthor = {Dokania, Vishesh },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR12_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR12_slides.pdf},\ntitle = {Intrusive Routing for Improved Standard Cell Pin Access},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Nan Lyu<\/p>\n\n\n\n<p><strong>Contact:<\/strong>   <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Huawei  <\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           N. Lyu, &#8220;Leon3 processor variability emulator for delay variability impact on performance,&#8221; Department of Electrical Engineering, University of California Los Angeles 2016. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_277\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_277_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR11,\nauthor = {Lyu, Nan},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR11_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR11_slides.pdf},\ntitle = {Leon3 Processor Variability Emulator for Delay Variability Impact on Performance},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Abishek Bhatia<\/p>\n\n\n\n<p><strong>Contact:<\/strong>    <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Xilinx  <\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. Bhatia, &#8220;Varleon: fpga based processor variability emulator for variation aware software,&#8221; Department of Electrical Engineering, University of California Los Angeles 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_278\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_278_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR9,\nauthor = {Bhatia, Abishek},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR9_paper.pdf},\ntitle = {VarLEON: FPGA Based Processor Variability Emulator for Variation Aware Software},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n<p><!--EndFragment--><\/p>\n\n\n<p class=\"has-text-align-center has-large-font-size\">Mukul Gupta<\/p>\n\n\n\n<p><strong>Contact:<\/strong>     &#32;&#109;&#x75;&#x6b;u&#108;&#103;&#x20;&#x41;&#x54; &#117;&#99;&#x6c;&#x61; D&#79;&#x54;&#x20;&#x65;d&#117;&#32;&#x20;      <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Qualcomm<\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e3741f\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e3741f\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c74.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c74_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, Y. Badr, <span class=\"papercite_highlight\">M. Gupta<\/span>, N. Jin, and P. Gupta, &#8220;Comprehensive Die-level Assessment of Design Rules and Layouts,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_280\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_280_block\"><pre><code class=\"tex bibtex\">@inproceedings{C74,\nauthor = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {dats,dre},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_slides.pdf},\ntitle = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j30.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, <span class=\"papercite_highlight\">M. Gupta<\/span>, and P. Gupta, &#8220;Framework for exploring the interaction between design rules and overlay control,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, vol. 12, iss. 3, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_281\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_281_block\"><pre><code class=\"tex bibtex\">@article{J30,\nauthor = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {variability},\nmonth = {August },\nnumber = {3},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J30_paper.pdf},\ntitle = {Framework for exploring the interaction between design rules and overlay control},\nvolume = {12},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c69.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, <span class=\"papercite_highlight\">M. Gupta<\/span>, and P. Gupta, &#8220;A Framework for Exploring the Interaction between Design Rules and Overlay Control,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_279\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_279_block\"><pre><code class=\"tex bibtex\">@inproceedings{C69,\nauthor = {Ghaida, R. S. and Gupta, Mukul and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C69},\nkeywords = {overlay, design rules, dre, alignment},\nmonth = {Feburary},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C69_paper.pdf},\ntitle = {A {F}ramework for {E}xploring the {I}nteraction between {D}esign {R}ules and {O}verlay {C}ontrol},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [4]                            R. S. Ghaida, <span class=\"papercite_highlight\">M. Gupta<\/span>, and P. Gupta, &#8220;A framework for exploring the interaction between design rules and overlay control,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_282\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_282_block\"><pre><code class=\"tex bibtex\">@conference{W11,\nauthor = {Ghaida, R. S. and Gupta, M. and Gupta, P.},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W11},\nkeywords = {dats, dre, design rules, overlay, alignment, process, multiple-patterning, lithography},\ntitle = {A Framework for Exploring the Interaction Between Design Rules and Overlay Control},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Tanaya Sahu<\/p>\n\n\n\n<p><strong>Contact:<\/strong>       tanay&#97;&#115;&#97;&#104;&#117;&#32;&#65;&#84;&#32;&#117;&#x63;&#x6c;&#x61;&#x20;&#x44;&#x4f;&#x54;&#x20;&#x65;&#x64;&#x75;&#x20;&#x20;&#x20; <\/p>\n\n\n\n<p> <strong>Last known coordinates:<\/strong> Intel        <\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37444\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37444\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c64.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c64_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, <span class=\"papercite_highlight\">T. Sahu<\/span>, P. Kulkarni, and P. Gupta, &#8220;A methodology for the early exploration of design rules for multiple-patterning technologies,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_283\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_283_block\"><pre><code class=\"tex bibtex\">@inproceedings{C64,\nauthor = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C64},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_slides.pdf},\ntitle = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><br \/><!--EndFragment--><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Chia-Hao Chang<\/p>\n\n\n\n<p><strong>Contact:<\/strong>      &#32;&#x20;&#x20;&#99;&#x68;&#x61;n&#x67;&#x63;h&#105;&#x61;h&#97;&#x6f; &#65;&#x54; &#117;&#x63;l&#97;&#x20;&#x44;&#79;&#x54;&#x20;&#101;&#x64;&#x75; &#x20; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong>      <\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37468\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37468\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]                            L. Lai, <span class=\"papercite_highlight\">C. Chang<\/span>, and P. Gupta, &#8220;Exploring total power saving from high temperature of server operations,&#8221;  2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_284\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_284_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP2,\nauthor = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/5898p020},\ntitle = {Exploring Total Power Saving from High Temperature of Server Operations},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [2]                            L. Lai, <span class=\"papercite_highlight\">C. Chang<\/span>, and P. Gupta, &#8220;Exploring total power saving from high temperature of server operations,&#8221; , 2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_285\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_285_block\"><pre><code class=\"tex bibtex\">@article{TR1,\nauthor = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},\nkeywords = {hsi},\npaperurl = {http:\/\/escholarship.org\/uc\/item\/5898p020},\ntitle = {Exploring Total Power Saving from High Temperature of Server Operations},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><br \/><!--EndFragment--><!--EndFragment--><!--EndFragment--><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Ankur Sharma<\/p>\n\n\n\n<p><strong>Contact:<\/strong>    &#x20;a&#x6e;&#107;&#x75;&#114;s&#x68;a&#x72;&#109;&#x61;&#32;A&#x54;&#32;&#x75;&#99;l&#x61; &#x44;&#79;&#x54;&#32;e&#x64;u&#x20;&#32;&#x20;&#x20; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong>  <\/p>\n\n\n\n<p><strong>MS Thesis:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. Sharma, &#8220;Understanding software application behaviour in presence of permanent and intermittent hardware faults,&#8221; Department of Electrical Engineering, University of California Los Angeles 2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_286\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_286_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH3,\nauthor = {Sharma, Ankur},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH3_paper.pdf},\ntitle = {Understanding Software Application Behaviour in Presence of Permanent and Intermittent Hardware Faults},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e3748d\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e3748d\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c72.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">A. Sharma<\/span>, J. Sloan, L. F. Wanner, S. H. Elmalaki, M. B. Srivastava, and P. Gupta, &#8220;Towards Analyzing and Improving Robustness of Software Applications to Intermittent and Permanent Faults in Hardware,&#8221; in <span style=\"font-style: italic\">Proc. IEEE International Conference on Computer Design<\/span>,  2013  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_287\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_287_block\"><pre><code class=\"tex bibtex\">@inproceedings{C72,\nauthor = {Sharma, Ankur and Sloan, Joseph and Wanner, Lucas F. and Elmalaki, Salma H. and Srivastava, Mani B. and Gupta, Puneet},\nbooktitle = {{Proc. IEEE International Conference on Computer Design}},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C72_paper.pdf},\ntitle = {{T}owards {A}nalyzing and {I}mproving {R}obustness of {S}oftware {A}pplications to {I}ntermittent and {P}ermanent {F}aults in {H}ardware},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">A. Sharma<\/span>, &#8220;Understanding software application behaviour in presence of permanent and intermittent hardware faults,&#8221; Department of Electrical Engineering, University of California Los Angeles 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_288\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_288_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH3,\nauthor = {Sharma, Ankur},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH3_paper.pdf},\ntitle = {Understanding Software Application Behaviour in Presence of Permanent and Intermittent Hardware Faults},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Ning Jin<\/p>\n\n\n\n<p><strong>Contact:<\/strong>     <\/p>\n\n\n\n<p> <strong>Last known coordinates:<\/strong> LinkedIn      <\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           N. Jin, &#8220;Modelling of guardband reduction on design area,&#8221; Department of Electrical Engineering, University of California Los Angeles 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_289\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_289_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR8,\nauthor = {Jin, Ning},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {mad, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR8_paper.pdf},\ntitle = {Modelling of Guardband Reduction on Design Area},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>  <\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e374aa\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e374aa\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c74.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c74_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, Y. Badr, M. Gupta, <span class=\"papercite_highlight\">N. Jin<\/span>, and P. Gupta, &#8220;Comprehensive Die-level Assessment of Design Rules and Layouts,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_290\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_290_block\"><pre><code class=\"tex bibtex\">@inproceedings{C74,\nauthor = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {dats,dre},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_slides.pdf},\ntitle = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">N. Jin<\/span>, &#8220;Modelling of guardband reduction on design area,&#8221; Department of Electrical Engineering, University of California Los Angeles 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_291\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_291_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR8,\nauthor = {Jin, Ning},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {mad, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR8_paper.pdf},\ntitle = {Modelling of Guardband Reduction on Design Area},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><br \/><!--EndFragment--><!--EndFragment--><!--EndFragment--><!--EndFragment--><!--EndFragment--><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Jingyuan Dong<\/p>\n\n\n\n<p><strong>Contact:<\/strong>   <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Snapchat      <\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Dong, &#8220;High Level Battery Modeling Considering Discharge Rate and Temperature Effects,&#8221; Department of Electrical Engineering, University of California Los Angeles 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_292\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_292_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR7,\nauthor = {Dong, Jingyuan},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR7_paper.pdf},\ntitle = {{High Level Battery Modeling Considering Discharge Rate and Temperature Effects}},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Parag Kulkarni<\/p>\n\n\n\n<p><strong>Contact:<\/strong>        &#32;&#32;&#x70;&#x61;r&#97;&#103;&#x6b;&#x20;&#x41;T&#32;&#117;&#x63;&#x6c;a &#68;&#x4f;&#x54;&#x20;e&#100;&#117;&#x20;&#x20;   <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Google \n\n<\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]                   P. Kulkarni, &#8220;Trading Accuracy for Power with an Under-designed Multiplier Architecture,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_293\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_293_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR6,\nauthor = {Kulkarni, Parag },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR6_paper.pdf},\ntitle = {{Trading Accuracy for Power with an Under-designed\nMultiplier Architecture}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>  <\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37556\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37556\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c76.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c76_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">P. Kulkarni<\/span>, P. Gupta, and R. Beraha, &#8220;Minimizing Clock Domain Crossing in Network on Chip Interconnect,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_296\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_296_block\"><pre><code class=\"tex bibtex\">@inproceedings{C76,\nauthor = {Kulkarni, Parag and Gupta, Puneet and Beraha, Rudy},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\nkeywords = {dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C76_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C76_slides.pdf},\ntitle = {{M}inimizing {C}lock {D}omain {C}rossing in {N}etwork on {C}hip {I}nterconnect},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c64.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c64_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            R. S. Ghaida, T. Sahu, <span class=\"papercite_highlight\">P. Kulkarni<\/span>, and P. Gupta, &#8220;A methodology for the early exploration of design rules for multiple-patterning technologies,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_295\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_295_block\"><pre><code class=\"tex bibtex\">@inproceedings{C64,\nauthor = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C64},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_slides.pdf},\ntitle = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c54.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c54_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            <span class=\"papercite_highlight\">P. Kulkarni<\/span>, P. Gupta, and M. Ercegovac, &#8220;Trading Accuracy for Power with an Underdesigned Multiplier Architecture,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_294\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_294_block\"><pre><code class=\"tex bibtex\">@inproceedings{C54,\nauthor = {Kulkarni, Parag and Gupta, Puneet and Ercegovac, Milos},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C54},\nkeywords = {low power, hsi},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C54_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C54_slides.pdf},\ntitle = {{T}rading {A}ccuracy for {P}ower with an {U}nderdesigned {M}ultiplier {A}rchitecture},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [4]                            <span class=\"papercite_highlight\">P. Kulkarni<\/span>, P. Gupta, and M. D. Ercegovac, &#8220;Trading accuracy for power in a multiplier architecture,&#8221; <span style=\"font-style: italic\">Journal of Low Power Electronics<\/span>, 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_297\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_297_block\"><pre><code class=\"tex bibtex\">@article{J16,\nauthor = {Kulkarni, P. and Gupta, P. and Ercegovac, M.D.},\njournal = {{Journal of Low Power Electronics}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/JOLPE_v3.pdf},\ntitle = {Trading Accuracy for Power in a Multiplier Architecture},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [5]                            <span class=\"papercite_highlight\">P. Kulkarni<\/span>, &#8220;Trading Accuracy for Power with an Under-designed Multiplier Architecture,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_298\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_298_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR6,\nauthor = {Kulkarni, Parag },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR6_paper.pdf},\ntitle = {{Trading Accuracy for Power with an Under-designed\nMultiplier Architecture}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><br \/><!--EndFragment--><!--EndFragment--><!--EndFragment--><!--EndFragment--><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Charwak S Apte<\/p>\n\n\n\n<p><strong>Contact:<\/strong>        c&#104;&#97;&#114;&#119;&#97;&#107;&#32;&#x41;&#x54;&#x20;&#x65;&#x65;&#x20;&#x44;&#x4f;&#x54; ucl&#97;&#32;&#68;&#79;&#84;&#32;&#101;&#x64;&#x75;&#x20;&#x20;&#x20;&#x20; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> AMD<\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]                   C. Apte, &#8220;Power Consumption Variability in Embedded Processors,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_299\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_299_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR5,\nauthor = {Apte, Charwak},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR5_paper.pdf},\ntitle = {{Power Consumption Variability in Embedded\nProcessors}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37585\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37585\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j23.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Wanner, <span class=\"papercite_highlight\">C. Apte<\/span>, R. Balani, P. Gupta, and M. Srivastava, &#8220;Hardware Variability-Aware Duty Cycling for Embedded Sensors,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_302\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_302_block\"><pre><code class=\"tex bibtex\">@article{J23,\nauthor = {Lucas Wanner and Charwak Apte and Rahul Balani and Puneet Gupta and Mani Srivastava},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/j23.pdf},\ntitle = {{H}ardware {V}ariability-{A}ware {D}uty {C}ycling for {E}mbedded {S}ensors},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c56.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c56_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            L. Wanner, R. Balani, S. Zahedi, <span class=\"papercite_highlight\">C. Apte<\/span>, P. Gupta, and M. Srivastava, &#8220;Variability Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems,&#8221; in <span style=\"font-style: italic\">Design, Automation, and Test in Europe (DATE)<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_300\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_300_block\"><pre><code class=\"tex bibtex\">@inproceedings{C56,\nauthor = {Wanner, Lucas and Balani, Rahul and Zahedi, Sadaf and Apte, Charwak and Gupta, Puneet and Srivastava, Mani },\nbooktitle = {{Design, Automation, and Test in Europe (DATE)}},\ncategory = {C56},\nkeywords = {variabilty-aware, embedded sensing, hsi},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C56_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C56_slides.pdf},\ntitle = {{V}ariability {A}ware {D}uty {C}ycle {S}cheduling in {L}ong {R}unning {E}mbedded {S}ensing {S}ystems},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [3]                            <span class=\"papercite_highlight\">C. Apte<\/span>, &#8220;Power Consumption Variability in Embedded Processors,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_303\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_303_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR5,\nauthor = {Apte, Charwak},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR5_paper.pdf},\ntitle = {{Power Consumption Variability in Embedded\nProcessors}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c58.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c58_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            L. Wanner, <span class=\"papercite_highlight\">C. Apte<\/span>, R. Balani, P. Gupta, and M. Srivastava, &#8220;A Case for Opportunistic Embedded Sensing In Presence of Hardware Power Varibility,&#8221; in <span style=\"font-style: italic\">HotPower&#8217;10<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_301\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_301_block\"><pre><code class=\"tex bibtex\">@conference{C58,\nauthor = {Wanner, Lucas and Apte, Charwak and Balani, Rahul and Gupta, Puneet and Srivastava, Mani},\nbooktitle = {{HotPower'10}},\ncategory = {C58},\nkeywords = {embedded sensing, leakage power, duty cycling, hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C58_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C58_slides.pdf},\ntitle = {{A} {C}ase for {O}pportunistic {E}mbedded {S}ensing {I}n {P}resence of {H}ardware {P}ower {V}aribility},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><br \/><!--EndFragment--><!--EndFragment--><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:19% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"1944\" height=\"2592\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/Santiago.jpg\" alt=\"\" class=\"wp-image-210 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Santiago Mok<\/p>\n\n\n\n<p><strong>Contact:<\/strong>         &#32;&#115;&#x6d;&#x6f;&#x6b; &#65;&#84;&#x20;&#x65;&#x65; D&#79;&#x54;&#x20;&#x75;cl&#97;&#32;&#x44;&#x4f;&#x54; &#101;&#100;&#x75;&#x20;&#x20;  <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Intel  <\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Mok, &#8220;Post-Layout Sizing for Leakage Power Optimization: A Comparative Study,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_304\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_304_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR4,\nauthor = {Mok, Santiago},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR4_paper.pdf},\ntitle = {{Post-Layout Sizing for Leakage Power Optimization: A Comparative Study}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>  <\/p>\n<\/div><\/div>\n\n\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e375b0\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e375b0\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j25.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Mok<\/span>, J. Lee, and P. Gupta, &#8220;Discrete sizing for leakage power optimization in physical design: a comparative study,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_305\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_305_block\"><pre><code class=\"tex bibtex\">@article{J25,\nauthor = {Santiago Mok and John Lee and Puneet Gupta},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J25_paper.pdf},\ntitle = {Discrete Sizing for Leakage Power Optimization in Physical Design: A Comparative Study},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Mok<\/span>, &#8220;Post-Layout Sizing for Leakage Power Optimization: A Comparative Study,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_306\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_306_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR4,\nauthor = {Mok, Santiago},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR4_paper.pdf},\ntitle = {{Post-Layout Sizing for Leakage Power Optimization: A Comparative Study}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ug6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">S. Mok<\/span>, &#8220;Propagation Delay Approximation Considering Effective Capacitance and Slew Degradation,&#8221; University of California, Los Angeles 2009.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_307\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_307_block\"><pre><code class=\"tex bibtex\">@techreport{UG6,\nauthor = {Mok, Santiago},\ninstitution = {University of California, Los Angeles},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/UG6_paper.pdf},\ntitle = {{Propagation Delay Approximation Considering Effective Capacitance and Slew Degradation}},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"303\" height=\"401\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/pic.jpg\" alt=\"\" class=\"wp-image-209 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Aashish Pant<\/p>\n\n\n\n<p><strong>Contact:<\/strong>   &#97;&#112;&#x61;&#x6e;t &#65;&#84;&#x20;&#x75;cl&#97;&#32;&#x44;&#x4f;T &#101;&#x64;&#x75;&#x20; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Facebook<\/p>\n\n\n\n<p><strong>MS Thesis: <\/strong> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. Pant, &#8220;Hardware-software interface in the presence of hardware manufacturing variations,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_308\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_308_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH1,\nauthor = {Pant, Aashish },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH1_paper.pdf},\ntitle = {Hardware-Software Interface in the Presence of Hardware Manufacturing Variations},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n<\/div><\/div>\n\n\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e375da\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e375da\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j21.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Chan, <span class=\"papercite_highlight\">A. Pant<\/span>, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_313\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_313_block\"><pre><code class=\"tex bibtex\">@article{J21,\nauthor = {Chan, Tuck-Boon and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {Process monitoring, wafer pruning, variability},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J21_paper.pdf},\ntitle = {{D}esign {D}ependent {P}rocess {M}onitoring for {W}afer {M}anufacturing and {T}est {C}ost {R}eduction},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [2]                            <span class=\"papercite_highlight\">A. Pant<\/span>, P. Gupta, and M. van der Schaar, &#8220;Appadapt: opportunistic application adaptation in presence of hardware variation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_312\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_312_block\"><pre><code class=\"tex bibtex\">@article{J17,\nauthor = {Aashish Pant and Gupta, Puneet and Mihaela van der Schaar},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/VarAwareAdapt.pdf},\ntitle = {AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c53.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c53_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, <span class=\"papercite_highlight\">A. Pant<\/span>, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_311\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_311_block\"><pre><code class=\"tex bibtex\">@inproceedings{C53,\nauthor = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C53},\nkeywords = {process variation, process monitoring, dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_slides.pdf},\ntitle = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c49.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">A. Pant<\/span>, P. Gupta, and M. van der Schaar, &#8220;Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability,&#8221; in <span style=\"font-style: italic\">ACM Great Lakes Symposium on Very Large Scale Integration<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_310\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_310_block\"><pre><code class=\"tex bibtex\">@inproceedings{C49,\nauthor = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},\nbooktitle = {{ACM Great Lakes Symposium on Very Large Scale Integration}},\ncategory = {C49},\nkeywords = {hsi},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C49_paper.pdf},\ntitle = {{S}oftware {A}daptation in {Q}uality {S}ensitive {A}pplications to {D}eal with {H}ardware {V}ariability},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c48.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Sartori, <span class=\"papercite_highlight\">A. Pant<\/span>, R. Kumar, and P. Gupta, &#8220;Variation Aware Speed Binning of Multi-core Processors,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_309\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_309_block\"><pre><code class=\"tex bibtex\">@inproceedings{C48,\nauthor = {Sartori, John and Pant, Aashish and Kumar, Rakesh and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\ncategory = {C48},\nkeywords = {hsi},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C48_paper.pdf},\ntitle = {{V}ariation {A}ware {S}peed {B}inning of {M}ulti-core {P}rocessors},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">A. Pant<\/span>, &#8220;Hardware-software interface in the presence of hardware manufacturing variations,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_314\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_314_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH1,\nauthor = {Pant, Aashish },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH1_paper.pdf},\ntitle = {Hardware-Software Interface in the Presence of Hardware Manufacturing Variations},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [7]                            T. -B. Chan, <span class=\"papercite_highlight\">A. Pant<\/span>, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring,&#8221; in <span style=\"font-style: italic\">SRC TECHCON&#8217;10<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_317\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_317_block\"><pre><code class=\"tex bibtex\">@conference{W9,\nauthor = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\nbooktitle = {{SRC TECHCON'10}},\ncategory = {W9},\nkeywords = {stat},\ntitle = {{D}esign {Dependent} {P}rocess {M}onitoring},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [8]                            <span class=\"papercite_highlight\">A. Pant<\/span>, P. Gupta, and M. van der Schaar, &#8220;Software Adaptation to Handle Manufacturing Variability and Relax Hardware Overdesign,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_315\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_315_block\"><pre><code class=\"tex bibtex\">@conference{W2,\nauthor = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W2},\nkeywords = {hsi-p1},\ntitle = {{S}oftware {A}daptation to {H}andle {M}anufacturing {Variability} and {R}elax {H}ardware {O}verdesign},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [9]                            J. Sartori, <span class=\"papercite_highlight\">A. Pant<\/span>, P. Gupta, and R. Kumar, &#8220;On Performance Binning of Multicore Processors,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_316\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_316_block\"><pre><code class=\"tex bibtex\">@conference{W3,\nauthor = {Sartori, John and Pant, Aashish and Gupta, Puneet and Kumar, Rakesh},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W3},\nkeywords = {hsi-p2},\ntitle = {{O}n {P}erformance {B}inning of {M}ulticore {P}rocessors},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<div class=\"wp-block-media-text alignwide\" style=\"grid-template-columns:20% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"410\" height=\"550\" src=\"http:\/\/nanocad.ee.ucla.edu\/wp-content\/uploads\/2019\/10\/tuckie.jpg\" alt=\"\" class=\"wp-image-211 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\">\n<p class=\"has-large-font-size\">Tuck Boon Chan<\/p>\n\n\n\n<p><strong>Contact:<\/strong>  &#x20;&#116;u&#x63;&#x6b;&#105;e&#x20;&#x41;&#84; &#x75;&#x63;&#108;a&#x20;&#x44;&#79;T&#x20;&#101;&#100;u&#x20;&#32;  <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Qualcomm<\/p>\n<\/div><\/div>\n\n\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e3760e\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e3760e\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j44.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, and A. B. Kahng, &#8220;Benchmarking of Mask Fracturing Heuristics,&#8221; in <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2016  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_328\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_328_block\"><pre><code class=\"tex bibtex\">@inproceedings{J44,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. },\nbooktitle = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ncategory = {J44},\nkeywords = {dats},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J44_paper.pdf},\ntitle = {Benchmarking of {M}ask {F}racturing {H}euristics},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c80.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, A. B. Kahng, and E. Sahouria, &#8220;Benchmarking of Mask Fracturing Heuristics,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2014  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_323\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_323_block\"><pre><code class=\"tex bibtex\">@inproceedings{C80,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. and Sahouria, Emile},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C80},\nkeywords = {dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C80_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C80_slides.pdf},\ntitle = {Benchmarking of {M}ask {F}racturing {H}euristics},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [3]                            Y. Agarwal, A. Bishop, <span class=\"papercite_highlight\">T. Chan<\/span>, M. Fotjik, P. Gupta, A. Kahng, L. Lai, P. Martin, M. Srivastava, D. Sylvester, L. Wanner, and B. Zhang, &#8220;Redcooper: hardware sensor enabled variability software testbed for lifetime energy constrained application,&#8221;  2014.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_329\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_329_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP1,\nauthor = {Agarwal, Yuvraj and Bishop, Alex and Chan, Tuck-Boon and Fotjik, Matt and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen and Martin, Paul and Srivastava, Mani and Sylvester, Dennis and Wanner, Lucas and Zhang, Bing},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/1c21g217},\ntitle = {Redcooper: Hardware sensor enabled variability software testbed for lifetime energy constrained application},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j31.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">T. Chan<\/span>, P. Gupta, A. B. Kahng, and L. Lai, &#8220;Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2013.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_327\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_327_block\"><pre><code class=\"tex bibtex\">@article{J31,\nauthor = {Chan, Tuck-Boon and Gupta, Puneet and Kahng, A. B. and Lai, Liangzhen},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi, DDRO},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J31_paper.pdf},\ntitle = {{S}ynthesis and {A}nalysis of {D}esign-{D}ependent {R}ing {O}scillator ({D}{D}{R}{O}) {P}erformance {M}onitors},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c60.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c60_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. B. Chan, P. Gupta, A. Kahng, and L. Lai, &#8220;DDRO: a Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,&#8221; in <span style=\"font-style: italic\">ISQED<\/span>,  2012  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_322\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_322_block\"><pre><code class=\"tex bibtex\">@inproceedings{C60,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen},\nbooktitle = {{ISQED}},\ncategory = {C60},\nkeywords = {hsi, DDRO},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C60_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C60_slides.pdf},\ntitle = {{DDRO}: A {N}ovel {P}erformance {M}onitoring {M}ethodology {B}ased on {D}esign-{D}ependent {R}ing {O}scillators},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j21.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">T. Chan<\/span>, A. Pant, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2012.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_326\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_326_block\"><pre><code class=\"tex bibtex\">@article{J21,\nauthor = {Chan, Tuck-Boon and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {Process monitoring, wafer pruning, variability},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J21_paper.pdf},\ntitle = {{D}esign {D}ependent {P}rocess {M}onitoring for {W}afer {M}anufacturing and {T}est {C}ost {R}eduction},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c55.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c55_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, J. Sartori, P. Gupta, and R. Kumar, &#8220;On the Efficacy of NBTI Mitigation Techniques,&#8221; in <span style=\"font-style: italic\">Design, Automation, and Test in Europe (DATE)<\/span>,  2011  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_321\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_321_block\"><pre><code class=\"tex bibtex\">@inproceedings{C55,\nauthor = {Chan, T.-B. and Sartori, John and Gupta, Puneet and Kumar, Rakesh},\nbooktitle = {{Design, Automation, and Test in Europe (DATE)}},\ncategory = {C55},\nkeywords = {variabilty-aware, embedded sensing, hsi, ucla_rdmode},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C55_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C55_slides.pdf},\ntitle = {{O}n the {E}fficacy of {NBTI} {M}itigation {T}echniques},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. B. Chan, A. A. Kagalwalla, and P. Gupta, &#8220;Measurement and Optimization of Electrical Process Window,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2011.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_325\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_325_block\"><pre><code class=\"tex bibtex\">@article{J15,\nauthor = {Chan, T.B. and Kagalwalla, Abde Ali and Gupta, P. },\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J15_paper.pdf},\ntitle = {{M}easurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c53.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c53_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, A. Pant, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_320\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_320_block\"><pre><code class=\"tex bibtex\">@inproceedings{C53,\nauthor = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C53},\nkeywords = {process variation, process monitoring, dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_slides.pdf},\ntitle = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c46.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c46_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, A. A. Kagalwalla, and P. Gupta, &#8220;Measurement and Optimization of Electrical Process Window,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_319\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_319_block\"><pre><code class=\"tex bibtex\">@inproceedings{C46,\nauthor = {Chan, T.-B. and Kagalwalla, Abde Ali and Gupta, P.},\nbooktitle = {{Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration}},\ncategory = {C46},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C46_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C46_slides.pdf},\ntitle = {Measurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c45.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/c45_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan and P. Gupta, &#8220;On Electrical Modeling of Imperfect Diffusion Patterning,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_318\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_318_block\"><pre><code class=\"tex bibtex\">@inproceedings{C45,\nauthor = {Chan, T.-B. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C45},\nkeywords = {dats, mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C45_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C45_slides.pdf},\ntitle = {On {E}lectrical {M}odeling of {I}mperfect {D}iffusion {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/ip6_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            T. -B. Chan, R. S. Ghaida, and P. Gupta, &#8220;Electrical Modeling of Lithographic Imperfections,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2010  &#8211; <b>Embedded Tutorial<\/b> <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_324\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_324_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP6,\nauthor = {Chan, T.-B. and Ghaida, R. S. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {IP6},\nkeywords = {mad},\nnote = {Embedded Tutorial},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP6_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP6_slides.pdf},\ntitle = {{E}lectrical {M}odeling of {L}ithographic {I}mperfections},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [13]                            T. -B. Chan, A. Pant, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring,&#8221; in <span style=\"font-style: italic\">SRC TECHCON&#8217;10<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_331\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_331_block\"><pre><code class=\"tex bibtex\">@conference{W9,\nauthor = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\nbooktitle = {{SRC TECHCON'10}},\ncategory = {W9},\nkeywords = {stat},\ntitle = {{D}esign {Dependent} {P}rocess {M}onitoring},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [14]                            T. -B. Chan, P. Gupta, V. Balakrishnan, and Y. Cao, &#8220;Extended Burn-in for Reduced Vth Variation,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_330\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_330_block\"><pre><code class=\"tex bibtex\">@conference{W4,\nauthor = {Chan, T.-B. and Gupta, Puneet and Balakrishnan, Varsha and Cao, Yu},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W4},\nkeywords = {dats},\ntitle = {{E}xtended {B}urn-in for {R}educed {V}th {V}ariation},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><code data-rich-text-format-boundary=\"true\"><\/code><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Kasibhatla Amarnath<\/p>\n\n\n\n<p><strong>Contact:<\/strong>      &#97;&#x6d;&#x61;r&#32;&#65;&#x54;&#x20;e&#101;&#x20;&#x44;O&#84;&#32;&#x75;&#x63;l&#97;&#x20;&#x44;O&#84;&#32;&#x65;&#x64;u&#32;&#x20;&#x20; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Intel <\/p>\n\n\n\n<p><strong>MS Thesis:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. Kasibhatla, &#8220;Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_332\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_332_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR3,\nauthor = {Kasibhatla, Amarnath},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR3_paper.pdf},\ntitle = {{Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37640\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37640\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c50.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    P. Gupta, A. Kahng, <span class=\"papercite_highlight\">A. Kasibhatla<\/span>, and P. Sharma, &#8220;Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_333\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_333_block\"><pre><code class=\"tex bibtex\">@inproceedings{C50,\nauthor = {Gupta, Puneet and Kahng, Andrew and Kasibhatla, Amarnath and Sharma, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C50},\nkeywords = {sizing, eyecharts},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C50_paper.pdf},\ntitle = {{E}yecharts: {C}onstructive {B}enchmarking of {G}ate {S}izing {H}euristics},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">A. Kasibhatla<\/span>, &#8220;Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_334\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_334_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR3,\nauthor = {Kasibhatla, Amarnath},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR3_paper.pdf},\ntitle = {{Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><br \/><!--EndFragment--><!--EndFragment--><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Dominic Reinhard<\/p>\n\n\n\n<p><strong>Contact:<\/strong>        &#x20;&#x64;&#111;m&#x69;&#x6e;&#x69;&#99;r&#x20;&#x41;&#x54;&#32;u&#x63;&#x6c;&#x61;&#32;D&#x4f;&#x54;&#x20;&#101;d&#x75;&#x20;     <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Western Digital  <\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           D. Reinhard, &#8220;On Comparing Conventional and Electrically Driven OPC Techniques,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_335\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_335_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR2,\nauthor = {Reinhard, Dominic},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {mad. msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR2_paper.pdf},\ntitle = {{On Comparing Conventional and Electrically Driven OPC Techniques}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e37668\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e37668\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">D. Reinhard<\/span>, &#8220;On Comparing Conventional and Electrically Driven OPC Techniques,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_337\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_337_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR2,\nauthor = {Reinhard, Dominic},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {mad. msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR2_paper.pdf},\ntitle = {{On Comparing Conventional and Electrically Driven OPC Techniques}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [2]                            P. Gupta and <span class=\"papercite_highlight\">D. Reinhard<\/span>, &#8220;On Comparing Conventional and Electrically Driven OPC Techniques,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2009  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_336\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_336_block\"><pre><code class=\"tex bibtex\">@inproceedings{C42,\nauthor = {Gupta, P. and Reinhard, D.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\ncategory = {C42},\nkeywords = {dats},\nmonth = {},\ntitle = {On {C}omparing {C}onventional and {E}lectrically {D}riven {OPC} {T}echniques},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><br \/><!--EndFragment--><!--EndFragment--><!--EndFragment--><!--EndFragment--><\/p>\n\n\n<hr class=\"wp-block-separator has-css-opacity\"\/>\n\n\n\n<p class=\"has-text-align-center has-large-font-size\">Viswakiran Popuri<\/p>\n\n\n\n<p><strong>Contact:<\/strong>         &#32;&#x76;&#105;&#x73;w&#97;&#x20;&#65;&#x54; &#x65;e&#32;&#x44;&#79;&#x54; &#x75;&#x63;&#108;&#x61; &#x44;O&#84;&#x20;&#101;&#x64;u&#x20; <\/p>\n\n\n\n<p><strong>Last known coordinates:<\/strong> Aquantia  <\/p>\n\n\n\n<p><strong>MS Report:<\/strong>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           V. Popuri, &#8220;Bias-driven Robust Analog Circuit Sizing Scheme,&#8221; Department of Electrical Engineering, University of California Los Angeles 2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_338\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_338_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR1,\nauthor = {Popuri, Viswakiran},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR1_paper.pdf},\ntitle = {{Bias-driven Robust Analog Circuit Sizing Scheme}},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n\n\n<p><!--EndFragment--><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><span class=\"collapseomatic \" id=\"id69f27e4e3768f\"  tabindex=\"0\" title=\"Publications\"    >Publications<\/span><div id=\"target-id69f27e4e3768f\" class=\"collapseomatic_content \"><\/code><\/p>\n<p><ul class=\"papercite_bibliography\">          [1]                            <span class=\"papercite_highlight\">V. Popuri<\/span>, P. Gupta, and S. Pamarti, &#8220;Bias-Driven Robust Analog Circuit Sizing Scheme,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_340\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_340_block\"><pre><code class=\"tex bibtex\">@conference{W8,\nauthor = {Popuri, V. and Gupta, P. and Pamarti, S.},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W8},\nkeywords = {dats},\ntitle = {{Bias-Driven Robust Analog Circuit Sizing Scheme}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    <span class=\"papercite_highlight\">V. Popuri<\/span>, &#8220;Bias-driven Robust Analog Circuit Sizing Scheme,&#8221; Department of Electrical Engineering, University of California Los Angeles 2009.  <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_339\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_339_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR1,\nauthor = {Popuri, Viswakiran},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR1_paper.pdf},\ntitle = {{Bias-driven Robust Analog Circuit Sizing Scheme}},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul><\/p>\n<p><code data-rich-text-format-boundary=\"true\"><\/div><\/code><br \/><!--EndFragment--><!--EndFragment--><!--EndFragment--><!--EndFragment--><\/p>","protected":false},"excerpt":{"rendered":"<p>Faculty (Principal Investigator) Professor Puneet Gupta Homepage: http:\/\/www.ee.ucla.edu\/~puneet&nbsp;&nbsp;&nbsp; Contact: Publications Post Docs Jooyeon Jeong Contact: PhD Students Alexander Graening Contact: George Karfakis Contact: Zhichao Chen&hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":23,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-25","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/25","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=25"}],"version-history":[{"count":70,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/25\/revisions"}],"predecessor-version":[{"id":1393,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/25\/revisions\/1393"}],"up":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/23"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=25"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}