{"id":168,"date":"2019-10-02T21:08:09","date_gmt":"2019-10-02T21:08:09","guid":{"rendered":"http:\/\/nanocad.ee.ucla.edu\/?page_id=168"},"modified":"2019-10-07T21:51:55","modified_gmt":"2019-10-07T21:51:55","slug":"hardware-software-interface-in-presence-of-variability","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=168","title":{"rendered":"Hardware-Software Interface in Presence of Variability"},"content":{"rendered":"\n<p>While a well-de\ufb01ned \ufb01rm hardware-software in- terface enabled advances in software and hardware design methods, it is increasingly harder to sustain as the newer semiconductor technologies exhibit growing manufacturing variabil- ity across di\ufb00erent instances of a chip,  aging-related wear-out,  and variability due to the operating environment.  We are developing techniques to establish a bidirectional data\ufb02ow between the system\/application layer and the physical\/circuit implementation layer to en- able software to opportunistically take advantage of underdesigned hardware systems.  The resulting  <strong>Underdesigned  and  Opportunistic  (UnO)  computing<\/strong>  machines  monitor  hardware power\/performance and use instance-speci\ufb01c adaptation in software to relax variation-induced guard-bands in hardware design. <\/p>\n\n\n\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=168\/#Circuit_Performance_Monitoring\" >Circuit Performance Monitoring<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=168\/#Hardware_Variability-Aware_Duty_Cycling_for_Embedded_Sensors\" >Hardware Variability-Aware Duty Cycling for Embedded Sensors<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=168\/#AppAdapt_Leveraging_Application_Adaptativity_to_Compensate_Hardware_Variation\" >AppAdapt: Leveraging Application Adaptativity to Compensate Hardware Variation<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=168\/#Variation_Aware_Binning_of_Multi-core_Processors\" >Variation Aware Binning of Multi-core Processors<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=168\/#Publications\" >Publications<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Circuit_Performance_Monitoring\"><\/span>Circuit Performance Monitoring <span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>\nStudents: <a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/www.seas.ucla.edu\/~liangzhe\/\">Liangzhen Lai<\/a> \n<\/p>\n\n\n\n<p>\nCircuit performance monitors are essential for systems with hardware \nand software adaptation to reduce the design margin. This project \naims at developing accurate and inexpensive performance monitoring \nmethodologies. Design-dependent ring oscillator (DDRO) is a replica \nmonitoring methodology, which designs multiple smart canary structures \nthat can reliably predict achievable chip frequency but with margins \nfor local variations. Early silicon results indicate that DDROs can \nreduce delay monitoring error by 35% compared to conventional ring \noscillators. To further improve the prediction (albeit at a higher \noverhead), we propose SlackProbein situ slack monitors which can \nmatch local variations as well at overheads much smaller than \nmonitoring all sequential elements. SlackProbe reduces the number \nof monitors required by over 15X with 5% additional delay margin \nin several commercial processor benchmarks. \n<\/p>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Hardware_Variability-Aware_Duty_Cycling_for_Embedded_Sensors\"><\/span>Hardware Variability-Aware Duty Cycling for Embedded Sensors <span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>\nInstance  and  temperature-dependent  power\nvariation  has  a  direct  impact  on  quality  of  sensing  for\nbattery  powered,  long  running  sensing  applications.  We\nmeasure  and  characterize  active  and  leakage  power  for\nan  ARM  Cortex  M3  processor,  and  show  that  across  a\ntemperature range of 20\u201360\u25e6C there is 10% variation in\nactive power, and 14x variation in leakage power.\nWe  introduce  variability  aware  duty  cycling  methods\nand a duty cycle abstraction for TinyOS that allows ap-\nplications to explicitly specify lifetime and minimum duty\ncycle requirements for individual tasks, and dynamically\nadjusts duty cycle rates so that overall quality of service is\nmaximized in the presence of power variability. We show\nthat variability-aware duty cycling yields a 3\u201322x improve-\nment in total active time over schedules based on worst-\ncase estimations of power, with an average improvement of\n6.4x across a wide variety of deployment scenarios based\non  collected  temperature  traces.  Conversely,  datasheet\npower speci\ufb01cations fail to meet required lifetimes by 7\u2013\n15%, with an average 37 days short of a required lifetime\nof  one  year.  Finally,  we  show  that  a  target  localization\napplication using variability-aware duty cycle yields a 50%\nimprovement in quality of results over one based on worst-\ncase estimations of power consumption.\n<\/p>\n\n\n\n<p> A demo of variability-aware duty-cycling using our own testchip and testbed platform is shown in the following youtube video. Detailed description can be found in the technical report(<a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/www.escholarship.org\/uc\/item\/1c21g217\">link<\/a>). <\/p>\n\n\n\n<figure class=\"wp-block-embed-youtube wp-block-embed is-type-video is-provider-youtube wp-embed-aspect-16-9 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"demorotated\" width=\"843\" height=\"474\" src=\"https:\/\/www.youtube.com\/embed\/-QCqYpaCq14?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; encrypted-media; gyroscope; picture-in-picture\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"AppAdapt_Leveraging_Application_Adaptativity_to_Compensate_Hardware_Variation\"><\/span>AppAdapt: Leveraging Application Adaptativity to Compensate Hardware Variation <span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>\nStudents: <a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/www.ee.ucla.edu\/~apant\/\">Aashish Pant<\/a> \n<\/p>\n\n\n\n<p>\n<em>Objective:<\/em>\nIn this project, we seek to build on the flexible hardware-software \ninterface paradigm by proposing the notion of hardware instance guided \nsoftware adaptation for performance constrained applications. where the \nactual hardware state guides application adaptation on a die specific \nbasis. We show that, by adapting the application to the post \nmanufacturing hardware characteristics (hardware signatures) across \ndifferent die, it is possible to compensate for application quality \nlosses that might otherwise be significant in presence of process \nvariations. This in turn results in improved manufacturing yield, \nrelaxed requirement for hardware over-design and better application \nquality.\n<\/p>\n\n\n\n<p>\nThis work is motivated by the fact that a plethora of modern \napplications are reconfigurable and adaptive, i.e. they are capable of \noperating in various configurations by adapting to certain input or \nenvironmental conditions in turn producing similar or different quality \nof service. Moreover, process variation is increasing and hence, the \nconventional methods of incorporating variation-resistant design \ntechniques, post manufacturing hardware tuning or hardware over-design \nhave become too expensive to use for practical reasons. We observe that \nit is easier and cheaper to implement adaptation at the software layer \nas compared to designing a robust and dependable hardware in the \npresence of manufacturing variations. Moreover, adaptation is much \nbetter informed of the die-specific variation scenario at the \napplication software layer.\n<\/p>\n\n\n\n<p>\nPlease see the videos below for a comparison of hardware adaptive vs \nnon-adaptive encoder. Use the player provided with a frame resolution of\n 352&#215;288 (CIF).\n<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li> <a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Codesign\/vidview.exe\">vidview.exe<\/a>: VidView Player to play the raw .yuv video files (CIF 352&#215;288 frame format)\n<\/li><\/ul>\n\n\n\n<ul class=\"wp-block-list\"><li> <a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Codesign\/orig.yuv\">orig.yuv<\/a>: Original Un-Encoded Mobile Video Sequence\n<\/li><\/ul>\n\n\n\n<ul class=\"wp-block-list\"><li> <a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Codesign\/output_29_m15.yuv\">output_29_m15.yuv<\/a>: Encoded Video on 20% over-designed hardware which is slower by 15%\n<\/li><\/ul>\n\n\n\n<ul class=\"wp-block-list\"><li> <a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Codesign\/output_59_m10.yuv\">output_59_m10.yuv<\/a>: Encoded Video on 20% over-designed hardware which is slower by 10%\n<\/li><\/ul>\n\n\n\n<ul class=\"wp-block-list\"><li> <a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Codesign\/output_85_m5.enc\">output_85_m5.enc<\/a>: Encoded Video on 20% over-designed hardware which is slower by 5%\n<\/li><\/ul>\n\n\n\n<ul class=\"wp-block-list\"><li> <a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Codesign\/output_87_0.yuv\">output_87_0.yuv<\/a>: Encoded Video on 20% over-designed hardware which is slower by 0%\n<\/li><\/ul>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Variation_Aware_Binning_of_Multi-core_Processors\"><\/span>Variation Aware Binning of Multi-core Processors <span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>\nStudents: <a href=\"https:\/\/web.archive.org\/web\/20171110103345\/http:\/\/www.ee.ucla.edu\/~apant\/\">Aashish Pant<\/a> \n<\/p>\n\n\n\n<p><em>Objective:<\/em> Number of cores per multi-core processor die, as well as variation  between the maximum operating frequency of individual cores, is rapidly  increasing. This makes performance binning of multi-core processors a  non-trivial task. In this paper, we study, for the \u0002first time,  multi-core binning metrics and strategies to evaluate them efficiently.  In this project, our major focus is to leverage information obtained  from a process variation model to evaluate the binning metrics more  efficiently and accurately. <\/p>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Publications\"><\/span>Publications<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           V. Dokania, &#8220;Intrusive routing for improved standard cell pin access,&#8221; Department of Electrical Engineering, University of California Los Angeles 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_30\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_30_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR12,\nauthor = {Dokania, Vishesh },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR12_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR12_slides.pdf},\ntitle = {Intrusive Routing for Improved Standard Cell Pin Access},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Pal, &#8220;Supervia: relieving routing congestion using double-height vias,&#8221; Department of Electrical Engineering, University of California Los Angeles 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_31\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_31_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR13,\nauthor = {Pal, Saptadeep},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR13_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR13_slides.pdf},\ntitle = {Supervia: Relieving Routing Congestion using Double-height Vias},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c90.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Lai and P. Gupta, &#8220;Hardware Reliability Margining for the Dark Silicon Era,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2016. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_12\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_12_block\"><pre><code class=\"tex bibtex\">@inproceedings{C90,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {hsi},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C90_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C90_slides.pptx},\ntitle = {{H}ardware {R}eliability {M}argining for the {D}ark {S}ilicon {E}ra},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           N. Lyu, &#8220;Leon3 processor variability emulator for delay variability impact on performance,&#8221; Department of Electrical Engineering, University of California Los Angeles 2016. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_29\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_29_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR11,\nauthor = {Lyu, Nan},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR11_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR11_slides.pdf},\ntitle = {Leon3 Processor Variability Emulator for Delay Variability Impact on Performance},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           M. Gottscho, C. Schoeny, L. Dolecek, and P. Gupta, &#8220;Software-Defined Error-Correcting Codes,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2016. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_42\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_42_block\"><pre><code class=\"tex bibtex\">@conference{W13,\nauthor = {Gottscho, Mark and Schoeny, Clayton and Dolecek, Lara and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {memres,hsi,ecc,memory,reliability,architecture,coding,systems,dram,caches},\nnote = {Best Paper Award},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W13_slides.pptx},\ntitle = {{Software-Defined Error-Correcting Codes}},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c88.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Lai, V. Chandra, and P. Gupta, &#8220;Evaluating and Exploiting Impacts of Dynamic Power Management Schemes on System Reliability,&#8221; in <span style=\"font-style: italic\">ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)<\/span>,  2015. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_11\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_11_block\"><pre><code class=\"tex bibtex\">@inproceedings{C88,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Gupta, Puneet},\nbooktitle = {{ACM\/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)}},\nkeywords = {hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C88_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C88_slides.pdf},\ntitle = {{E}valuating and {E}xploiting {I}mpacts of {D}ynamic {P}ower {M}anagement {S}chemes on {S}ystem {R}eliability},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Lai, &#8220;Cross-layer approaches for monitoring, margining and mitigation of circuit variability,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2015. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_36\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_36_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH5,\nauthor = {Lai, Liangzhen},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH5_paper.pdf},\ntitle = {Cross-Layer Approaches for Monitoring, Margining and Mitigation of Circuit Variability},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Wang, H. Hu, H. Zheng, and P. Gupta, &#8220;MEMRES: A Fast Memory System Reliability Simulator,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Silicon Errors in Logic &#8211; System Effects (SELSE)<\/span>,  2015. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_41\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_41_block\"><pre><code class=\"tex bibtex\">@conference{W12,\nauthor = {Wang, Shaodi and Hu, Henry and Zheng, Hongzhong and Gupta, Puneet},\nbooktitle = {{IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)}},\nkeywords = {hsi, MEMRES, memory faults},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W12_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W12_slides.pptx},\ntitle = {{MEMRES: A Fast Memory System Reliability Simulator}},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j34.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Lai, V. Chandra, R. Aitken, and P. Gupta, &#8220;SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, vol. 33, iss. 8, pp. 1168-1179, 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_27\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_27_block\"><pre><code class=\"tex bibtex\">@article{J34,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {hsi},\nmonth = {Aug},\nnumber = {8},\npages = {1168-1179},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J34_paper.pdf},\ntitle = {{S}lack{P}robe: {A} {F}lexible and {E}fficient {I}n {S}itu {T}iming {S}lack {M}onitoring {M}ethodology},\nvolume = {33},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j32.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Lai, V. Chandra, R. Aitken, and P. Gupta, &#8220;BTI-Gater: An Aging-Resilient Clock Gating Methodology,&#8221; <span style=\"font-style: italic\">IEEE Journal on Emerging and Selected Topics in Circuits and Systems<\/span>, vol. 4, iss. 2, pp. 180-189, 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_26\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_26_block\"><pre><code class=\"tex bibtex\">@article{J32,\nauthor = {Lai, Liangzhen and Chandra, Vikas and Aitken, Robert and Gupta, Puneet},\njournal = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},\nkeywords = {hsi, NBTI},\nmonth = {June},\nnumber = {2},\npages = {180-189},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J32_paper.pdf},\ntitle = {{B}{T}{I}-{G}ater: {A}n {A}ging-{R}esilient {C}lock {G}ating {M}ethodology},\nvolume = {4},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Lai and P. Gupta, &#8220;Accurate and inexpensive performance monitoring for variability-aware systems,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014, pp. 467-473. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_15\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_15_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP13,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {hsi},\nmonth = {Jan},\npages = {467-473},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP13_paper.pdf},\ntitle = {Accurate and inexpensive performance monitoring for variability-aware systems},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           M. Gottscho, &#8220;ViPZonE: Exploiting DRAM Power Variability for Energy Savings in Linux x86-64,&#8221; Department of Electrical Engineering, University of California Los Angeles 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_28\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_28_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR10,\nauthor = {Gottscho, Mark},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR10_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR10_slides.pdf},\ntitle = {{V}i{P}{Z}on{E}: {E}xploiting {DRAM} {P}ower {V}ariability for {E}nergy {S}avings in {L}inux x86-64},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. Bhatia, &#8220;Varleon: fpga based processor variability emulator for variation aware software,&#8221; Department of Electrical Engineering, University of California Los Angeles 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_35\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_35_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR9,\nauthor = {Bhatia, Abishek},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR9_paper.pdf},\ntitle = {VarLEON: FPGA Based Processor Variability Emulator for Variation Aware Software},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [14]                   Y. Agarwal, A. Bishop, T. Chan, M. Fotjik, P. Gupta, A. Kahng, L. Lai, P. Martin, M. Srivastava, D. Sylvester, L. Wanner, and B. Zhang, &#8220;Redcooper: hardware sensor enabled variability software testbed for lifetime energy constrained application,&#8221;  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_37\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_37_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP1,\nauthor = {Agarwal, Yuvraj and Bishop, Alex and Chan, Tuck-Boon and Fotjik, Matt and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen and Martin, Paul and Srivastava, Mani and Sylvester, Dennis and Wanner, Lucas and Zhang, Bing},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/1c21g217},\ntitle = {Redcooper: Hardware sensor enabled variability software testbed for lifetime energy constrained application},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [15]                   L. Lai, C. Chang, and P. Gupta, &#8220;Exploring total power saving from high temperature of server operations,&#8221;  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_38\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_38_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP2,\nauthor = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/5898p020},\ntitle = {Exploring Total Power Saving from High Temperature of Server Operations},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [16]                   L. Lai and P. Gupta, &#8220;A case study of logic delay fault behaviors on general-purpose embedded processor under voltage overscaling,&#8221;  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_39\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_39_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP3,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/3967v8hw},\ntitle = {A Case Study of Logic Delay Fault Behaviors on General-Purpose Embedded Processor Under Voltage Overscaling},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [17]                   L. Lai, C. Chang, and P. Gupta, &#8220;Exploring total power saving from high temperature of server operations,&#8221; , 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_40\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_40_block\"><pre><code class=\"tex bibtex\">@article{TR1,\nauthor = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},\nkeywords = {hsi},\npaperurl = {http:\/\/escholarship.org\/uc\/item\/5898p020},\ntitle = {Exploring Total Power Saving from High Temperature of Server Operations},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c70.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Wanner, S. Elmalaki, L. Lai, P. Gupta, and M. Srivastava, &#8220;VarEMU: An Emulation Testbed for Variability-Aware Software,&#8221; in <span style=\"font-style: italic\">ACM International Conference on Hardware\/Software Codesign and System Synthesis<\/span>,  2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_9\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_9_block\"><pre><code class=\"tex bibtex\">@inproceedings{C70,\nauthor = {Wanner, Lucas and Elmalaki, Salma and Lai, Liangzhen and Gupta, Puneet and Srivastava, Mani},\nbooktitle = {{ACM International Conference on Hardware\/Software Codesign and System Synthesis}},\ncategory = {C70},\nkeywords = {hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C70_paper.pdf},\ntitle = {{V}ar{E}{M}{U}: {A}n {E}mulation {T}estbed for {V}ariability-{A}ware {S}oftware},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c71.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           M. Namaki-Shoushtari, A. Rahimi, N. Dutt, P. Gupta, and R. K. Gupta, &#8220;ARGO: Aging-aware GPGPU register file allocation,&#8221; in <span style=\"font-style: italic\">ACM International Conference on Hardware\/Software Codesign and System Synthesis<\/span>,  2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_10\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_10_block\"><pre><code class=\"tex bibtex\">@inproceedings{C71,\nauthor = {Namaki-Shoushtari, Majid and Rahimi, Abbas and Dutt, Nikil and Gupta, Puneet and Gupta, Rajesh K.},\nbooktitle = {{ACM International Conference on Hardware\/Software Codesign and System Synthesis}},\nkeywords = {hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C71_paper.pdf},\ntitle = {{A}{R}{G}{O}: {A}ging-aware {G}{P}{G}{P}{U} Register File Allocation},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [20]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           N. Dutt, P. Gupta, A. Nicolau, L. Bathen, and M. Gottscho, &#8220;Variability-Aware Memory Management for Nanoscale Computing,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_13\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_13_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP10,\nauthor = {Dutt, Nikil and Gupta, Puneet and Nicolau, Alex and Bathen, Luis and Gottscho, Mark},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {hsi, variability, memory, dram, uno},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP10_paper.pdf},\ntitle = {{V}ariability-{A}ware {M}emory {M}anagement for {N}anoscale {C}omputing},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [21]                   J. Henkel, L. Bauer, N. Dutt, P. Gupta, S. Nassif, M. Shafique, M. Tahoori, and N. Wehn, &#8220;Reliable on-chip systems in the nano-era: lessons learnt and future trends,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2013, p. 99:1\u201399:10. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_14\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_14_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP12,\nauthor = {Henkel, J\\\"{o}rg and Bauer, Lars and Dutt, Nikil and Gupta, Puneet and Nassif, Sani and Shafique, Muhammad and Tahoori, Mehdi and Wehn, Norbert},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {hsi},\npages = {99:1--99:10},\ntitle = {Reliable on-chip systems in the nano-era: lessons learnt and future trends},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [22]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j31.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. Chan, P. Gupta, A. B. Kahng, and L. Lai, &#8220;Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_25\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_25_block\"><pre><code class=\"tex bibtex\">@article{J31,\nauthor = {Chan, Tuck-Boon and Gupta, Puneet and Kahng, A. B. and Lai, Liangzhen},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi, DDRO},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J31_paper.pdf},\ntitle = {{S}ynthesis and {A}nalysis of {D}esign-{D}ependent {R}ing {O}scillator ({D}{D}{R}{O}) {P}erformance {M}onitors},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [23]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c65.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Bathen, M. Gottscho, N. Dutt, P. Gupta, and A. Nicolau, &#8220;ViPZonE: OS-Level Memory Variability-Aware Physical Address Zoning for Energy Savings,&#8221; in <span style=\"font-style: italic\">ACM International Conference on Hardware\/Software Codesign and System Synthesis<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_8\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_8_block\"><pre><code class=\"tex bibtex\">@inproceedings{C65,\nauthor = {Bathen, Luis and Gottscho, Mark and Dutt, Nikil and Gupta, Puneet and Nicolau, Alex},\nbooktitle = {{ACM International Conference on Hardware\/Software Codesign and System Synthesis}},\ncategory = {C65},\nkeywords = {hsi, vipzone, os, variability, variability-aware, dram, memory, power, zone, zoning, allocation},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C65_paper.pdf},\ntitle = {{V}i{P}{Z}on{E}: {O}{S}-{L}evel {M}emory {V}ariability-{A}ware {P}hysical {A}ddress {Z}oning for {E}nergy {S}avings},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [24]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c60.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. B. Chan, P. Gupta, A. Kahng, and L. Lai, &#8220;DDRO: a Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,&#8221; in <span style=\"font-style: italic\">ISQED<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_6\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_6_block\"><pre><code class=\"tex bibtex\">@inproceedings{C60,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen},\nbooktitle = {{ISQED}},\ncategory = {C60},\nkeywords = {hsi, DDRO},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C60_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C60_slides.pdf},\ntitle = {{DDRO}: A {N}ovel {P}erformance {M}onitoring {M}ethodology {B}ased on {D}esign-{D}ependent {R}ing {O}scillators},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [25]                   L. A. D. Bathen, N. D. Dutt, A. Nicolau, and P. Gupta, &#8220;Vamv: variability-aware memory virtualization,&#8221; in <span style=\"font-style: italic\">DATE<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_7\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_7_block\"><pre><code class=\"tex bibtex\">@inproceedings{C61,\nauthor = {L.A.D. Bathen and N.D. Dutt and A. Nicolau and P. Gupta},\nbooktitle = {{DATE}},\nkeywords = {hsi},\nmonth = {March},\nnote = {Best interactive presentation},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/BathenDNG12.pdf},\ntitle = {VaMV: Variability-aware Memory Virtualization},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [26]                   P. Gupta, &#8220;Measuring and monitoring variability,&#8221; in <span style=\"font-style: italic\">IEEE International On-Line Test Symposium<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_19\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_19_block\"><pre><code class=\"tex bibtex\">@conference{ITT16,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International On-Line Test Symposium}},\nkeywords = {hsi},\nnote = {Invited Talk},\ntitle = { Measuring and Monitoring Variability},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [27]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j20.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           M. Gottscho, A. A. Kagalwalla, and P. Gupta, &#8220;Power Variability in Contemporary DRAMs,&#8221; <span style=\"font-style: italic\">IEEE Embedded Systems Letters<\/span>, vol. 4, p. 37\u201340, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_22\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_22_block\"><pre><code class=\"tex bibtex\">@article{J20,\nauthor = {Gottscho, Mark and Kagalwalla, Abde Ali and Gupta, Puneet},\nissue = {2},\njournal = {{IEEE Embedded Systems Letters}},\nkeywords = {DRAM, DDR3, power, variability, hsi},\npages = {37--40},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J20_paper.pdf},\ntitle = {{P}ower {V}ariability in {C}ontemporary {DRAM}s},\nvolume = {4},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [28]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j23.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, &#8220;Hardware Variability-Aware Duty Cycling for Embedded Sensors,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_23\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_23_block\"><pre><code class=\"tex bibtex\">@article{J23,\nauthor = {Lucas Wanner and Charwak Apte and Rahul Balani and Puneet Gupta and Mani Srivastava},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/j23.pdf},\ntitle = {{H}ardware {V}ariability-{A}ware {D}uty {C}ycling for {E}mbedded {S}ensors},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [29]                   P. Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. N. T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester, &#8220;Underdesigned and opportunistic computing in presence of hardware variability,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_24\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_24_block\"><pre><code class=\"tex bibtex\">@article{J26,\nauthor = {Puneet Gupta and Yuvraj Agarwal and Lara Dolecek and Nikil Dutt and Rajesh K. Gupta and Rakesh Kumar and Subhasish Mitra and Alexandru Nicolauand Tajana Simunic Rosing and Mani B. Srivastava and Steven Swanson and Dennis Sylvester},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {hsi},\nnote = {Keynote Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/UnO_keynote.pdf},\ntitle = {Underdesigned and Opportunistic Computing in Presence of Hardware Variability},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [30]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Dong, &#8220;High Level Battery Modeling Considering Discharge Rate and Temperature Effects,&#8221; Department of Electrical Engineering, University of California Los Angeles 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_34\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_34_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR7,\nauthor = {Dong, Jingyuan},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR7_paper.pdf},\ntitle = {{High Level Battery Modeling Considering Discharge Rate and Temperature Effects}},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [31]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c55.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. -B. Chan, J. Sartori, P. Gupta, and R. Kumar, &#8220;On the Efficacy of NBTI Mitigation Techniques,&#8221; in <span style=\"font-style: italic\">Design, Automation, and Test in Europe (DATE)<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_3\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_3_block\"><pre><code class=\"tex bibtex\">@inproceedings{C55,\nauthor = {Chan, T.-B. and Sartori, John and Gupta, Puneet and Kumar, Rakesh},\nbooktitle = {{Design, Automation, and Test in Europe (DATE)}},\ncategory = {C55},\nkeywords = {variabilty-aware, embedded sensing, hsi, ucla_rdmode},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C55_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C55_slides.pdf},\ntitle = {{O}n the {E}fficacy of {NBTI} {M}itigation {T}echniques},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [32]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c56.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Wanner, R. Balani, S. Zahedi, C. Apte, P. Gupta, and M. Srivastava, &#8220;Variability Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems,&#8221; in <span style=\"font-style: italic\">Design, Automation, and Test in Europe (DATE)<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_4\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_4_block\"><pre><code class=\"tex bibtex\">@inproceedings{C56,\nauthor = {Wanner, Lucas and Balani, Rahul and Zahedi, Sadaf and Apte, Charwak and Gupta, Puneet and Srivastava, Mani },\nbooktitle = {{Design, Automation, and Test in Europe (DATE)}},\ncategory = {C56},\nkeywords = {variabilty-aware, embedded sensing, hsi},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C56_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C56_slides.pdf},\ntitle = {{V}ariability {A}ware {D}uty {C}ycle {S}cheduling in {L}ong {R}unning {E}mbedded {S}ensing {S}ystems},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [33]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c54.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Kulkarni, P. Gupta, and M. Ercegovac, &#8220;Trading Accuracy for Power with an Underdesigned Multiplier Architecture,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_2\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_2_block\"><pre><code class=\"tex bibtex\">@inproceedings{C54,\nauthor = {Kulkarni, Parag and Gupta, Puneet and Ercegovac, Milos},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C54},\nkeywords = {low power, hsi},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C54_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C54_slides.pdf},\ntitle = {{T}rading {A}ccuracy for {P}ower with an {U}nderdesigned {M}ultiplier {A}rchitecture},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [34]                   P. Gupta and R. Gupta, &#8220;Underdesigned and opportunistic computing,&#8221; in <span style=\"font-style: italic\">Proc. Asian Test Symposium<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_16\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_16_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP8,\nauthor = {P. Gupta and R. Gupta},\nbooktitle = {{Proc. Asian Test Symposium}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/uno_ats_v4.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/ats_11_v1.pdf},\ntitle = {Underdesigned and Opportunistic Computing},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [35]                   P. Gupta, &#8220;Underdesigned and opportunistic computing machines,&#8221; in <span style=\"font-style: italic\">Nanosystem Design and Variability Workshop, EPFL<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_17\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_17_block\"><pre><code class=\"tex bibtex\">@conference{ITT12,\nauthor = {Gupta, P.},\nbooktitle = {{Nanosystem Design and Variability Workshop, EPFL}},\nkeywords = {hsi},\nnote = {Invited Talk},\ntitle = {Underdesigned and Opportunistic Computing Machines},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [36]                   P. Gupta, &#8220;Designing for uncertainty: addressing process variations and aging issues in vlsi designs,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on VLSI Design, Automation and Test<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_18\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_18_block\"><pre><code class=\"tex bibtex\">@conference{ITT13,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International Symposium on VLSI Design, Automation and Test}},\nkeywords = {mad, hsi},\nnote = {Tutorial},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/vlsidat_11.pdf},\ntitle = {Designing for Uncertainty: Addressing Process Variations and Aging Issues in VLSI Designs},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [37]                   P. Kulkarni, P. Gupta, and M. D. Ercegovac, &#8220;Trading accuracy for power in a multiplier architecture,&#8221; <span style=\"font-style: italic\">Journal of Low Power Electronics<\/span>, 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_20\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_20_block\"><pre><code class=\"tex bibtex\">@article{J16,\nauthor = {Kulkarni, P. and Gupta, P. and Ercegovac, M.D.},\njournal = {{Journal of Low Power Electronics}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/JOLPE_v3.pdf},\ntitle = {Trading Accuracy for Power in a Multiplier Architecture},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [38]                   A. Pant, P. Gupta, and M. van der Schaar, &#8220;Appadapt: opportunistic application adaptation in presence of hardware variation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Very Large Scale Integration Systems<\/span>, 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_21\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_21_block\"><pre><code class=\"tex bibtex\">@article{J17,\nauthor = {Aashish Pant and Gupta, Puneet and Mihaela van der Schaar},\njournal = {{IEEE Transactions on Very Large Scale Integration Systems}},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/VarAwareAdapt.pdf},\ntitle = {AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [39]                   C. Apte, &#8220;Power Consumption Variability in Embedded Processors,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_32\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_32_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR5,\nauthor = {Apte, Charwak},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR5_paper.pdf},\ntitle = {{Power Consumption Variability in Embedded\nProcessors}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [40]                   P. Kulkarni, &#8220;Trading Accuracy for Power with an Under-designed Multiplier Architecture,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_33\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_33_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR6,\nauthor = {Kulkarni, Parag },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR6_paper.pdf},\ntitle = {{Trading Accuracy for Power with an Under-designed\nMultiplier Architecture}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [41]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c58.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, &#8220;A Case for Opportunistic Embedded Sensing In Presence of Hardware Power Varibility,&#8221; in <span style=\"font-style: italic\">HotPower&#8217;10<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_5\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_5_block\"><pre><code class=\"tex bibtex\">@conference{C58,\nauthor = {Wanner, Lucas and Apte, Charwak and Balani, Rahul and Gupta, Puneet and Srivastava, Mani},\nbooktitle = {{HotPower'10}},\ncategory = {C58},\nkeywords = {embedded sensing, leakage power, duty cycling, hsi},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C58_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C58_slides.pdf},\ntitle = {{A} {C}ase for {O}pportunistic {E}mbedded {S}ensing {I}n {P}resence of {H}ardware {P}ower {V}aribility},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [42]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c49.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. Pant, P. Gupta, and M. van der Schaar, &#8220;Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability,&#8221; in <span style=\"font-style: italic\">ACM Great Lakes Symposium on Very Large Scale Integration<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_1\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_1_block\"><pre><code class=\"tex bibtex\">@inproceedings{C49,\nauthor = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},\nbooktitle = {{ACM Great Lakes Symposium on Very Large Scale Integration}},\ncategory = {C49},\nkeywords = {hsi},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C49_paper.pdf},\ntitle = {{S}oftware {A}daptation in {Q}uality {S}ensitive {A}pplications to {D}eal with {H}ardware {V}ariability},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [43]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c48.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Sartori, A. Pant, R. Kumar, and P. Gupta, &#8220;Variation Aware Speed Binning of Multi-core Processors,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_0\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_0_block\"><pre><code class=\"tex bibtex\">@inproceedings{C48,\nauthor = {Sartori, John and Pant, Aashish and Kumar, Rakesh and Gupta, Puneet},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\ncategory = {C48},\nkeywords = {hsi},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C48_paper.pdf},\ntitle = {{V}ariation {A}ware {S}peed {B}inning of {M}ulti-core {P}rocessors},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [44]                   A. Pant, P. Gupta, and M. van der Schaar, &#8220;Software Adaptation to Handle Manufacturing Variability and Relax Hardware Overdesign,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_43\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_43_block\"><pre><code class=\"tex bibtex\">@conference{W2,\nauthor = {Pant, Aashish and Gupta, Puneet and Schaar, Mihaela van der},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W2},\nkeywords = {hsi-p1},\ntitle = {{S}oftware {A}daptation to {H}andle {M}anufacturing {Variability} and {R}elax {H}ardware {O}verdesign},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [45]                   J. Sartori, A. Pant, P. Gupta, and R. Kumar, &#8220;On Performance Binning of Multicore Processors,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_44\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_44_block\"><pre><code class=\"tex bibtex\">@conference{W3,\nauthor = {Sartori, John and Pant, Aashish and Gupta, Puneet and Kumar, Rakesh},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W3},\nkeywords = {hsi-p2},\ntitle = {{O}n {P}erformance {B}inning of {M}ulticore {P}rocessors},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>   <\/p>\n","protected":false},"excerpt":{"rendered":"<p>While a well-de\ufb01ned \ufb01rm hardware-software in- terface enabled advances in software and hardware design methods, it is increasingly harder to sustain as the newer semiconductor&hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":160,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-168","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/168","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=168"}],"version-history":[{"count":3,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/168\/revisions"}],"predecessor-version":[{"id":249,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/168\/revisions\/249"}],"up":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/160"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=168"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}