{"id":166,"date":"2019-10-02T21:07:43","date_gmt":"2019-10-02T21:07:43","guid":{"rendered":"http:\/\/nanocad.ee.ucla.edu\/?page_id=166"},"modified":"2019-10-07T21:52:11","modified_gmt":"2019-10-07T21:52:11","slug":"manufacturing-aware-design","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=166","title":{"rendered":"Manufacturing-Aware Design"},"content":{"rendered":"\n<p> For design for manufacturing (DFM) models and methods to be&nbsp; defensible &nbsp;and &nbsp;adoptable, &nbsp;they &nbsp;have &nbsp;to &nbsp;be &nbsp;as &nbsp;simple &nbsp;as  &nbsp;possible &nbsp;without &nbsp;losing &nbsp;physical &nbsp;justification. &nbsp;Our &nbsp;ongoing&nbsp; research &nbsp;is &nbsp;re-evaluating &nbsp;several &nbsp;assumptions &nbsp;that &nbsp;CAD &nbsp;research  &nbsp;has &nbsp;made &nbsp;in &nbsp;recent &nbsp;years &nbsp;to &nbsp;avoid &nbsp;&#8220;DFM &nbsp;overkill&#8221;.&nbsp; Starting   from  a  deep  understanding  of    the  makeup  of  different  physical   phenomena that lead to the observed electrical variability, we  have  developed variability models and methods in physical design to deal with  patterning constraints.  <\/p>\n\n\n\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=166\/#Physically_Justifiable_Die-Level_Modeling_of_Spatial_Variation_in_View_of_Systematic_Across-Wafer_Variability\" >Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across-Wafer Variability<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=166\/#Publications\" >Publications<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Physically_Justifiable_Die-Level_Modeling_of_Spatial_Variation_in_View_of_Systematic_Across-Wafer_Variability\"><\/span>Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across-Wafer Variability <span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><em>Objective:<\/em> Modeling spatial variation is important for statistical analysis. In  practice, all of which indicate that spatial variation comes from  deterministic across-wafer variation, and purely random spatial  variation is not significant. We analytically study the impact of  across-wafer variation and show how it gives an appearance of  correlation. We have developed a new die-level variation model considering  deterministic across-wafer variation and derived the range of conditions  under which ignoring spatial variation altogether may be acceptable. <\/p>\n\n\n\n<p>\n<em>Package:<\/em>\nSpatial_detect is a Matlab script to extract across-wafer variation from\n measurement data. It assumes the across wafer variation to be a \nquadratic function. In this detection, we have two different spatial \nvariation models: 1) Random field based spatial variation model [1, 2]; \n2) Modeling across-wafer variation [3]. In practice, modeling \nacross-wafer variation is more accurate and efficient than the random \nfield based spatial variation model. The current release includes source\n code, user manual, and sample input files.\n<\/p>\n\n\n\n<p> By: <a href=\"https:\/\/web.archive.org\/web\/20171028203942\/http:\/\/www.ee.ucla.edu\/~lerong\/\">Lerong Cheng<\/a>, advised by <a href=\"https:\/\/web.archive.org\/web\/20171028203942\/http:\/\/www.ee.ucla.edu\/~puneet\/\">Prof. Puneet Gupta<\/a> <\/p>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Publications\"><\/span>Publications<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>   <ul class=\"papercite_bibliography\">          [1]                   R. Puri, N. Charudhattan, S. Saha, S. Rangarajan, R. Rao, and P. Gupta, &#8220;Design of deep sub-micron cmos circuit and design methodologies for high performance microprocessors,&#8221; in <span style=\"font-style: italic\"> IEEE International Conference on VLSI Design<\/span>,  2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_37\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_37_block\"><pre><code class=\"tex bibtex\">@conference{ITT17,\nauthor = {R. Puri and N. Charudhattan and S. Saha and S. Rangarajan and R. Rao and P. Gupta},\nbooktitle = {{ IEEE International Conference on VLSI Design}},\nkeywords = {mad},\nnote = {Tutorial},\ntitle = {Design of Deep Sub-Micron CMOS Circuit and Design Methodologies for High Performance Microprocessors},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [2]                   P. Gupta, &#8220;Design-assisted semiconductor manufacturing,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_36\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_36_block\"><pre><code class=\"tex bibtex\">@conference{ITT15,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\nkeywords = {mad},\nnote = {Short tutorial},\ntitle = {Design-Assisted Semiconductor Manufacturing},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           N. Jin, &#8220;Modelling of guardband reduction on design area,&#8221; Department of Electrical Engineering, University of California Los Angeles 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_53\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_53_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR8,\nauthor = {Jin, Ning},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {mad, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR8_paper.pdf},\ntitle = {Modelling of Guardband Reduction on Design Area},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [4]                   A. R. Neureuther, J. Rubinstein, M. Miller, Y. K. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T. -J. K. Liu, X. Sun, K. Jeong, P. and Gupta, A. A. Kagalwalla, R. S. Ghaida, and T. -B. Chan, &#8220;Collaborative research on emerging technologies and design,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Photomask and Next-Generation Lithography Mask Technology<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_30\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_30_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP7,\nauthor = {A.R. Neureuther and J. Rubinstein and M. Miller and K. Yamazoeand E. Chin and C. Levy and L. Wang and N. Xu and C. Spanos and K. Qian and K. Poolla and J. Ghan and A. Subramanian and T.-J. K. Liu and X. Sun and K. Jeong and and P. Gupta and Kagalwalla, Abde Ali and Ghaida, R. S. and T.-B. Chan},\nbooktitle = {{Proc. SPIE Photomask and Next-Generation Lithography Mask Technology}},\ncategory = {IP7},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/pmj11.pdf},\ntitle = {Collaborative research on emerging technologies and design},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [5]                   P. Gupta, &#8220;Designing for uncertainty: addressing process variations and aging issues in vlsi designs,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on VLSI Design, Automation and Test<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_34\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_34_block\"><pre><code class=\"tex bibtex\">@conference{ITT13,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International Symposium on VLSI Design, Automation and Test}},\nkeywords = {mad, hsi},\nnote = {Tutorial},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/vlsidat_11.pdf},\ntitle = {Designing for Uncertainty: Addressing Process Variations and Aging Issues in VLSI Designs},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [6]                   P. Gupta, &#8220;Variability and reliability: will they get better or worse in future cmos technologies ?,&#8221; in <span style=\"font-style: italic\">IEEE Workshop on Design for Reliability and Variability<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_35\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_35_block\"><pre><code class=\"tex bibtex\">@conference{ITT14,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE Workshop on Design for Reliability and Variability}},\nkeywords = {mad},\nnote = {Panel Discussion},\ntitle = { Variability and Reliability: Will they Get Better or Worse in Future CMOS Technologies ?},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Cong, P. Gupta, and J. Lee, &#8220;Evaluating Statistical Power Optimization,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, vol. 29, iss. 11, p. 1750\u20131762, 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_46\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_46_block\"><pre><code class=\"tex bibtex\">@article{J12,\nauthor = {Cong, J. and Gupta, P. and Lee, John},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {sizing, mad},\nmonth = {Nov},\nnumber = {11},\npages = {1750--1762},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J12_paper.pdf},\ntitle = {{Evaluating Statistical Power Optimization}},\nvolume = {29},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c51.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Lee and P. Gupta, &#8220;Incremental Gate Sizing for Late Process Changes,&#8221; in <span style=\"font-style: italic\">Proc. IEEE International Conference on Computer Design<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_25\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_25_block\"><pre><code class=\"tex bibtex\">@inproceedings{C51,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{Proc. IEEE International Conference on Computer Design}},\ncategory = {C51},\nkeywords = {sizing, mad},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C51_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C51_slides.pdf},\ntitle = {{I}ncremental {G}ate {S}izing for {L}ate {P}rocess {C}hanges},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c45.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. -B. Chan and P. Gupta, &#8220;On Electrical Modeling of Imperfect Diffusion Patterning,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_23\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_23_block\"><pre><code class=\"tex bibtex\">@inproceedings{C45,\nauthor = {Chan, T.-B. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C45},\nkeywords = {dats, mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C45_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C45_slides.pdf},\ntitle = {On {E}lectrical {M}odeling of {I}mperfect {D}iffusion {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c47.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Cheng, P. Gupta, and L. He, &#8220;On Confidence in Characterization and Application of Variation Models,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_24\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_24_block\"><pre><code class=\"tex bibtex\">@inproceedings{C47,\nauthor = {Cheng, L. and Gupta, P. and He, L.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C47},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C47_paper.pdf},\ntitle = {On {C}onfidence in {C}haracterization and {A}pplication of {V}ariation {M}odels},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. -B. Chan, R. S. Ghaida, and P. Gupta, &#8220;Electrical Modeling of Lithographic Imperfections,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_29\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_29_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP6,\nauthor = {Chan, T.-B. and Ghaida, R. S. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {IP6},\nkeywords = {mad},\nnote = {Embedded Tutorial},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP6_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP6_slides.pdf},\ntitle = {{E}lectrical {M}odeling of {L}ithographic {I}mperfections},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [12]                   P. Gupta, &#8220;Modeling performance impact of variability,&#8221; in <span style=\"font-style: italic\">NSF\/SRC The International Variability Characterization Workshop<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_33\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_33_block\"><pre><code class=\"tex bibtex\">@conference{ITT11,\nauthor = {Gupta, P.},\nbooktitle = {{NSF\/SRC The International Variability Characterization Workshop}},\nkeywords = {mad},\nnote = {Invited Talk},\ntitle = {Modeling Performance Impact of Variability},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, &#8220;Electrical Assessment of Lithographic Gate Line-End Patterning,&#8221; <span style=\"font-style: italic\">spieJ<\/span>, 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_45\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_45_block\"><pre><code class=\"tex bibtex\">@article{J11,\nauthor = {Gupta, P. and Jeong, K. and Kahng, A.B. and Park, C.-H.},\njournal = {{spieJ}},\nkeywords = {mad, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J11_paper.pdf},\ntitle = {Electrical {A}ssessment of {L}ithographic {G}ate {L}ine-{E}nd {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Cheng, P. Gupta, C. J. Spanos, K. Qian, and L. He, &#8220;Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_47\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_47_block\"><pre><code class=\"tex bibtex\">@article{J14,\nauthor = {Cheng, L. and Gupta, P. and Spanos, C. J. and Qian, K. and He, L.},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J14_paper.pdf},\ntitle = {{P}hysically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           D. Reinhard, &#8220;On Comparing Conventional and Electrically Driven OPC Techniques,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_52\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_52_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR2,\nauthor = {Reinhard, Dominic},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {mad. msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR2_paper.pdf},\ntitle = {{On Comparing Conventional and Electrically Driven OPC Techniques}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c38.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Cong, P. Gupta, and J. Lee, &#8220;On the Futlity of Statistical Power Optimization,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_20\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_20_block\"><pre><code class=\"tex bibtex\">@inproceedings{C38,\nauthor = {Cong, J. and Gupta, P. and Lee, John},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C38},\nkeywords = {sizing, mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C38_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C38_slides.pdf},\ntitle = {On the {F}utlity of {S}tatistical {P}ower {O}ptimization},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c39.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Cheng, P. Gupta, and L. He, &#8220;Accounting for Non-linear Dependence Using Function Driven Component Analysis,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_21\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_21_block\"><pre><code class=\"tex bibtex\">@inproceedings{C39,\nauthor = {Cheng, L. and Gupta, P. and He, L.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C39},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C39_paper.pdf},\ntitle = {Accounting for {N}on-linear {D}ependence {U}sing {F}unction {D}riven {C}omponent {A}nalysis},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [18]                   L. Cheng, P. Gupta, K. Qian, C. Spanos, and L. He, &#8220;Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_22\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_22_block\"><pre><code class=\"tex bibtex\">@inproceedings{C43,\nauthor = {Cheng, L. and Gupta, P. and Qian, K. and Spanos, C. and He, L.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C43},\nkeywords = {mad},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C43_paper.pdf},\ntitle = {Physically {J}ustifiable {D}ie-{L}evel {M}odeling of {S}patial {V}ariation in {V}iew of {S}ystematic {A}cross {W}afer {V}ariability},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [19]                   P. Gupta, &#8220;Revisiting variation models and their reliability,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Workshop on Variability Modeling and Characterization<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_31\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_31_block\"><pre><code class=\"tex bibtex\">@conference{ITT10,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE\/ACM Workshop on Variability Modeling and Characterization}},\nkeywords = {mad},\nnote = {Invited talk},\ntitle = {Revisiting Variation Models and Their Reliability},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [20]                   P. Gupta, &#8220;Design for ultra-low-k1 patterning and manufacturing,&#8221; in <span style=\"font-style: italic\">IEEE International Conference on Microelectronic Teststructures (ICMTS)<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_32\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_32_block\"><pre><code class=\"tex bibtex\">@conference{ITT10a,\nauthor = {Gupta, P.},\nbooktitle = {{IEEE International Conference on Microelectronic Teststructures (ICMTS)}},\nkeywords = {mad},\nnote = {Tutorial},\ntitle = { Design for Ultra-low-k1 Patterning and Manufacturing},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [21]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Cheng, P. Gupta, and L. He, &#8220;Efficient Additive Statistical Leakage Estimation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_51\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_51_block\"><pre><code class=\"tex bibtex\">@article{J9,\nauthor = {Cheng, L. and Gupta, P. and He, L.},\ncategory = {J9},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J9_paper.pdf},\ntitle = {Efficient {A}dditive {S}tatistical {L}eakage {E}stimation},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [22]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c37.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta and A. B. Kahng, &#8220;Bounded Lifetime Integrated Circuits,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_19\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_19_block\"><pre><code class=\"tex bibtex\">@inproceedings{C37,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C37},\nkeywords = {mad},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C37_paper.pdf},\ntitle = {Bounded {L}ifetime {I}ntegrated {C}ircuits},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [23]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c36.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, &#8220;Electrical Metrics for Lithographic Line-End Tapering,&#8221; in <span style=\"font-style: italic\">SPIE Photomask and NGL Mask Technology<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_18\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_18_block\"><pre><code class=\"tex bibtex\">@inproceedings{C36,\nauthor = {Gupta, P. and Jeong, K. and Kahng, A. B. and Park, C.-H},\nbooktitle = {{SPIE Photomask and NGL Mask Technology}},\ncategory = {C36},\nkeywords = {mad, dats},\nmonth = {April},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C36_paper.pdf},\ntitle = {Electrical {M}etrics for {L}ithographic {L}ine-{E}nd {T}apering},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [24]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c35.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, &#8220;Shaping Gate Channels for Improved Devices,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_17\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_17_block\"><pre><code class=\"tex bibtex\">@inproceedings{C35,\nauthor = {Gupta, P. and Kahng, A. B. and Shah, S. and Sylvester, D.},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\ncategory = {C35},\nkeywords = {dats, mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C35_paper.pdf},\ntitle = {Shaping {G}ate {C}hannels for {I}mproved {D}evices},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [25]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c34.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, &#8220;Investigation of Diffusion Rounding for Post-Lithography Analysis,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_16\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_16_block\"><pre><code class=\"tex bibtex\">@inproceedings{C34,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S. and Sylvester, D.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C34},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C34_paper.pdf},\ntitle = {Investigation of {D}iffusion {R}ounding for {P}ost-{L}ithography {A}nalysis},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [26]                   P. Gupta, &#8220;The Electrical Design Manufacturing Interface,&#8221; in <span style=\"font-style: italic\">Electronic Design Processes Workshop<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_41\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_41_block\"><pre><code class=\"tex bibtex\">@conference{ITT5,\nauthor = {Gupta, P.},\nbooktitle = {{Electronic Design Processes Workshop}},\ncategory = {ITT5},\nkeywords = {mad, dats},\ntitle = {The {E}lectrical {D}esign {M}anufacturing {I}nterface},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [27]                   P. Gupta and C. Wu, &#8220;Lithography and Memories: From Shapes to Electrical,&#8221; in <span style=\"font-style: italic\">IEEE VLSI Test Symposium<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_42\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_42_block\"><pre><code class=\"tex bibtex\">@conference{ITT6,\nauthor = {Gupta, P. and Wu, C.},\nbooktitle = {{IEEE VLSI Test Symposium}},\ncategory = {ITT6},\nkeywords = {mad},\ntitle = {Lithography and {M}emories: {F}rom {S}hapes to {E}lectrical},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [28]                   D. Chidambarrao, P. Gupta, P. Elakkumanan, L. Liebmann, D. Marculescu, and N. Tamarapalli, &#8220;DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_43\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_43_block\"><pre><code class=\"tex bibtex\">@conference{ITT7,\nauthor = {Chidambarrao, D. and Gupta, P. and Elakkumanan, P. and Liebmann, L. and Marculescu, D. and Tamarapalli, N.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {ITT7},\nkeywords = {mad},\nnote = {Full-day Tutorial},\ntitle = {{DFM} {R}evisited: {A} {C}omprehensive {A}nalysis of {V}ariability at all {L}evels of {A}bstraction},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [29]                   P. Gupta, &#8220;Challenges at 45nm and Beyond,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_44\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_44_block\"><pre><code class=\"tex bibtex\">@conference{ITT8,\nauthor = {Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {ITT8},\nkeywords = {mad, dats},\nnote = {Panel Discussion},\ntitle = {Challenges at 45nm and {B}eyond},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [30]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Detailed Placement for Enhanced Control of Resist and Etch CDs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2007. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_50\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_50_block\"><pre><code class=\"tex bibtex\">@article{J7,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H.},\ncategory = {J7},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\nmonth = {December},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J7_paper.pdf},\ntitle = {Detailed {P}lacement for {E}nhanced {C}ontrol of {R}esist and {E}tch {CD}s},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [31]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, &#8220;Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2007. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_49\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_49_block\"><pre><code class=\"tex bibtex\">@article{J6,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},\ncategory = {J6},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {mad},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J6_paper.pdf},\ntitle = {Self-{C}ompensating {D}esign for {R}eduction of {T}iming and {L}eakage {S}ensitivity to {S}ystematic {P}attern {D}ependent {V}ariation},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [32]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c33.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, &#8220;Line End Shortening is not Always a Failure,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2007. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_15\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_15_block\"><pre><code class=\"tex bibtex\">@inproceedings{C33,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C2},\nkeywords = {mad, dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C33_paper.pdf},\ntitle = {Line {E}nd {S}hortening is not {A}lways a {F}ailure},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [33]                   P. Gupta and R. Puri, &#8220;Impact of Variability On VLSI Circuits,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2007. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_40\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_40_block\"><pre><code class=\"tex bibtex\">@conference{ITT4,\nauthor = {Gupta, P. and Puri, R.},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\ncategory = {ITT4},\nkeywords = {mad},\nnote = {Short Course},\ntitle = {Impact Of {V}ariability {O}n {VLSI} {C}ircuits},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [34]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, &#8220;Gate-Length Biasing for Runtime Leakage Control,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2006. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_48\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_48_block\"><pre><code class=\"tex bibtex\">@article{J4,\nauthor = {Gupta, P. and Kahng, A. B. and Sharma, P. and Sylvester, D.},\ncategory = {J4},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {sizing, mad},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J4_paper.pdf},\ntitle = {Gate-{L}ength {B}iasing for {R}untime {L}eakage {C}ontrol},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [35]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c28.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah, and P. Sharma, &#8220;Lithography Simulation-Based Full-Chip Design Analyses,&#8221; in <span style=\"font-style: italic\">SPIE Microlithography<\/span>,  2006. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_10\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_10_block\"><pre><code class=\"tex bibtex\">@inproceedings{C28,\nauthor = {Gupta, P. and Kahng, A. B. and Nakagawa, S. and Shah, S. and Sharma, P.},\nbooktitle = {{SPIE Microlithography}},\ncategory = {C28},\nkeywords = {mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C28_paper.pdf},\ntitle = {Lithography {S}imulation-{B}ased {F}ull-{C}hip {D}esign {A}nalyses},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [36]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c29.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, &#8220;Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis,&#8221; in <span style=\"font-style: italic\">SPIE Microlithography<\/span>,  2006. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_11\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_11_block\"><pre><code class=\"tex bibtex\">@inproceedings{C29,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S. and Sylvester, D.},\nbooktitle = {{SPIE Microlithography}},\ncategory = {C29},\nkeywords = {mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C2999999999_paper.pdf},\ntitle = {Modeling of {N}on-{U}niform {D}evice {G}eometries for {P}ost-{L}ithography {C}ircuit {A}nalysis},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [37]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c31.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, &#8220;Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,&#8221; in <span style=\"font-style: italic\">SPIE Microlithography<\/span>,  2006. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_14\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_14_block\"><pre><code class=\"tex bibtex\">@inproceedings{C31,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},\nbooktitle = {{SPIE Microlithography}},\ncategory = {C31},\nkeywords = {mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C31_paper.pdf},\ntitle = {Self-{C}ompensating {D}esign for {R}eduction of {T}iming and {L}eakage {S}ensitivity to {S}ystematic {P}attern {D}ependent {V}ariation},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [38]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c27.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta and A. B. Kahng, &#8220;Efficient Design and Analysis of Robust Power Distribution Meshes,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2006. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_9\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_9_block\"><pre><code class=\"tex bibtex\">@inproceedings{C27,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C27},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C27_paper.pdf},\ntitle = {Efficient {D}esign and {A}nalysis of {R}obust {P}ower {D}istribution {M}eshes},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [39]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c30.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, S. V. Muddu, and N. S., &#8220;Modeling Edge Placement Error Distribution in Standard Cell Library,&#8221; in <span style=\"font-style: italic\">SPIE Microlithography<\/span>,  2006. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_13\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_13_block\"><pre><code class=\"tex bibtex\">@inproceedings{C30,\nauthor = {Gupta, P. and Kahng, A. B. and Muddu, S.V. and Nakagawa S.},\nbooktitle = {{SPIE Microlithography}},\ncategory = {C30},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C30_paper.pdf},\ntitle = {Modeling {E}dge {P}lacement {E}rror {D}istribution in {S}tandard {C}ell {L}ibrary},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [40]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c24.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Enhanced Resist and Etch CD Control by Design Perturbation,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_8\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_8_block\"><pre><code class=\"tex bibtex\">@inproceedings{C24,\nauthor = {Gupta, P. and Kahng, A. B. and C.-H. Park},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\ncategory = {C24},\nkeywords = {mad},\nmonth = {October},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C24_paper.pdf},\ntitle = {Enhanced {R}esist and {E}tch {CD} {C}ontrol by {D}esign {P}erturbation},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [41]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, O. S. Nakagawa, and K. Samadi, &#8220;Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing,&#8221; in <span style=\"font-style: italic\">Proc. 22nd Intl. VLSI\/ULSI Multilevel Interconnection (VMIC) Conf.<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_28\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_28_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP4,\nauthor = {Gupta, P. and Kahng, A. B. and Nakagawa, O.S. and Samadi, K.},\nbooktitle = {{Proc. 22nd Intl. VLSI\/ULSI Multilevel Interconnection (VMIC) Conf.}},\ncategory = {IP4},\nkeywords = {mad},\nmonth = {October},\nnote = {Invited Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP4_paper.pdf},\ntitle = {Closing the {L}oop in {I}nterconnect {A}nalyses and {O}ptimization: {CMP} {F}ill, {L}ithography and {T}iming},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [42]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c23.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, &#8220;Self-Compensating Design for Focus Variation,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_7\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_7_block\"><pre><code class=\"tex bibtex\">@inproceedings{C23,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D. },\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C23},\nkeywords = {mad},\nmonth = {June},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C23_paper.pdf},\ntitle = {Self-{C}ompensating {D}esign for {F}ocus {V}ariation},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [43]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c20.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Manufacturing-Aware Design Methodology for Assist Feature Correctness,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_5\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_5_block\"><pre><code class=\"tex bibtex\">@inproceedings{C20,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H.},\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C20},\nkeywords = {mad},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C20_paper.pdf},\ntitle = {Manufacturing-{A}ware {D}esign {M}ethodology for {A}ssist {F}eature {C}orrectness},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [44]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c21.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, F. -L. Heng, and J. -F. Lee, &#8220;Toward Through-Process Layout Quality Metrics,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_6\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_6_block\"><pre><code class=\"tex bibtex\">@inproceedings{C21,\nauthor = {Gupta, P. and Heng, F.-L. and Lee, J.-F. },\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C21},\nkeywords = {mad},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C21_paper.pdf},\ntitle = {Toward {T}hrough-{P}rocess {L}ayout {Q}uality {M}etrics},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [45]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c19.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Detailed Placement for Improved Depth of Focus and CD Control,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_4\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_4_block\"><pre><code class=\"tex bibtex\">@inproceedings{C19,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H.},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C19},\nkeywords = {mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C19_paper.pdf},\ntitle = {Detailed {P}lacement for {I}mproved {D}epth of {F}ocus and {CD} {C}ontrol},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [46]                   P. Gupta and A. B. Kahng, &#8220;CMP and DFM,&#8221; in <span style=\"font-style: italic\">CMP-MIC<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_38\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_38_block\"><pre><code class=\"tex bibtex\">@conference{ITT2,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{CMP-MIC}},\ncategory = {ITT2},\nkeywords = {mad},\nnote = {Short Tutorial},\ntitle = {{CMP} and {DFM}},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [47]                   P. Gupta, &#8220;DFM Fundamentals,&#8221; in <span style=\"font-style: italic\">WesCon<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_39\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_39_block\"><pre><code class=\"tex bibtex\">@conference{ITT3,\nauthor = {Gupta, P.},\nbooktitle = {{WesCon}},\ncategory = {ITT3},\nkeywords = {mad},\nnote = {Short Tutorial},\ntitle = {{DFM} {F}undamentals},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [48]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta and F. -L. Heng, &#8220;Toward a Systematic-Variation Aware Timing Methodology,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2004. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_2\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_2_block\"><pre><code class=\"tex bibtex\">@inproceedings{C14,\nauthor = {Gupta, P. and Heng, F.-L.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C14},\nkeywords = {mad},\nmonth = {July},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C14_paper.pdf},\ntitle = {Toward a {S}ystematic-{V}ariation {A}ware {T}iming {M}ethodology},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [49]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, P. Sharma, and D. D. Sylvester, &#8220;Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Reduction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2004. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_3\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_3_block\"><pre><code class=\"tex bibtex\">@inproceedings{C15,\nauthor = {Gupta, P. and Kahng, A. B. and Sharma, P. and D. Sylvester, D.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C5},\nkeywords = {sizing, mad},\nmonth = {July},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C15_paper.pdf},\ntitle = {Selective {G}ate-{L}ength {B}iasing for {C}ost-{E}ffective {R}untime {L}eakage {R}eduction},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [50]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, F. -L. Heng, R. L. Gordon, K. Lai, and J. Lee, &#8220;Taming Focus Variation in VLSI Design,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2004. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_1\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_1_block\"><pre><code class=\"tex bibtex\">@inproceedings{C12,\nauthor = {Gupta, P. and Heng, F.-L. and Gordon, R.L. and Lai, K. and Lee, J. },\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C12},\nkeywords = {mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C12_paper.pdf},\ntitle = {Taming {F}ocus {V}ariation in {VLSI} {D}esign},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [51]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip1b.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta and A. B. Kahng, &#8220;Manufacturing-Aware Physical Design,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2003. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_27\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_27_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP1b,\nauthor = {Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {IP1b},\nkeywords = {mad},\nmonth = {November},\nnote = {Embedded Tutorial},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP1b_paper.pdf},\ntitle = {Manufacturing-{A}ware {P}hysical {D}esign},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [52]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Chen, P. Gupta, and A. B. Kahng, &#8220;Performance-Impact Limited Area Fill Synthesis,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2003. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_26\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_26_block\"><pre><code class=\"tex bibtex\">@inproceedings{C6,\nauthor = {Chen, Y. and Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C6},\nkeywords = {mad},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C6_paper.pdf},\ntitle = {Performance-{I}mpact {L}imited {A}rea {F}ill {S}ynthesis},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [53]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Chen, P. Gupta, and A. B. Kahng, &#8220;Performance-Impact Limited Dummy Fill Insertion,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2003, pp. 857-862. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_12\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_12_block\"><pre><code class=\"tex bibtex\">@inproceedings{C3,\nauthor = {Chen, Y. and Gupta, P. and Kahng, A. B.},\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C3},\nkeywords = {mad},\nmonth = {February},\npages = {857-862},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C3_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C3_slides.pdf},\ntitle = {Performance-{I}mpact {L}imited {D}ummy {F}ill {I}nsertion},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [54]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI,&#8221; in <span style=\"font-style: italic\">IEEE ASIC\/SoC Conference<\/span>,  2002, pp. 411-415. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_0\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_0_block\"><pre><code class=\"tex bibtex\">@inproceedings{C1,\nauthor = {Cao, Y. and Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{IEEE ASIC\/SoC Conference}},\ncategory = {C1},\nkeywords = {mad},\nmonth = {September},\npages = {411-415},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C1_paper.pdf},\ntitle = {Design {S}ensitivities to {V}ariability: {E}xtrapolation and {A}ssessments in {N}anometer {VLSI}},\nyear = {2002}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>   <\/p>\n","protected":false},"excerpt":{"rendered":"<p>For design for manufacturing (DFM) models and methods to be&nbsp; defensible &nbsp;and &nbsp;adoptable, &nbsp;they &nbsp;have &nbsp;to &nbsp;be &nbsp;as &nbsp;simple &nbsp;as &nbsp;possible &nbsp;without &nbsp;losing &nbsp;physical &nbsp;justification.&hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":160,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-166","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/166","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=166"}],"version-history":[{"count":3,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/166\/revisions"}],"predecessor-version":[{"id":250,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/166\/revisions\/250"}],"up":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/160"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=166"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}