{"id":164,"date":"2019-10-02T21:07:25","date_gmt":"2019-10-02T21:07:25","guid":{"rendered":"http:\/\/nanocad.ee.ucla.edu\/?page_id=164"},"modified":"2019-10-07T21:51:24","modified_gmt":"2019-10-07T21:51:24","slug":"benchmarking-and-robustness-of-gate-sizing-heuristics","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=164","title":{"rendered":"Benchmarking and Robustness of Gate Sizing Heuristics"},"content":{"rendered":"\n<p>We are looking into <strong>optimality  of  power  optimization  heuristics<\/strong>, speci\ufb01cally gate sizing. Gate sizing, along with gate length and Vt  assignment, are important methods for physical design. They allow for an  effective optimization method that can balance the power, delay and  area costs. The importance of these methods highlights the importance of  a systematic benchmarking and evaluation methodology to compare  methods, and to gain an understanding of the &#8220;best-practices&#8221; for gate  sizing. These questions are addressed in the research. <\/p>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_85 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=164\/#Empirical_Benchmarking\" >Empirical Benchmarking<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=164\/#Benchmarking_using_Synthetic_Eyecharts\" >Benchmarking using Synthetic Eyecharts<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=164\/#Manufacturing-Aware_Gate_Sizing_Benchmarking_and_ECO-Awareness\" >Manufacturing-Aware Gate Sizing: Benchmarking and ECO-Awareness<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=164\/#Publications\" >Publications:<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Empirical_Benchmarking\"><\/span> Empirical Benchmarking <span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>\nBy: <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/nanocad.ee.ucla.edu\/Main\/SantiagoMok\">Santiago Mok<\/a>, advised by <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/www.ee.ucla.edu\/~puneet\/\">Prof. Puneet Gupta<\/a>\n<em>Objective:<\/em>\nTo investigate benchmarking alternatives and performance of post-layout \ngate sizing algorithm. The first step in this project is to enhance an \nopen-source static timing engine. Spef-reading, Elmore wire delay \ncalculation and power calculation are \nfunctions developed so far that serve as the infrastructure for gate \nsizing algorithm. The enhancement are integrated into <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/openedatools.si2.org\/oagear\/\">OA Gear<\/a> static timing engine. OA Gear is an open source toolkit based on <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/www.si2.org\/?page=621\">Si2 OpenAccess<\/a>. <code>OpenAccess<\/code> is an open source API built on C++ for IC CAD design and development.   <\/p>\n\n\n\n<ul class=\"wp-block-list\"><li> <strong>UCLA-Timer<\/strong> Enhanced Features: <ol><li> Elmore wire delay calculator with SPEF including a wire slew degradation model.\n<\/li><li> A simple power calculator and extended parser functionalities to parse power related entries.\n<\/li><li> Added support for reading units from .lib\/SPEF and ensuring consistency.\n<\/li><li> A simple Ceff calculation (disabled by default).\n<\/li><li> Sensitivity-based gate sizing approaches: (updated 09\/14\/2009) <ul><li> Power Sensitivity\n<\/li><li> Duet Sensitivity based on 1) power-delay and 2) power-slack\n<\/li><\/ul> \n<\/li><\/ol><ul><li> Download: <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/nanocad.ee.ucla.edu\/Main\/DownloadForm\">UCLA-Timer<\/a> (<a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Sizing\/UCLA_tools_LICENSE.txt\">LICENSE<\/a>) (subset of OA Gear, for full OA Gear refer to OAGear project page)\n<\/li><\/ul> \n<\/li><\/ul>\n\n\n\n<p> UCSD benchmarks for gate sizing can be found in this link: <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/vlsicad.ucsd.edu\/SIZING\/\">UC Benchmark Suite for Gate Sizing <\/a> <\/p>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Benchmarking_using_Synthetic_Eyecharts\"><\/span>Benchmarking using Synthetic Eyecharts <span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>\nBy: <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/www.ee.ucla.edu\/~amar\/\">Amarnath Kasibhatla<\/a>, advised by <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/www.ee.ucla.edu\/~puneet\/\">Prof. Puneet Gupta<\/a>\n<\/p>\n\n\n\n<p> <em>Objective:<\/em> Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proved to be NP-hard. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suffered from lack of any systematic way of assessing the quality of the proposed algorithms. We develop methods to generate benchmark circuits (called eyecharts) of arbitrary size along with their optimal solutions calculated using dynamic programming. We evaluate the suboptimalities of some popular gate sizing algorithms. Eyecharts help diagnose weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research. Our results show that common sizing methods (including commercial tools) can be suboptimal by as much as 46% for realistic libraries and circuit topologies. The benchmarks and the code can be downloaded from <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/nanocad.ee.ucla.edu\/Main\/DownloadForm\">EyeCharts<\/a>. <\/p>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Manufacturing-Aware_Gate_Sizing_Benchmarking_and_ECO-Awareness\"><\/span>Manufacturing-Aware Gate Sizing: Benchmarking and ECO-Awareness <span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>\nBy: <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/www.ee.ucla.edu\/~lee\/\">John Lee<\/a>, advised by <a href=\"https:\/\/web.archive.org\/web\/20171028203216\/http:\/\/www.ee.ucla.edu\/~puneet\/\">Prof. Puneet Gupta<\/a>\n<\/p>\n\n\n\n<p>\n<em>Objective:<\/em>\nThis research seeks to answer practical questions related to the gate \nsizing problem (1) what is the advantage of using a statistical power \nobjective in gate sizing, and (2) how can gate sizing be used to perform\n late ECOs. \n<\/p>\n\n\n\n<p>\n(1) In response to the increasing variations in integrated-circuit \nmanufacturing, the current trend is to create\ndesigns that take these variations into account statistically. In this \npaper, we quantify the difference between the statistical and\ndeterministic optima of leakage power while making no assumptions about \nthe delay model.We develop a framework for deriving\na theoretical upper bound on the suboptimality that is incurred by using\n the deterministic optimum as an approximation for the\nstatistical optimum. We show that for the mean power measure, the \ndeterministic optima is an excellent approximation, and for\nthe mean plus standard deviation measures, the optimality gap increases \nas the amount of inter-die variation grows, for a suite of\nbenchmark circuits in a 45 nm technology. For large variations, we show \nthat there are excellent linear approximations that can\nbe used to approximate the effects of variation. Therefore, the need to \ndevelop special statistical power optimization algorithms\nis questionable.\n<\/p>\n\n\n\n<p>\n(2) Circuit design often runs in parallel with the development of the \nmanufacturing process that will be used to\nfabricate it. However, as the manufacturing process matures, its models \nmay undergo substantial changes as the design nears\nproduction. These changes may cause the design itself to fail its \nspecifications, and in these cases it is necessary to perform an\nEngineering Change Order (ECO) to correct these problems. We present a \nnew framework to perform incremental gate sizing\nfor process changes late in the design cycle. This includes a method to \nmeasure and estimate ECO cost, transform these\ncosts into a linear programming optimization problem, and solve the \nproblem to find the ECO. This method performs\nwell, compared to a leading commercial physical design tool, reducing \nECO costs by 18% to 99% in changed area, and 1%\nto 96% in number of pins with unnecessary pin timing changes.\n<\/p>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Publications\"><\/span>Publications:<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c67.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Lee and P. Gupta, &#8220;Impact of range and precision in technology on cell-based design,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_7\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_7_block\"><pre><code class=\"tex bibtex\">@inproceedings{C67,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C67},\nkeywords = {sizing},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C67_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C67_slides.pdf},\ntitle = {Impact of Range and Precision in Technology on Cell-Based Design},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/b2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Lee and P. Gupta, <span style=\"font-style: italic\">Discrete circuit optimization: library based gate sizing and threshold voltage assignment<\/span>, Now Publishers, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_0\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_0_block\"><pre><code class=\"tex bibtex\">@book{B2,\nauthor = {Lee, J. and Gupta, P.},\nisbn = {978-1-60198-542-2},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/B2_paper.pdf},\npublisher = {Now Publishers},\ntitle = {Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j24.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Lee and P. Gupta, &#8220;ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_10\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_10_block\"><pre><code class=\"tex bibtex\">@article{J24,\nauthor = {John Lee and Puneet Gupta},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J24_paper.pdf},\ntitle = {{ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes}},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j25.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Mok, J. Lee, and P. Gupta, &#8220;Discrete sizing for leakage power optimization in physical design: a comparative study,&#8221; <span style=\"font-style: italic\">ACM Transactions on Design Automation of Electronic Systems<\/span>, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_11\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_11_block\"><pre><code class=\"tex bibtex\">@article{J25,\nauthor = {Santiago Mok and John Lee and Puneet Gupta},\njournal = {{ACM Transactions on Design Automation of Electronic Systems}},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J25_paper.pdf},\ntitle = {Discrete Sizing for Leakage Power Optimization in Physical Design: A Comparative Study},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Lee, &#8220;Implications of modern semiconductor technologies on gate sizing,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_16\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_16_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH2,\nauthor = {Lee, John},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH2_paper.pdf},\ntitle = {Implications of Modern Semiconductor Technologies on Gate Sizing},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Mok, &#8220;Post-Layout Sizing for Leakage Power Optimization: A Comparative Study,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_15\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_15_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR4,\nauthor = {Mok, Santiago},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR4_paper.pdf},\ntitle = {{Post-Layout Sizing for Leakage Power Optimization: A Comparative Study}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Cong, P. Gupta, and J. Lee, &#8220;Evaluating Statistical Power Optimization,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, vol. 29, iss. 11, p. 1750\u20131762, 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_9\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_9_block\"><pre><code class=\"tex bibtex\">@article{J12,\nauthor = {Cong, J. and Gupta, P. and Lee, John},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {sizing, mad},\nmonth = {Nov},\nnumber = {11},\npages = {1750--1762},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J12_paper.pdf},\ntitle = {{Evaluating Statistical Power Optimization}},\nvolume = {29},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c51.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Lee and P. Gupta, &#8220;Incremental Gate Sizing for Late Process Changes,&#8221; in <span style=\"font-style: italic\">Proc. IEEE International Conference on Computer Design<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_6\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_6_block\"><pre><code class=\"tex bibtex\">@inproceedings{C51,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{Proc. IEEE International Conference on Computer Design}},\ncategory = {C51},\nkeywords = {sizing, mad},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C51_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C51_slides.pdf},\ntitle = {{I}ncremental {G}ate {S}izing for {L}ate {P}rocess {C}hanges},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c50.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, &#8220;Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_5\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_5_block\"><pre><code class=\"tex bibtex\">@inproceedings{C50,\nauthor = {Gupta, Puneet and Kahng, Andrew and Kasibhatla, Amarnath and Sharma, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C50},\nkeywords = {sizing, eyecharts},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C50_paper.pdf},\ntitle = {{E}yecharts: {C}onstructive {B}enchmarking of {G}ate {S}izing {H}euristics},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. Kasibhatla, &#8220;Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_14\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_14_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR3,\nauthor = {Kasibhatla, Amarnath},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR3_paper.pdf},\ntitle = {{Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Lee and P. Gupta, &#8220;Incremental gate sizing for late process changes,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_17\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_17_block\"><pre><code class=\"tex bibtex\">@conference{W7,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W7},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W7_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W7_slides.pdf},\ntitle = {Incremental Gate Sizing for Late Process Changes},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c38.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Cong, P. Gupta, and J. Lee, &#8220;On the Futlity of Statistical Power Optimization,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_4\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_4_block\"><pre><code class=\"tex bibtex\">@inproceedings{C38,\nauthor = {Cong, J. and Gupta, P. and Lee, John},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\ncategory = {C38},\nkeywords = {sizing, mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C38_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C38_slides.pdf},\ntitle = {On the {F}utlity of {S}tatistical {P}ower {O}ptimization},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           V. Popuri, &#8220;Bias-driven Robust Analog Circuit Sizing Scheme,&#8221; Department of Electrical Engineering, University of California Los Angeles 2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_13\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_13_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR1,\nauthor = {Popuri, Viswakiran},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR1_paper.pdf},\ntitle = {{Bias-driven Robust Analog Circuit Sizing Scheme}},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c32.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, and S. Shah, &#8220;Standard Cell Library Optimization for Leakage Reduction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2006. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_3\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_3_block\"><pre><code class=\"tex bibtex\">@inproceedings{C32,\nauthor = {Gupta, P. and Kahng, A. B. and Shah, S.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C32},\nkeywords = {sizing},\nmonth = {July},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C32_paper.pdf},\ntitle = {Standard {C}ell {L}ibrary {O}ptimization for {L}eakage {R}eduction},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, &#8220;Gate-Length Biasing for Runtime Leakage Control,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2006. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_12\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_12_block\"><pre><code class=\"tex bibtex\">@article{J4,\nauthor = {Gupta, P. and Kahng, A. B. and Sharma, P. and Sylvester, D.},\ncategory = {J4},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {sizing, mad},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J4_paper.pdf},\ntitle = {Gate-{L}ength {B}iasing for {R}untime {L}eakage {C}ontrol},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c18.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, and P. Sharma, &#8220;A Practical Transistor-Level Threshold Voltage Assignment Methodology,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2005, pp. 261-265. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_2\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_2_block\"><pre><code class=\"tex bibtex\">@inproceedings{C18,\nauthor = {Gupta, P. and Kahng, A. B. and Sharma, P.},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\ncategory = {C18},\nkeywords = {sizing},\nmonth = {March},\npages = {261-265},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C18_paper.pdf},\ntitle = {A {P}ractical {T}ransistor-{L}evel {T}hreshold {V}oltage {A}ssignment {M}ethodology},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, P. Sharma, and D. D. Sylvester, &#8220;Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Reduction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2004. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_1\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_1_block\"><pre><code class=\"tex bibtex\">@inproceedings{C15,\nauthor = {Gupta, P. and Kahng, A. B. and Sharma, P. and D. Sylvester, D.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C5},\nkeywords = {sizing, mad},\nmonth = {July},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C15_paper.pdf},\ntitle = {Selective {G}ate-{L}ength {B}iasing for {C}ost-{E}ffective {R}untime {L}eakage {R}eduction},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2003. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_8\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_8_block\"><pre><code class=\"tex bibtex\">@inproceedings{C7,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C7},\nkeywords = {sizing, dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C7_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C7_slides.pdf},\ntitle = {A {C}ost-{D}riven {L}ihographic {C}orrection {M}ethodology {B}ased on {O}ff-the-{S}helf {S}izing {T}ools},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>  <\/p>\n","protected":false},"excerpt":{"rendered":"<p>We are looking into optimality of power optimization heuristics, speci\ufb01cally gate sizing. Gate sizing, along with gate length and Vt assignment, are important methods for&hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":160,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-164","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/164","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=164"}],"version-history":[{"count":3,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/164\/revisions"}],"predecessor-version":[{"id":246,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/164\/revisions\/246"}],"up":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/160"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=164"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}