{"id":162,"date":"2019-10-02T21:06:57","date_gmt":"2019-10-02T21:06:57","guid":{"rendered":"http:\/\/nanocad.ee.ucla.edu\/?page_id=162"},"modified":"2019-10-07T21:51:36","modified_gmt":"2019-10-07T21:51:36","slug":"design-assisted-technology-scaling","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=162","title":{"rendered":"Design-Assisted Technology Scaling"},"content":{"rendered":"\n<p> The semiconductor industry is likely to see several rad- ical changes in  the fabrication and device technologies in the next decade. Each of  these technologies requires enormous research investment before they can  see any adoption. Con- ventional \u201cafter-the-fact\u201d changes to design  methodologies and tools to what technology o\ufb00ers lead to wasted research  investment, delayed adoption and underutilization of technology as well  as more design overhead. Therefore, early assessment of design  restrictions imposed by, and design advantages of technological choices  is absolutely essential. In addition to <strong>building such co-evaluation frameworks<\/strong>, we have pioneered several techniques to enable <strong>silicon manufacturing guided by design<\/strong> and also explore <strong>design-enablement of future patterning<\/strong> options. <\/p>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=162\/#A_Framework_for_Early_and_Systematic_Evaluation_and_Exploration_of_Design_Rules\" >A Framework for Early and Systematic Evaluation and Exploration of Design Rules<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=162\/#A_Framework_for_Evaluating_Device_Variability_Impact_on_Circuits\" >A Framework for Evaluating Device Variability Impact on Circuits<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=162\/#Publications\" >Publications<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"A_Framework_for_Early_and_Systematic_Evaluation_and_Exploration_of_Design_Rules\"><\/span>A Framework for Early and Systematic Evaluation and Exploration of Design Rules<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p><strong>Students:<\/strong> <a rel=\"noreferrer noopener\" href=\"http:\/\/www.ee.ucla.edu\/~rani\/\" target=\"_blank\">Rani S. Ghaida<\/a>, <a rel=\"noreferrer noopener\" href=\"http:\/\/www.ee.ucla.edu\/~abdeali\/\" target=\"_blank\">Abde Ali Kagalwalla<\/a><\/p>\n\n\n\n<p><strong>Objective:<\/strong> A framework for co-evaluation and exploration of  design rules and technology decisions at cell and chip levels. By using  first order models of variability and manufacturability and layout  topology\/congestion-based area estimation, our framework can evaluate  big decisions before exact process and design technologies are known.<\/p>\n\n\n\n<p><strong>UCLA_DRE<\/strong>  is a tool written in C++ for evaluating and exploring design rules  (DRs) and layout styles at cell level in standard-cell based designs.<\/p>\n\n\n\n<p>The tool takes a transistor netlist, design rules, and estimates of  process control parameters as input and evaluates cell-area,  manufacturability, and variability of the entire design. It also  displays evaluation results and layout information of every cell in the  design separately. The latest release can be downloaded here (LICENSE).<\/p>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"A_Framework_for_Evaluating_Device_Variability_Impact_on_Circuits\"><\/span>A Framework for Evaluating Device Variability Impact on Circuits<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Students: <a href=\"http:\/\/www.ee.ucla.edu\/~liangzhe\/\" target=\"_blank\" rel=\"noreferrer noopener\">Liangzhen Lai<\/a>, <a href=\"http:\/\/www.ee.ucla.edu\/~shaodiw\/\" target=\"_blank\" rel=\"noreferrer noopener\">Shaodi Wang<\/a><\/p>\n\n\n\n<p><em>Objective:<\/em> A framework for evaluating the impact of \ndevice-level variability on circuit-level performance. An evaluation \nflow is implemented to automatically take device-level performance \nfigures (i.e. Ion, Ioff, DIBL, SS etc.) variations as input, and \ngenerate corresponding variation data on circuit-level performance (i.e.\n leakage power, delay etc.). The framework is applied to line edge \nroughness (LER) induced variability on double-gate finfet. The sample \ndata can be downloaded here:<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>LER_circuit_data.xlsx: LER_circuit_data.xlsx<\/li><\/ul>\n\n\n\n<hr class=\"wp-block-separator\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Publications\"><\/span>Publications<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p> <ul class=\"papercite_bibliography\">          [1]                   P. Gupta, &#8220;Design Technology Co-Optimization for EUV (Keynote Talk),&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Advanced Patterning Solutions<\/span>,  2022. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_45\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_45_block\"><pre><code class=\"tex bibtex\">@conference{ITT30,\nauthor = {Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Advanced Patterning Solutions}},\nkeywords = {dats},\ntitle = {{Design Technology Co-Optimization for EUV (Keynote Talk)}},\nyear = {2022}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c97.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Badr and P. Gupta, &#8220;Technology Path-finding for Directed Self-assembly for Via Layers&#8221;,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_34\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_34_block\"><pre><code class=\"tex bibtex\">@inproceedings{C97,\nauthor = {Badr, Yasmine and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C97_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C97_slides.pdf},\ntitle = {{T}echnology {P}ath-finding for {D}irected {S}elf-assembly for {V}ia {L}ayers\"},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [3]                   P. Gupta, &#8220;Design technology co-optimization for disruptive patterning schemes,&#8221; in <span style=\"font-style: italic\">China Semiconductor Technology International Conference (CSTIC)<\/span>,  2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_43\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_43_block\"><pre><code class=\"tex bibtex\">@conference{ITT26,\nauthor = {P. Gupta},\nbooktitle = {{China Semiconductor Technology International Conference (CSTIC)}},\nkeywords = {dats},\ntitle = {Design Technology Co-optimization for Disruptive Patterning Schemes},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [4]                   P. Gupta and J. A. Torres, &#8220;Understanding design-patterning interactions for euv and dsa,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_44\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_44_block\"><pre><code class=\"tex bibtex\">@conference{ITT27,\nauthor = {P. Gupta and J.A. Torres},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nnote = {Short Course},\ntitle = {Understanding Design-Patterning Interactions for EUV and DSA},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j52.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Badr and P. Gupta, &#8220;Technology path-finding framework for directed-self assembly for via layers,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_62\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_62_block\"><pre><code class=\"tex bibtex\">@article{J52,\nauthor = {Badr, Yasmine and Gupta, Puneet},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J52_paper.pdf},\ntitle = {Technology path-finding framework for directed-self assembly for via layers},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Badr, &#8220;Co-optimization of restrictive patterning technologies and design,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_66\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_66_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH8,\nauthor = {Badr, Yasmine},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH8_paper.pdf},\ntitle = {Co-optimization of Restrictive Patterning Technologies and Design},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j48.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Badr, A. Torres, and P. Gupta, &#8220;Mask Assignment and Dsa Grouping for DSA-MP Hybrid Lithography for sub-7nm Contact\/Via Holes,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2016. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_60\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_60_block\"><pre><code class=\"tex bibtex\">@article{J48,\nauthor = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},\ncategory = {J48},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J48_paper.pdf},\ntitle = {{M}ask {A}ssignment and {D}SA {G}rouping for {DSA-MP} {H}ybrid {L}ithography for sub-7nm {C}ontact\/{V}ia {H}oles},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j45.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           L. Zhu, Y. Badr, S. Wang, S. Iyer, and P. Gupta, &#8220;Assessing Benefits of a Buried Interconnect Layer in Digital Designs,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2016. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_59\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_59_block\"><pre><code class=\"tex bibtex\">@article{J45,\nauthor = {Zhu, Liheng and Badr, Yasmine and Wang, Shaodi and Iyer, Subramanian and Gupta, Puneet},\ncategory = {J45},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\nmonth = {May},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J45_paper.pdf},\ntitle = {Assessing {B}enefits of a {B}uried {I}nterconnect {L}ayer in {D}igital {D}esigns},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [9]                   P. Gupta and J. A. Torres, &#8220;Understanding design-patterning interactions for euv and dsa,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2016. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_42\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_42_block\"><pre><code class=\"tex bibtex\">@conference{ITT20,\nauthor = {P. Gupta and J.A. Torres},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nnote = {Short Course},\ntitle = {Understanding Design-Patterning Interactions for EUV and DSA},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j44.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, and A. B. Kahng, &#8220;Benchmarking of Mask Fracturing Heuristics,&#8221; in <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>,  2016. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_58\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_58_block\"><pre><code class=\"tex bibtex\">@inproceedings{J44,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. },\nbooktitle = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\ncategory = {J44},\nkeywords = {dats},\nmonth = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J44_paper.pdf},\ntitle = {Benchmarking of {M}ask {F}racturing {H}euristics},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c86.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Badr, A. Torres, and P. Gupta, &#8220;Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts\/Vias,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2015. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_32\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_32_block\"><pre><code class=\"tex bibtex\">@inproceedings{C86,\nauthor = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C86_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C86_slides.pdf},\ntitle = { {M}ask {A}ssignment and {S}ynthesis of {DSA}-{MP} {H}ybrid {L}ithography for sub-7nm {C}ontacts\/{V}ias},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c87.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. A. Kagalwalla and P. Gupta, &#8220;Effective Model-Based Mask Fracturing for Mask Cost Reduction,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2015. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_33\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_33_block\"><pre><code class=\"tex bibtex\">@inproceedings{C87,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C87_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C87_slides.pptx},\ntitle = { {E}ffective {M}odel-{B}ased {M}ask {F}racturing for {M}ask {C}ost {R}eduction},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c85.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Badr, A. Torres, and P. Gupta, &#8220;Incorporating DSA in multipatterning semiconductor manufacturing technologies,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2015. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_31\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_31_block\"><pre><code class=\"tex bibtex\">@inproceedings{C85,\nauthor = {Badr, Yasmine and Torres, Andres and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C85_paper.pdf},\ntitle = { {I}ncorporating {DSA} in {m}ultipatterning {s}emiconductor {m}anufacturing {t}echnologies},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [14]                   P. Gupta, A. Mallik, and J. A. Torres, &#8220;Patterning beyond multiple patterning,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2015. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_41\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_41_block\"><pre><code class=\"tex bibtex\">@conference{ITT19,\nauthor = {P. Gupta and A. Mallik and J.A. Torres},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\nkeywords = {dats},\nnote = {Embedded tutorial},\ntitle = {Patterning beyond multiple patterning},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c80.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, A. B. Kahng, and E. Sahouria, &#8220;Benchmarking of Mask Fracturing Heuristics,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_29\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_29_block\"><pre><code class=\"tex bibtex\">@inproceedings{C80,\nauthor = {Chan, Tuck Boon and Gupta, Puneet and Han, Kwangsoo and Kagalwalla, Abde Ali and Kahng, Andrew B. and Sahouria, Emile},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C80},\nkeywords = {dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C80_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C80_slides.pdf},\ntitle = {Benchmarking of {M}ask {F}racturing {H}euristics},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c81.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           W. Wang and P. Gupta, &#8220;Efficient Layout Generation and Evaluation of Vertical Channel Devices,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_30\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_30_block\"><pre><code class=\"tex bibtex\">@inproceedings{C81,\nauthor = {Wang, Wei-Che and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C81},\nkeywords = {dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C81_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C81_slides.pdf},\ntitle = {{E}fficient {L}ayout {G}eneration and {E}valuation of {V}ertical {C}hannel {D}evices},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [17]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c76.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Kulkarni, P. Gupta, and R. Beraha, &#8220;Minimizing Clock Domain Crossing in Network on Chip Interconnect,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_26\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_26_block\"><pre><code class=\"tex bibtex\">@inproceedings{C76,\nauthor = {Kulkarni, Parag and Gupta, Puneet and Beraha, Rudy},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\nkeywords = {dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C76_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C76_slides.pdf},\ntitle = {{M}inimizing {C}lock {D}omain {C}rossing in {N}etwork on {C}hip {I}nterconnect},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [18]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c77.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. A. Kagalwalla and P. Gupta, &#8220;Comprehensive Defect Avoidance Framework for Mitigating EUV Mask Defects,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_27\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_27_block\"><pre><code class=\"tex bibtex\">@inproceedings{C77,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C77_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C77_slides.pdf},\ntitle = {{C}omprehensive {D}efect {A}voidance {F}ramework for {M}itigating {EUV} {M}ask {D}efects},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c78.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Badr, K. Ma, and P. Gupta, &#8220;Layout Pattern-driven Design Rule Evaluation,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_28\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_28_block\"><pre><code class=\"tex bibtex\">@inproceedings{C78,\nauthor = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C78_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C78_slides.pdf},\ntitle = {{L}ayout {P}attern-driven {D}esign {R}ule {E}valuation},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [20]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c74.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, &#8220;Comprehensive Die-level Assessment of Design Rules and Layouts,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_24\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_24_block\"><pre><code class=\"tex bibtex\">@inproceedings{C74,\nauthor = {Ghaida, R. S. and Badr, Yasmine and Gupta, Mukul and Jin, Ning and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {dats,dre},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C74_slides.pdf},\ntitle = {{C}omprehensive {D}ie-Level {A}ssessment of {D}esign {R}ules and {L}ayouts},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [21]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c75.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           S. Wang, A. Pan, C. O. Chui, and P. Gupta, &#8220;PROCEED: a Pareto Optimization-based Circuit-level Evaluator for Emerging Devices,&#8221; in <span style=\"font-style: italic\">Proc. Asia and South Pacific Design Automation Conference<\/span>,  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_25\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_25_block\"><pre><code class=\"tex bibtex\">@inproceedings{C75,\nauthor = {Wang, Shaodi and Pan, Andrew and Chui, Chi On and Gupta, Puneet},\nbooktitle = {{Proc. Asia and South Pacific Design Automation Conference}},\nkeywords = {dats,proceed},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C75_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C75_slides.pptx},\ntitle = {{PROCEED:} A {P}areto {O}ptimization-based {C}ircuit-level {E}valuator for {E}merging {D}evices},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [22]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j35.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>   <a href='http:\/\/dx.doi.org\/10.1117\/1.JMM.13.4.043005' class='papercite_doi' title='View document on publisher site'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/external.png' width='10' height='10' alt='[DOI]' \/><\/a>        A. A. Kagalwalla and P. Gupta, &#8220;Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, vol. 13, iss. 4, p. 43005, 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_56\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_56_block\"><pre><code class=\"tex bibtex\">@article{J35,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\ndoi = {10.1117\/1.JMM.13.4.043005},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\nnumber = {4},\npages = {043005},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J35_paper.pdf},\ntitle = {Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects},\nvolume = {13},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [23]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j36.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Badr, K. Ma, and P. Gupta, &#8220;Layout pattern-driven design rule evaluation,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_57\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_57_block\"><pre><code class=\"tex bibtex\">@article{J36,\nauthor = {Badr, Yasmine and Ma, Ko-wei and Gupta, Puneet},\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J36_paper.pdf},\ntitle = {Layout Pattern-driven Design Rule Evaluation},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [24]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. A. Kagalwalla, &#8220;Computational methods for design-assisted mask flows,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_65\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_65_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH4,\nauthor = {Kagalwalla, Abde Ali},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH4_paper.pdf},\ntitle = {Computational Methods for Design-Assisted Mask Flows},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [25]                   R. S. Ghaida and P. Gupta, &#8220;Role of design in multiple patterning: technology development, design enablement and process control,&#8221; in <span style=\"font-style: italic\">IEEE\/ACM Design, Automation and Test in Europe<\/span>,  2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_36\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_36_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP11,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{IEEE\/ACM Design, Automation and Test in Europe}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/mp_and_design_date13.pdf},\ntitle = {Role of Design in Multiple Patterning: Technology\nDevelopment, Design Enablement and Process Control},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [26]                   P. Gupta, A. Mallik, and J. A. Torres, &#8220;Design-patterning interactions,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_40\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_40_block\"><pre><code class=\"tex bibtex\">@conference{ITT18,\nauthor = {P. Gupta and A. Mallik and J.A. Torres},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {dats},\nnote = {Half-Day tutorial.},\ntitle = {Design-Patterning Interactions},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [27]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j28.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. A. Kagalwalla and P. Gupta, &#8220;Design-Aware Defect-Avoidance Floorplanning of EUV Masks,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, vol. 26, 2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_55\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_55_block\"><pre><code class=\"tex bibtex\">@article{J28,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet},\nissue = {1},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J28_paper.pdf},\ntitle = {{Design-Aware Defect-Avoidance Floorplanning of EUV Masks}},\nvolume = {26},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [28]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c64.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, &#8220;A methodology for the early exploration of design rules for multiple-patterning technologies,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_22\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_22_block\"><pre><code class=\"tex bibtex\">@inproceedings{C64,\nauthor = {Ghaida, R. S. and Sahu, T. and Kulkarni, P. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C64},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C64_slides.pdf},\ntitle = {A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [29]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, &#8220;O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,&#8221; in <span style=\"font-style: italic\">Intl. Conf. on IC Design and Technology<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_39\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_39_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP9,\nauthor = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},\nbooktitle = {{Intl. Conf. on IC Design and Technology}},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/ip9_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/ip9_slides.pdf},\ntitle = {O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [30]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c62.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta, &#8220;Design-of-Experiments Based Design Rule Optimization,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_20\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_20_block\"><pre><code class=\"tex bibtex\">@inproceedings{C62,\nauthor = {Kagalwalla, Abde Ali and Muddu, Swamy and Capodieci, Luigi and Zelnik, Coby and Gupta, Puneet },\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C62},\nkeywords = {Design Rules, DOE, dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C62_paper.pdf},\ntitle = {{D}esign-of-{E}xperiments {B}ased {D}esign {R}ule {O}ptimization},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [31]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c63.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, K. Agarwal, L. Liebmann, S. R. Nassif, and P. Gupta, &#8220;A Novel Methodology for Triple\/Multiple-Patterning Layout Decomposition,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_21\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_21_block\"><pre><code class=\"tex bibtex\">@inproceedings{C63,\nauthor = {Ghaida, R. S. and Agarwal, K. and Liebmann, L. and Nassif, S. R. and Gupta, P.},\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C63},\nkeywords = {triple patterning, double patterning, dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C63_paper.pdf},\ntitle = {{A} {N}ovel {M}ethodology for {T}riple\/{M}ultiple-{P}atterning {L}ayout {D}ecomposition},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [32]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j18.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, &#8220;Design-Aware Mask Inspection,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_52\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_52_block\"><pre><code class=\"tex bibtex\">@article{J18,\nauthor = {Kagalwalla, Abde Ali and Puneet Gupta and Progler, Chris and McDonald, Steve},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J18_paper.pdf},\ntitle = {Design-{A}ware {M}ask {I}nspection},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [33]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j19.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida and P. Gupta, &#8220;DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_53\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_53_block\"><pre><code class=\"tex bibtex\">@article{J19,\nauthor = {Ghaida, R. S. and Gupta, P.},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {design rules, technology assessment, dre, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J19_paper.pdf},\ntitle = {{DRE}: a {F}ramework for {E}arly {C}o-{E}valuation of {D}esign {R}ules, {T}echnology {C}hoices, and {L}ayout {M}ethodologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [34]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j27.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, &#8220;Layout Decomposition and Legalization for Double-Patterning Technology,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_54\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_54_block\"><pre><code class=\"tex bibtex\">@article{J27,\nauthor = {Ghaida, R. S. and Agarwal, K. B. and Nassif, S. R. and Yuan, X. and Liebmann, L. W. and Gupta, P.},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi, multiple-patterning},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J27_paper.pdf},\ntitle = {{L}ayout {D}ecomposition and {L}egalization for {D}ouble-{P}atterning {T}echnology},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [35]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, &#8220;Design enablement and design-centric assessment of future semiconductor technologies,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_64\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_64_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH3,\nauthor = {Ghaida, R. S.},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH3_paper.pdf},\ntitle = {Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [36]                   R. S. Ghaida, M. Gupta, and P. Gupta, &#8220;A framework for exploring the interaction between design rules and overlay control,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_69\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_69_block\"><pre><code class=\"tex bibtex\">@conference{W11,\nauthor = {Ghaida, R. S. and Gupta, M. and Gupta, P.},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W11},\nkeywords = {dats, dre, design rules, overlay, alignment, process, multiple-patterning, lithography},\ntitle = {A Framework for Exploring the Interaction Between Design Rules and Overlay Control},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [37]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c59.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, &#8220;A Framework for Double Patterning-Enabled Design,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_19\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_19_block\"><pre><code class=\"tex bibtex\">@inproceedings{C59,\nauthor = {Ghaida, R. S. and Agarwal, K. and Nassif, S. and Yuan, X. and Liebmann, L. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C59},\nkeywords = {dats, double-patterning, compaction, dpl, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C59_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C59_slides.pdf},\ntitle = {A {F}ramework for {D}ouble {P}atterning-{E}nabled {D}esign},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [38]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c57.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. A. Kagalwalla, P. Gupta, D. Hur, and C. Park, &#8220;Defect-aware Reticle Floorplanning for EUV Masks,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_18\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_18_block\"><pre><code class=\"tex bibtex\">@inproceedings{C57,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet and Hur, Duck-Hyung and Park, Chul-Hong },\nbooktitle = {{SPIE Advanced Lithography}},\ncategory = {C57},\nkeywords = {EUV, floorplanning, dats},\nmonth = {March},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C57_paper.pdf},\ntitle = {{D}efect-aware {R}eticle {F}loorplanning for {EUV} {M}asks},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [39]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j15.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. B. Chan, A. A. Kagalwalla, and P. Gupta, &#8220;Measurement and Optimization of Electrical Process Window,&#8221; <span style=\"font-style: italic\">SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)<\/span>, 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_51\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_51_block\"><pre><code class=\"tex bibtex\">@article{J15,\nauthor = {Chan, T.B. and Kagalwalla, Abde Ali and Gupta, P. },\njournal = {{SPIE Journal of Micro\/Nanolithography, MEMS and MOEMS (JM3)}},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J15_paper.pdf},\ntitle = {{M}easurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [40]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/w10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           J. Lee and P. Gupta, &#8220;Parametric hierarchy recovery for layout extracted netlists,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_68\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_68_block\"><pre><code class=\"tex bibtex\">@conference{W10,\nauthor = {Lee, John and Gupta, Puneet},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W10},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W10_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/W10_slides.pdf},\ntitle = {Parametric Hierarchy Recovery for Layout Extracted Netlists},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [41]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c52.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, &#8220;Design-aware Mask Inspection,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_16\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_16_block\"><pre><code class=\"tex bibtex\">@inproceedings{C52,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C52},\nkeywords = {mask manufacturing, inspection, dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C52_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C52_slides.pdf},\ntitle = {{D}esign-aware {M}ask {I}nspection},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [42]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c53.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. -B. Chan, A. Pant, L. Cheng, and P. Gupta, &#8220;Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_17\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_17_block\"><pre><code class=\"tex bibtex\">@inproceedings{C53,\nauthor = {Chan, T.-B. and Pant, Aashish and Cheng, Lerong and Gupta, Puneet},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C53},\nkeywords = {process variation, process monitoring, dats},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C53_slides.pdf},\ntitle = {{D}esign {D}ependent {P}rocess {M}onitoring for {B}ack-end {M}anufacturing {C}ost {R}eduction},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [43]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c46.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. -B. Chan, A. A. Kagalwalla, and P. Gupta, &#8220;Measurement and Optimization of Electrical Process Window,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_15\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_15_block\"><pre><code class=\"tex bibtex\">@inproceedings{C46,\nauthor = {Chan, T.-B. and Kagalwalla, Abde Ali and Gupta, P.},\nbooktitle = {{Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration}},\ncategory = {C46},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C46_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C46_slides.pdf},\ntitle = {Measurement and {O}ptimization of {E}lectrical {P}rocess {W}indow},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [44]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c45.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           T. -B. Chan and P. Gupta, &#8220;On Electrical Modeling of Imperfect Diffusion Patterning,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on VLSI Design<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_14\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_14_block\"><pre><code class=\"tex bibtex\">@inproceedings{C45,\nauthor = {Chan, T.-B. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on VLSI Design}},\ncategory = {C45},\nkeywords = {dats, mad},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C45_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C45_slides.pdf},\ntitle = {On {E}lectrical {M}odeling of {I}mperfect {D}iffusion {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [45]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida and P. Gupta, &#8220;Within-Layer Overlay Impact for Design in Metal Double Patterning,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_48\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_48_block\"><pre><code class=\"tex bibtex\">@article{J10,\nauthor = {Ghaida, R. S. and Gupta, P.},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {double patterning, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J10_paper.pdf},\ntitle = {Within-{L}ayer {O}verlay {I}mpact for {D}esign in {M}etal {D}ouble {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [46]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, &#8220;Electrical Assessment of Lithographic Gate Line-End Patterning,&#8221; <span style=\"font-style: italic\">spieJ<\/span>, 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_49\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_49_block\"><pre><code class=\"tex bibtex\">@article{J11,\nauthor = {Gupta, P. and Jeong, K. and Kahng, A.B. and Park, C.-H.},\njournal = {{spieJ}},\nkeywords = {mad, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J11_paper.pdf},\ntitle = {Electrical {A}ssessment of {L}ithographic {G}ate {L}ine-{E}nd {P}atterning},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [47]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, G. Torres, and P. Gupta, &#8220;Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Semiconductor Manufacturing<\/span>, 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_50\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_50_block\"><pre><code class=\"tex bibtex\">@article{J13,\nauthor = {Ghaida, R. S. and Torres, G. and Gupta, P.},\njournal = {{IEEE Transactions on Semiconductor Manufacturing}},\nkeywords = {double patterning, stdpl, dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J13_paper.pdf},\ntitle = {{S}ingle-{M}ask {D}ouble-{P}atterning {L}ithography for {R}educed {C}ost and {I}mproved {O}verlay {C}ontrol},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [48]                   A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, &#8220;Design-aware Mask Inspection,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_71\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_71_block\"><pre><code class=\"tex bibtex\">@conference{W6,\nauthor = {Kagalwalla, Abde Ali and Gupta, Puneet and Progler, Chris and McDonald, Steve},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W6},\nkeywords = {dats},\ntitle = {{D}esign-aware {M}ask {I}nspection},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [49]                   V. Popuri, P. Gupta, and S. Pamarti, &#8220;Bias-Driven Robust Analog Circuit Sizing Scheme,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_72\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_72_block\"><pre><code class=\"tex bibtex\">@conference{W8,\nauthor = {Popuri, V. and Gupta, P. and Pamarti, S.},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W8},\nkeywords = {dats},\ntitle = {{Bias-Driven Robust Analog Circuit Sizing Scheme}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [50]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c44.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida and P. Gupta, &#8220;A Framework for Early and Systematic Evaluation of Design Rules,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_13\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_13_block\"><pre><code class=\"tex bibtex\">@inproceedings{C44,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {C44},\nkeywords = {dats, design rules, dre, dmi},\nmonth = {November},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C44_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C44_slides.pdf},\ntitle = {A {F}ramework for {E}arly and {S}ystematic {E}valuation of {D}esign {R}ules},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [51]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c41.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida, G. Torres, and P. Gupta, &#8220;Single-Mask Double-Patterning Lithography,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_11\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_11_block\"><pre><code class=\"tex bibtex\">@inproceedings{C41,\nauthor = {Ghaida, R. S. and Torres, G. and Gupta, P.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\nkeywords = {dats},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C41_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C41_slides.pdf},\ntitle = {Single-{M}ask {D}ouble-{P}atterning {L}ithography},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [52]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c40.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           R. S. Ghaida and P. Gupta, &#8220;Design-Overlay Interactions in Metal Double Patterning,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_10\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_10_block\"><pre><code class=\"tex bibtex\">@inproceedings{C40,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\nkeywords = {double patterning, test pattern, dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C40_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C40_slides.pdf},\ntitle = {Design-{O}verlay {I}nteractions in {M}etal {D}ouble {P}atterning},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [53]                   P. Gupta and D. Reinhard, &#8220;On Comparing Conventional and Electrically Driven OPC Techniques,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_12\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_12_block\"><pre><code class=\"tex bibtex\">@inproceedings{C42,\nauthor = {Gupta, P. and Reinhard, D.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\ncategory = {C42},\nkeywords = {dats},\nmonth = {},\ntitle = {On {C}omparing {C}onventional and {E}lectrically {D}riven {OPC} {T}echniques},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [54]                   R. S. Ghaida and P. Gupta, &#8220;A Framework for Systematic Evaluation and Exploration of Design Rules,&#8221; in <span style=\"font-style: italic\">SRC TECHCON&#8217;09<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_67\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_67_block\"><pre><code class=\"tex bibtex\">@conference{W1,\nauthor = {Ghaida, R. S. and Gupta, P.},\nbooktitle = {{SRC TECHCON'09}},\ncategory = {W1},\nkeywords = {dats},\nmonth = {},\npages = {},\ntitle = {A {F}ramework for {S}ystematic {E}valuation and {E}xploration of {D}esign {R}ules},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [55]                   T. -B. Chan, P. Gupta, V. Balakrishnan, and Y. Cao, &#8220;Extended Burn-in for Reduced Vth Variation,&#8221; in <span style=\"font-style: italic\">IEEE International Workshop on Design for Manufacturibility and Yield<\/span>,  2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_70\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_70_block\"><pre><code class=\"tex bibtex\">@conference{W4,\nauthor = {Chan, T.-B. and Gupta, Puneet and Balakrishnan, Varsha and Cao, Yu},\nbooktitle = {{IEEE International Workshop on Design for Manufacturibility and Yield}},\ncategory = {W4},\nkeywords = {dats},\ntitle = {{E}xtended {B}urn-in for {R}educed {V}th {V}ariation},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>          [56]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c36.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, K. Jeong, A. B. Kahng, and C. -H. Park, &#8220;Electrical Metrics for Lithographic Line-End Tapering,&#8221; in <span style=\"font-style: italic\">SPIE Photomask and NGL Mask Technology<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_9\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_9_block\"><pre><code class=\"tex bibtex\">@inproceedings{C36,\nauthor = {Gupta, P. and Jeong, K. and Kahng, A. B. and Park, C.-H},\nbooktitle = {{SPIE Photomask and NGL Mask Technology}},\ncategory = {C36},\nkeywords = {mad, dats},\nmonth = {April},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C36_paper.pdf},\ntitle = {Electrical {M}etrics for {L}ithographic {L}ine-{E}nd {T}apering},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [57]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c35.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, &#8220;Shaping Gate Channels for Improved Devices,&#8221; in <span style=\"font-style: italic\">SPIE Advanced Lithography Symposium<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_8\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_8_block\"><pre><code class=\"tex bibtex\">@inproceedings{C35,\nauthor = {Gupta, P. and Kahng, A. B. and Shah, S. and Sylvester, D.},\nbooktitle = {{SPIE Advanced Lithography Symposium}},\ncategory = {C35},\nkeywords = {dats, mad},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C35_paper.pdf},\ntitle = {Shaping {G}ate {C}hannels for {I}mproved {D}evices},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [58]                   P. Gupta, &#8220;The Electrical Design Manufacturing Interface,&#8221; in <span style=\"font-style: italic\">Electronic Design Processes Workshop<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_46\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_46_block\"><pre><code class=\"tex bibtex\">@conference{ITT5,\nauthor = {Gupta, P.},\nbooktitle = {{Electronic Design Processes Workshop}},\ncategory = {ITT5},\nkeywords = {mad, dats},\ntitle = {The {E}lectrical {D}esign {M}anufacturing {I}nterface},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [59]                   P. Gupta, &#8220;Challenges at 45nm and Beyond,&#8221; in <span style=\"font-style: italic\">Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/span>,  2008. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_47\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_47_block\"><pre><code class=\"tex bibtex\">@conference{ITT8,\nauthor = {Gupta, P.},\nbooktitle = {{Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)}},\ncategory = {ITT8},\nkeywords = {mad, dats},\nnote = {Panel Discussion},\ntitle = {Challenges at 45nm and {B}eyond},\nyear = {2008}\n}<\/code><\/pre><\/div>   <\/br>          [60]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Performance-Driven Optical Proximity Correction for Mask Cost Reduction,&#8221; <span style=\"font-style: italic\">spieJ<\/span>, 2007. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_63\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_63_block\"><pre><code class=\"tex bibtex\">@article{J8,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\ncategory = {J8},\njournal = {{spieJ}},\nkeywords = {dats},\nmonth = {September},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J8_paper.pdf},\ntitle = {Performance-{D}riven {O}ptical {P}roximity {C}orrection for {M}ask {C}ost {R}eduction},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [61]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c33.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, &#8220;Line End Shortening is not Always a Failure,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2007. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_7\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_7_block\"><pre><code class=\"tex bibtex\">@inproceedings{C33,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Shah, S.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C2},\nkeywords = {mad, dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C33_paper.pdf},\ntitle = {Line {E}nd {S}hortening is not {A}lways a {F}ailure},\nyear = {2007}\n}<\/code><\/pre><\/div>   <\/br>          [62]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/j5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, C. -H. Park, K. Samadi, and X. Xu, &#8220;Wafer Topography-Aware Optical Proximity Correction,&#8221; <span style=\"font-style: italic\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/span>, 2006. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_61\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_61_block\"><pre><code class=\"tex bibtex\">@article{J5,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Samadi, K. and Xu, X.},\ncategory = {J5},\njournal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}},\nkeywords = {dats},\nmonth = {April},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/J5_paper.pdf},\ntitle = {Wafer {T}opography-{A}ware {O}ptical {P}roximity {C}orrection},\nyear = {2006}\n}<\/code><\/pre><\/div>   <\/br>          [63]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c25.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, S. Muddu, O. S. Nakagawa, and C. -H. Park, &#8220;Modeling OPC Complexity for Design for Manufacturability,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_5\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_5_block\"><pre><code class=\"tex bibtex\">@inproceedings{C25,\nauthor = {Gupta, P. and Kahng, A. B. and Muddu,S. and Nakagawa, O.S. and Park, C.-H.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\ncategory = {C25},\nkeywords = {dats},\nmonth = {October},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C25_paper.pdf},\ntitle = {Modeling {OPC} {C}omplexity for {D}esign for {M}anufacturability},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [64]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c26.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           Y. Zhang, R. Gray, O. S. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and C. Progler, &#8220;Interaction and Balance of Mask Write Time and Design RET Strategies,&#8221; in <span style=\"font-style: italic\">SPIE Photomask and NGL Mask Technology<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_6\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_6_block\"><pre><code class=\"tex bibtex\">@inproceedings{C26,\nauthor = {Zhang, Y. and Gray, R. and Nakagawa, O.S. and Gupta, P. and Kamberian, H. and Xiao, G. and Cottle, R. and Progler, C.},\nbooktitle = {{SPIE Photomask and NGL Mask Technology}},\ncategory = {C26},\nkeywords = {dats},\nmonth = {April},\npages = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C26_paper.pdf},\ntitle = {Interaction and {B}alance of {M}ask {W}rite {T}ime and {D}esign {RET} {S}trategies},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [65]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, and C. -H. Park, &#8220;Improving OPC Quality Via Interactions Within the Design-to-Manufacturing Flow,&#8221; in <span style=\"font-style: italic\">SPIE Photomask and NGL Mask Technology<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_38\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_38_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP3,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H.},\nbooktitle = {{SPIE Photomask and NGL Mask Technology}},\ncategory = {IP3},\nkeywords = {dats},\nmonth = {April},\nnote = {Invited Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP3_paper.pdf},\ntitle = {Improving {OPC} {Q}uality {V}ia {I}nteractions {W}ithin the {D}esign-to-{M}anufacturing {F}low},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [66]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c17.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Performance-Driven OPC for Mask Cost Reduction,&#8221; in <span style=\"font-style: italic\">IEEE International Symposium on Quality Electronic Design<\/span>,  2005, pp. 270-275. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_3\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_3_block\"><pre><code class=\"tex bibtex\">@inproceedings{C17,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{IEEE International Symposium on Quality Electronic Design}},\ncategory = {C17},\nkeywords = {dats},\nmonth = {March},\npages = {270-275},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C17_paper.pdf},\ntitle = {Performance-{D}riven {OPC} for {M}ask {C}ost {R}eduction},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [67]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c22.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, C. -H. Park, K. Samadi, and X. Xu, &#8220;Topography-Aware Optical Proximity Correction for Better DOF margin and CD Control,&#8221; in <span style=\"font-style: italic\">SPIE Photomask and NGL Mask Technology<\/span>,  2005. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_4\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_4_block\"><pre><code class=\"tex bibtex\">@inproceedings{C22,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Samadi, K. and Xu, X. },\nbooktitle = {{SPIE Photomask and NGL Mask Technology}},\ncategory = {C22},\nkeywords = {dats},\nmonth = {January},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C22_paper.pdf},\ntitle = {Topography-{A}ware {O}ptical {P}roximity {C}orrection for {B}etter {DOF} margin and {CD} {C}ontrol},\nyear = {2005}\n}<\/code><\/pre><\/div>   <\/br>          [68]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, C. -H. Park, P. Sharma, D. Sylvester, and J. Yang, &#8220;Joining the Design and Mask Flows for Better and Cheaper Masks,&#8221; in <span style=\"font-style: italic\">SPIE\/BACUS Symposium on Photomask Technology and Management<\/span>,  2004. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_37\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_37_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP2,\nauthor = {Gupta, P. and Kahng, A. B. and Park, C.-H. and Sharma, P. and Sylvester, D. and Yang, J.},\nbooktitle = {{SPIE\/BACUS Symposium on Photomask Technology and Management}},\ncategory = {IP2},\nkeywords = {dats},\nmonth = {September},\nnote = {Invited Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP2_paper.pdf},\ntitle = {Joining the {D}esign and {M}ask {F}lows for {B}etter and {C}heaper {M}asks},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [69]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c16.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Toward a Methodology for Manufacturability Driven Design Rule Exploration,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2004. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_2\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_2_block\"><pre><code class=\"tex bibtex\">@inproceedings{C16,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C16},\nkeywords = {dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C16_paper.pdf},\ntitle = {Toward a {M}ethodology for {M}anufacturability {D}riven {D}esign {R}ule {E}xploration},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [70]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, F. -L. Heng, and M. Lavin, &#8220;Merits of Cellwise Model-Based OPC,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2004. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_0\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_0_block\"><pre><code class=\"tex bibtex\">@inproceedings{C11,\nauthor = {Gupta, P. and Heng, F.-L. and Lavin, M. },\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {C11},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C11_paper.pdf},\ntitle = {Merits of {C}ellwise {M}odel-{B}ased {OPC}},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [71]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, &#8220;Investigation of Performance Metrics for Interconnect Stack Architectures,&#8221; in <span style=\"font-style: italic\">Proc. g SLIP<\/span>,  2004. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_1\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_1_block\"><pre><code class=\"tex bibtex\">@inproceedings{C13,\nauthor = {Gupta, P. and Kahng, A. B. and Kim, Y. and Sylvester, D.},\nbooktitle = {{Proc. g SLIP}},\ncategory = {C13},\nkeywords = {dats},\nmonth = {February},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C13_paper.pdf},\ntitle = {Investigation of {P}erformance {M}etrics for {I}nterconnect {S}tack {A}rchitectures},\nyear = {2004}\n}<\/code><\/pre><\/div>   <\/br>          [72]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/c7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools,&#8221; in <span style=\"font-style: italic\">Proc. ACM\/IEEE Design Automation Conference (DAC)<\/span>,  2003. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_23\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_23_block\"><pre><code class=\"tex bibtex\">@inproceedings{C7,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{Proc. ACM\/IEEE Design Automation Conference (DAC)}},\ncategory = {C7},\nkeywords = {sizing, dats},\nmonth = {June},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C7_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/C7_slides.pdf},\ntitle = {A {C}ost-{D}riven {L}ihographic {C}orrection {M}ethodology {B}ased on {O}ff-the-{S}helf {S}izing {T}ools},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>          [73]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/ip1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/pdf.png' alt=\"[PDF]\"\/><\/a>           P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, &#8220;Toward Performance-Driven Reduction of the Cost of RET-based Lithography Control,&#8221; in <span style=\"font-style: italic\">Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing<\/span>,  2003. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_35\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_35_block\"><pre><code class=\"tex bibtex\">@inproceedings{IP1,\nauthor = {Gupta, P. and Kahng, A. B. and Sylvester, D. and Yang, J.},\nbooktitle = {{Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing}},\ncategory = {IP1},\nkeywords = {dats},\nmonth = {February},\nnote = {Invited Paper},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/IP1_paper.pdf},\ntitle = {Toward {P}erformance-{D}riven {R}eduction of the {C}ost of {RET}-based {L}ithography {C}ontrol},\nyear = {2003}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul> <\/p>\n","protected":false},"excerpt":{"rendered":"<p>The semiconductor industry is likely to see several rad- ical changes in the fabrication and device technologies in the next decade. Each of these technologies&hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":160,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-162","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/162","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=162"}],"version-history":[{"count":4,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/162\/revisions"}],"predecessor-version":[{"id":247,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/162\/revisions\/247"}],"up":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/160"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=162"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}