{"id":145,"date":"2019-10-02T20:56:21","date_gmt":"2019-10-02T20:56:21","guid":{"rendered":"http:\/\/nanocad.ee.ucla.edu\/?page_id=145"},"modified":"2019-11-06T01:33:42","modified_gmt":"2019-11-06T01:33:42","slug":"thesis-and-project-reports","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=145","title":{"rendered":"Thesis and Project Reports"},"content":{"rendered":"\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=145\/#PhD_Theses\" >Ph.D. Theses<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/nanocad.ee.ucla.edu\/?page_id=145\/#MS_ThesesReports\" >M.S. Theses\/Reports<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"PhD_Theses\"><\/span>Ph.D. Theses<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p> <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth14.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Li, &#8220;Architecture, modeling, and optimization of photonic neural network accelerators,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2024. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_5\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_5_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH14,\nauthor = {Li, Shurui},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {},\ntitle = {Architecture, Modeling, and Optimization of Photonic Neural Network Accelerators},\nyear = {2024}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Romaszkan, &#8220;Efficient machine learning acceleration at the edge,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2023. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_3\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_3_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH12,\nauthor = {Romaszkan, Wojciech},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {},\ntitle = {Efficient Machine Learning Acceleration at the Edge},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    T. Li, &#8220;Learned approximate computing for machine learning,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2023. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_4\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_4_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH13,\nauthor = {Li, Tianmu},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {},\ntitle = {Learned Approximate Computing for Machine Learning},\nyear = {2023}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Pal, &#8220;Scale-out packageless processing,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_2\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_2_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH11,\nauthor = {Pal, Saptadeep},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {November},\ntitle = {Scale-Out Packageless Processing},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam, &#8220;Lightweight opportunistic memory resilience,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2021. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_1\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_1_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH10,\nauthor = {Alam, Irina},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\nmonth = {August},\ntitle = {Lightweight Opportunistic Memory Resilience},\nyear = {2021}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    W. Wang, &#8220;Hardware-enabled design for security (dfs) solutions,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2018. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_13\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_13_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH9,\nauthor = {Wang, Wei-Che},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH8_paper.pdf},\ntitle = {Hardware-Enabled Design for Security (DFS) Solutions},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Wang, &#8220;Design, evaluation and co-optimization of emerging devices and circuits,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_10\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_10_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH6,\nauthor = {Wang, Shaodi},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {emerging technology, emerging device, emerging memory, MRAM, TFET, negative differential resistance, optimization, evaluation, stochastic computing, non-volatile memory, memory reliability},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH6_paper.pdf},\ntitle = {Design, Evaluation and Co-optimization of Emerging Devices and Circuits},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/phdth7_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            M. W. Gottscho, &#8220;Opportunistic memory systems in presence of hardware variability,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_11\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_11_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH7,\nauthor = {Gottscho, Mark William},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {computer architecture, memory systems, variation-aware, hardware\/software interface, reliability, error-correcting codes, caches, scratchpads, SRAM, DRAM, supercomputers, IoT, embedded systems, electronic design auomation, CAD, EDA, operating systems, Linux, tools, benchmarks, resiliency, approximate computing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH7_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH7_slides.pdf},\ntitle = {Opportunistic Memory Systems in Presence of Hardware Variability},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [9]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Badr, &#8220;Co-optimization of restrictive patterning technologies and design,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_12\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_12_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH8,\nauthor = {Badr, Yasmine},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH8_paper.pdf},\ntitle = {Co-optimization of Restrictive Patterning Technologies and Design},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [10]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Lai, &#8220;Cross-layer approaches for monitoring, margining and mitigation of circuit variability,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2015. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_9\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_9_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH5,\nauthor = {Lai, Liangzhen},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH5_paper.pdf},\ntitle = {Cross-Layer Approaches for Monitoring, Margining and Mitigation of Circuit Variability},\nyear = {2015}\n}<\/code><\/pre><\/div>   <\/br>          [11]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. A. Kagalwalla, &#8220;Computational methods for design-assisted mask flows,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_8\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_8_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH4,\nauthor = {Kagalwalla, Abde Ali},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH4_paper.pdf},\ntitle = {Computational Methods for Design-Assisted Mask Flows},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Lee, &#8220;Implications of modern semiconductor technologies on gate sizing,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_6\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_6_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH2,\nauthor = {Lee, John},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH2_paper.pdf},\ntitle = {Implications of Modern Semiconductor Technologies on Gate Sizing},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    R. S. Ghaida, &#8220;Design enablement and design-centric assessment of future semiconductor technologies,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles, 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_7\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_7_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH3,\nauthor = {Ghaida, R. S.},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {dats},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH3_paper.pdf},\ntitle = {Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/phdth1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    L. Cheng, &#8220;Statistical analysis and optimization for timing and power of vlsi circuits,&#8221; PhD Thesis, 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_0\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_0_block\"><pre><code class=\"tex bibtex\">@phdthesis{PHDTH1,\nauthor = {Cheng, Lerong},\ncategory = {PT1},\nkeywords = {stat},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/PHDTH1_paper.pdf},\nschool = {Department of Electrical Engineering, University of California Los Angeles },\ntitle = {Statistical Analysis and Optimization for Timing and Power of VLSI Circuits},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>  <\/p>\n\n\n\n<hr class=\"wp-block-separator is-style-wide\"\/>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"MS_ThesesReports\"><\/span>M.S. Theses\/Reports<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>  <ul class=\"papercite_bibliography\">          [1]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth6.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Wu, &#8220;Pin assignment for 2.5d dielet assembly,&#8221; Department of Electrical and Computer Engineering, University of California Los Angeles 2019. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_19\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_19_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH6,\nauthor = {Wu, Yizhang},\ninstitution = {Department of Electrical and Computer Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH6_paper.pdf},\ntitle = {Pin Assignment for 2.5D Dielet Assembly},\nyear = {2019}\n}<\/code><\/pre><\/div>   <\/br>          [2]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    I. Alam, &#8220;Lightweight fault tolerance in sram based on-chip memories,&#8221; Department of Electrical and Computer Engineering, University of California Los Angeles 2018. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_17\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_17_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH4,\nauthor = {Alam, Irina},\ninstitution = {Department of Electrical and Computer Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH4_paper.pdf},\ntitle = {Lightweight Fault Tolerance in SRAM Based On-Chip Memories},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [3]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth5.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    Y. Chae, &#8220;Defect avoidance for extreme ultraviolet mask defects using intentional pattern deformation,&#8221; Department of Electrical and Computer Engineering, University of California Los Angeles 2018. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_18\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_18_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH5,\nauthor = {Chae, Yoo-Jin},\ninstitution = {Department of Electrical and Computer Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH5_paper.pdf},\ntitle = {Defect Avoidance for Extreme Ultraviolet Mask Defects using Intentional Pattern Deformation},\nyear = {2018}\n}<\/code><\/pre><\/div>   <\/br>          [4]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr12.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/mstr12_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            V. Dokania, &#8220;Intrusive routing for improved standard cell pin access,&#8221; Department of Electrical Engineering, University of California Los Angeles 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_23\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_23_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR12,\nauthor = {Dokania, Vishesh },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR12_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR12_slides.pdf},\ntitle = {Intrusive Routing for Improved Standard Cell Pin Access},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [5]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr13.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/mstr13_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            S. Pal, &#8220;Supervia: relieving routing congestion using double-height vias,&#8221; Department of Electrical Engineering, University of California Los Angeles 2017. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_24\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_24_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR13,\nauthor = {Pal, Saptadeep},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR13_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR13_slides.pdf},\ntitle = {Supervia: Relieving Routing Congestion using Double-height Vias},\nyear = {2017}\n}<\/code><\/pre><\/div>   <\/br>          [6]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr11.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/mstr11_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            N. Lyu, &#8220;Leon3 processor variability emulator for delay variability impact on performance,&#8221; Department of Electrical Engineering, University of California Los Angeles 2016. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_22\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_22_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR11,\nauthor = {Lyu, Nan},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR11_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR11_slides.pdf},\ntitle = {Leon3 Processor Variability Emulator for Delay Variability Impact on Performance},\nyear = {2016}\n}<\/code><\/pre><\/div>   <\/br>          [7]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr10.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>    <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/ppt\/mstr10_slides.pdf\" title='Download Slides' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_powerpoint_272700.svg'  height=\"16\" width=\"16\" alt=\"[PDF Slides]\"\/><\/a>            M. Gottscho, &#8220;ViPZonE: Exploiting DRAM Power Variability for Energy Savings in Linux x86-64,&#8221; Department of Electrical Engineering, University of California Los Angeles 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_21\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_21_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR10,\nauthor = {Gottscho, Mark},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR10_paper.pdf},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR10_slides.pdf},\ntitle = {{V}i{P}{Z}on{E}: {E}xploiting {DRAM} {P}ower {V}ariability for {E}nergy {S}avings in {L}inux x86-64},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [8]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr9.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Bhatia, &#8220;Varleon: fpga based processor variability emulator for variation aware software,&#8221; Department of Electrical Engineering, University of California Los Angeles 2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_32\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_32_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR9,\nauthor = {Bhatia, Abishek},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR9_paper.pdf},\ntitle = {VarLEON: FPGA Based Processor Variability Emulator for Variation Aware Software},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [9]                            Y. Agarwal, A. Bishop, T. Chan, M. Fotjik, P. Gupta, A. Kahng, L. Lai, P. Martin, M. Srivastava, D. Sylvester, L. Wanner, and B. Zhang, &#8220;Redcooper: hardware sensor enabled variability software testbed for lifetime energy constrained application,&#8221;  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_33\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_33_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP1,\nauthor = {Agarwal, Yuvraj and Bishop, Alex and Chan, Tuck-Boon and Fotjik, Matt and Gupta, Puneet and Kahng, Andrew and Lai, Liangzhen and Martin, Paul and Srivastava, Mani and Sylvester, Dennis and Wanner, Lucas and Zhang, Bing},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/1c21g217},\ntitle = {Redcooper: Hardware sensor enabled variability software testbed for lifetime energy constrained application},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [10]                            L. Lai, C. Chang, and P. Gupta, &#8220;Exploring total power saving from high temperature of server operations,&#8221;  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_34\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_34_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP2,\nauthor = {Lai, Liangzhen and Chang, Chia-Hao and Gupta, Puneet},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/5898p020},\ntitle = {Exploring Total Power Saving from High Temperature of Server Operations},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [11]                            L. Lai and P. Gupta, &#8220;A case study of logic delay fault behaviors on general-purpose embedded processor under voltage overscaling,&#8221;  2014. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_35\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_35_block\"><pre><code class=\"tex bibtex\">@techreport{TECHRP3,\nauthor = {Lai, Liangzhen and Gupta, Puneet},\nkeywords = {techreport, hsi},\npaperurl = {http:\/\/www.escholarship.org\/uc\/item\/3967v8hw},\ntitle = {A Case Study of Logic Delay Fault Behaviors on General-Purpose Embedded Processor Under Voltage Overscaling},\nyear = {2014}\n}<\/code><\/pre><\/div>   <\/br>          [12]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Sharma, &#8220;Understanding software application behaviour in presence of permanent and intermittent hardware faults,&#8221; Department of Electrical Engineering, University of California Los Angeles 2013. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_16\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_16_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH3,\nauthor = {Sharma, Ankur},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH3_paper.pdf},\ntitle = {Understanding Software Application Behaviour in Presence of Permanent and Intermittent Hardware Faults},\nyear = {2013}\n}<\/code><\/pre><\/div>   <\/br>          [13]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr7.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    J. Dong, &#8220;High Level Battery Modeling Considering Discharge Rate and Temperature Effects,&#8221; Department of Electrical Engineering, University of California Los Angeles 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_30\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_30_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR7,\nauthor = {Dong, Jingyuan},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR7_paper.pdf},\ntitle = {{High Level Battery Modeling Considering Discharge Rate and Temperature Effects}},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [14]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr8.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    N. Jin, &#8220;Modelling of guardband reduction on design area,&#8221; Department of Electrical Engineering, University of California Los Angeles 2012. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_31\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_31_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR8,\nauthor = {Jin, Ning},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {mad, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR8_paper.pdf},\ntitle = {Modelling of Guardband Reduction on Design Area},\nyear = {2012}\n}<\/code><\/pre><\/div>   <\/br>          [15]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. A. Kagalwalla, &#8220;Design-aware mask manufacturing,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_15\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_15_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH2,\nauthor = {Kagalwalla, Abde Ali},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH2_paper.pdf},\ntitle = {Design-Aware Mask Manufacturing},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [16]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr4.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    S. Mok, &#8220;Post-Layout Sizing for Leakage Power Optimization: A Comparative Study,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_27\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_27_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR4,\nauthor = {Mok, Santiago},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR4_paper.pdf},\ntitle = {{Post-Layout Sizing for Leakage Power Optimization: A Comparative Study}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [17]                            C. Apte, &#8220;Power Consumption Variability in Embedded Processors,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_28\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_28_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR5,\nauthor = {Apte, Charwak},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR5_paper.pdf},\ntitle = {{Power Consumption Variability in Embedded\nProcessors}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [18]                            P. Kulkarni, &#8220;Trading Accuracy for Power with an Under-designed Multiplier Architecture,&#8221; Department of Electrical Engineering, University of California Los Angeles 2011. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_29\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_29_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR6,\nauthor = {Kulkarni, Parag },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {hsi, msreport},\nslideurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR6_paper.pdf},\ntitle = {{Trading Accuracy for Power with an Under-designed\nMultiplier Architecture}},\nyear = {2011}\n}<\/code><\/pre><\/div>   <\/br>          [19]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/msth1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Pant, &#8220;Hardware-software interface in the presence of hardware manufacturing variations,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_14\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_14_block\"><pre><code class=\"tex bibtex\">@techreport{MSTH1,\nauthor = {Pant, Aashish },\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {thesis},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTH1_paper.pdf},\ntitle = {Hardware-Software Interface in the Presence of Hardware Manufacturing Variations},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [20]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr2.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    D. Reinhard, &#8220;On Comparing Conventional and Electrically Driven OPC Techniques,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_25\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_25_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR2,\nauthor = {Reinhard, Dominic},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {mad. msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR2_paper.pdf},\ntitle = {{On Comparing Conventional and Electrically Driven OPC Techniques}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [21]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr3.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    A. Kasibhatla, &#8220;Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,&#8221; Department of Electrical Engineering, University of California Los Angeles 2010. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_26\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_26_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR3,\nauthor = {Kasibhatla, Amarnath},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR3_paper.pdf},\ntitle = {{Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics}},\nyear = {2010}\n}<\/code><\/pre><\/div>   <\/br>          [22]         <a href=\"https:\/\/nanocad.ee.ucla.edu\/wp-content\/papercite-data\/pdf\/mstr1.pdf\" title='Download PDF' class='papercite_pdf'><img src='https:\/\/nanocad.ee.ucla.edu\/wp-content\/plugins\/papercite\/img\/iconfinder_pdf_272699.svg' height=\"16\" width=\"16\" alt=\"[PDF]\"\/><\/a>                    V. Popuri, &#8220;Bias-driven Robust Analog Circuit Sizing Scheme,&#8221; Department of Electrical Engineering, University of California Los Angeles 2009. <br\/>    <a href=\"javascript:void(0)\" id=\"papercite_20\" class=\"papercite_toggle\">[Bibtex]<\/a>    <div class=\"papercite_bibtex\" id=\"papercite_20_block\"><pre><code class=\"tex bibtex\">@techreport{MSTR1,\nauthor = {Popuri, Viswakiran},\ninstitution = {Department of Electrical Engineering, University of California Los Angeles},\nkeywords = {sizing, msreport},\npaperurl = {http:\/\/nanocad.ee.ucla.edu\/pub\/Main\/Publications\/MSTR1_paper.pdf},\ntitle = {{Bias-driven Robust Analog Circuit Sizing Scheme}},\nyear = {2009}\n}<\/code><\/pre><\/div>   <\/br>           <\/ul>   <\/p>\n","protected":false},"excerpt":{"rendered":"<p>Ph.D. Theses [1] S. Li, &#8220;Architecture, modeling, and optimization of photonic neural network accelerators,&#8221; PhD Thesis, Department of Electrical Engineering, University of California Los Angeles,&hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":56,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-145","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/145","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=145"}],"version-history":[{"count":6,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/145\/revisions"}],"predecessor-version":[{"id":349,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/145\/revisions\/349"}],"up":[{"embeddable":true,"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=\/wp\/v2\/pages\/56"}],"wp:attachment":[{"href":"https:\/\/nanocad.ee.ucla.edu\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=145"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}