{"id":1307,"date":"2025-04-28T21:22:09","date_gmt":"2025-04-28T21:22:09","guid":{"rendered":"https:\/\/nanocad.ee.ucla.edu\/?page_id=1307"},"modified":"2025-06-22T05:35:56","modified_gmt":"2025-06-22T05:35:56","slug":"chico-workshop-2025","status":"publish","type":"page","link":"https:\/\/nanocad.ee.ucla.edu\/?page_id=1307","title":{"rendered":"CHICO Workshop 2025"},"content":{"rendered":"\n
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CHICO 2025 <\/mark><\/strong><\/p>\n\n\n\n

Workshop on Chiplet-based Heterogeneous Integration and CO-design<\/bdo><\/strong><\/p>\n<\/div>\n\n\n\n

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June 22, 2025
Moscone Center
San Francisco, CA<\/strong><\/p>\n<\/div>\n\n\n\n

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Contemporary microelectronic design is facing tremendous challenges in memory bandwidth, processing speed, and power consumption. Although recent advances in monolithic design (e.g. near-memory and in-memory computing) help relieve some issues, the scaling trend is still lagging behind the ever increasing demand of AI, HPC and other applications.<\/p>\n\n\n\n

In this context, technological innovations beyond a monolithic chip, such as 2.5D and 3D packaging at the macro and micro levels, are critical to enabling heterogeneous integration with various types of chiplets, and bringing significant performance and cost benefits for future systems. Such a paradigm shift further drives new innovations on chiplet IPs, heterogeneous architectures, and system mapping.<\/p>\n<\/div>\n\n\n\n

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Organizers<\/strong><\/p>\n\n\n\n

Yu (Kevin) Cao, University of Minnesota Twin Cities<\/p>\n\n\n\n

Puneet Gupta, University of California, Los Angeles