#This file contains the values of design rules which needs to be given to the tool. Refer to /doc/DRE-SupportedRules.pdf for description of these rules. The exact order of the DRs and the syntax must be followed. All design rules are in [nm] unit. Layout styles are binary (1 for true, 0 for false). See the tutorial for help. NOTE ALL FIELD POLY RULES ARE EQUIVALENT TO CB RULES. BE CAREFULL, some rules are interdependent and must be modified together. For example, if you change CB.LW.1, you must update CT.W.2 so that CT.W.2 = CB.LW.1 + 2 x CT.EX.CB.2. IMPORTANT: for metal, width in Y direction is width in VERTICAL direction, while spacing in Y direction is spacing in HORIZONTAL direction (which is spacing between lines in vertical directions).
1.1.1	CA.W.1 - Min diff-width (for routing of diffusion power-straps).......... = 65
1.1.2a  RX.W.1 - Min transistor width (also min fin pitch)....................... = 80 
1.1.2b  RXFIN.S.1 - Min fin space (may be different than active fins spacing).... = 60
1.1.2c  RXFIN.S.2 - Max fin space (may be different than active fins spacing).... = 90
1.1.2d  RXFIN.S.3 - Step for increments over min space for allowed fin spacing... = 1
1.1.2e  RXFIN.H - Fin height..................................................... = 50
1.1.2f  RXFIN.C - Bulk to FinFET W conversion parameter.......................... = 2
1.1.3   RXFIN.W.1 - Fin width (exact)............................................ = 20
1.1.4   RX.EX.RXFIN.1 - Diffusion overlap past active fin........................ = 20
1.1.5   NW.W.1 - Min n-well width................................................ = 200
1.1.6   PC.EX.RX.1 - Poly overlap past diffusion (for dummy poly at diff-edge)... = 25
1.2.1	RX.S.1 - Diff-to-diff spacing same network............................... = 215
1.2.2	RX.S.2 - Diff-to-diff spacing p/n network................................ = 140
1.3.1   CA.S.1 - CA tip to tip spacing........................................... = 75
1.3.2   CA.OL.CB.1 - Minimum overlap of CA with CB............................... = 20
1.3.3   CA.EX.RX.1 - CA extension past RX........................................ = 0
2.1.1	PC.W.1 - Gate poly width................................................. = 50
2.1.2	CB.LW.1 - Field poly width (same as wrong way poly)...................... = 65
2.2.1	PC.S.1 - Gate poly spacing (side to side)................................ = 165
2.2.2	Fixed Gate pitch (i.e. PC.S.1 + PC.W.1 if poly on pitch scheme).......... = 215
2.2.3	CB.S.1 - Field poly spacing (side to side, same as wrong way poly)....... = 75 
2.2.4	CT.EX.CB.2 - Gate poly line-end to field poly side....................... = 75 
2.2.5	CT.W.2 - Gate poly line-end gap (tip to tip)............................. = 75
2.3.1	CA.S.PC.1 - Gate poly-to-diff spacing.................................... = 50
2.3.2   PC.S.RX.1 - Poly tip to diffusion side spacing........................... = 50
2.4.1	CA.S.PC.1 - Gate poly-to-contact spacing in X direction.................. = 50
2.4.2   CB.S.PC.2 - Poly-to-contact spacing in Y direction....................... = 75
2.5.1	PC.EX.RX.1 - Gate poly line-end extension................................ = 55
2.5.2   CT.S.CB.2 - Poly extension over wrong-way poly........................... = 20
2.5.3a  CB.EX.PC.1 - Wrong-way poly extension over poly.......................... = 10
2.5.3b  CB.EX.PC.2 - Wrong-way poly end extension over poly...................... = 10
2.6	MAX (CB.S.CA.1 + CA.EX.RX.1, CB.S.RX.1) - Field poly-to-diff spacing..... = 50
2.7	Diffusion extension of gate (i.e. PC.S.1 + PC.W.1 / 2)................... = 190
3.1	V0.LW.1 - Contact width.................................................. = 65
3.2a	V0.S.2 - Contact spacing (edge-to-edge).................................. = 75
3.2b    V0.S.1 - Redundant contact spacing (edge-to-edge)........................ = 75
3.3.1	V0.EN.CA.1 - Contact enclosure within diff (all sides)................... = 5
3.3.2   V0.EN.CB.1 - Contact enclosure within CB (all sides)..................... = 0
3.4	Contact enclosure within poly (all sides)................................ = 5
3.5	V0.S.CA.1 + CA.EX.RX.1 - Contact to diffusion spacing (edge-to-edge)..... = 55 
4.1     Number of metal layers................................................... = 2
4.1.1   M1.W.1 - M1 width in X direction......................................... = 65
4.1.2   M1.W.2 - M1 width in Y direction......................................... = 65
4.2.1.1 M1.S.1 - M1 spacing (side to side) in X direction........................ = 65
4.2.1.2 M1.S.2 - M1 spacing (side to side) in Y directio......................... = 65
4.2.2.1	M1.S.4 - M1 spacing (tip to side) in X direction......................... = 65
4.2.2.2	M1.S.4 - M1 spacing (tip to side) in Y direction......................... = 65
4.2.3.1	M1 spacing (tip to tip) in X direction................................... = 65
4.2.3.2	M1 spacing (tip to tip) in Y direction................................... = 65
4.2.4.1	M1.S.4 - M1 spacing (L-bend to outer line-tip) in X direction............ = 65
4.2.4.2	M1.S.4 - M1 spacing (L-bend to outer line-tip) in Y direction............ = 65
4.2.5.1	M1.S.4 - M1 spacing (L-bend to inner line-tip) in X direction............ = 65
4.2.5.2	M1.S.4 - M1 spacing (L-bend to inner line-tip) in Y direction............ = 65
4.2.6.1	M1.S.1 - M1 spacing (L-bend to outer line-side) in X direction........... = 65
4.2.6.2	M1.S.2 - M1 spacing (L-bend to outer line-side) in Y direction........... = 65
4.2.7.1	M1.S.4 - M1 spacing (T-bend to outer line-tip) in X direction............ = 65
4.2.7.2	M1.S.4 - M1 spacing (T-bend to outer line-tip) in Y direction............ = 65
4.2.8.1	M1.S.4 - M1 spacing (T-bend to inner line-tip) in X direction............ = 65
4.2.8.2	M1.S.4 - M1 spacing (T-bend to inner line-tip) in Y direction............ = 65
4.2.9.1	M1.S.1 - M1 spacing (T-bend to outer line-side) in X direction........... = 65
4.2.9.2	M1.S.2 - M1 spacing (T-bend to outer line-side) in Y direction........... = 65
4.2.10.1 M1.S.1 - M1 spacing (T-bend to T-bend) in X direction................... = 65
4.2.10.2 M1.S.2 - M1 spacing (T-bend to T-bend) in Y direction................... = 65
4.2.11.1 M1.S.1 - M1 spacing (L-bend to inner L-bend) in X direction............. = 65
4.2.11.2 M1.S.2 - M1 spacing (L-bend to inner L-bend) in Y direction............. = 65
4.2.12.1 M1.S.1 - M1 spacing (L-bend to outer L-bend) in X direction............. = 65
4.2.12.2 M1.S.2 - M1 spacing (L-bend to outer L-bend) in Y direction............. = 65
4.2.13.1 M1.S.1 - M1 spacing (T-bend to inner L-bend) in X direction............. = 65
4.2.13.2 M1.S.2 - M1 spacing (T-bend to inner L-bend) in Y direction............. = 65
4.2.14.1 M1.S.1 - M1 spacing (T-bend to outer L-bend) in X direction............. = 65
4.2.14.2 M1.S.2 - M1 spacing (T-bend to outer L-bend) in Y direction............. = 65
4.2.15.1 M1.S.4 - M1 spacing (cross to inner line-tip) in X direction............ = 65
4.2.15.2 M1.S.4 - M1 spacing (cross to inner line-tip) in Y direction............ = 65
4.2.16 M1 spacing with M1 power rail............................................. = 65
4.2.17 M1 spacing with wide I/O pin pads in X direction.......................... = 65
4.2.18 M1 spacing with wide I/O pin pads in Y direction.......................... = 65
4.3.1.1	M1.EX.V0.1.OR.a - M1 overhang over diff-contact 1st 2 sides in X drction. = 35
4.3.1.2	M1.EX.V0.1.OR.b - M1 overhang over diff-contact 1st 2 sides in Y drction. = 35
4.3.2.1	M1.EX.V0.1.OR.a OPPOSITE - M1 ovrhng over diff-CA 2nd 2 sides in X....... = 0
4.3.2.2	M1.EX.V0.1.OR.b OPPOSITE - M1 ovrhng over diff-CA 2nd 2 sides in Y....... = 0
4.3.3.1	M1.EX.V0.1.OR.a - M1 overhang over poly-contact 1st 2 sides in X drction. = 35
4.3.3.2	M1.EX.V0.1.OR.b - M1 overhang over poly-contact 1st 2 sides in Y drction. = 35
4.3.4.1	M1.EX.V0.1.OR.a OPPOSITE - M1 overhang over poly-contact 2nd 2 sides in X = 0
4.3.4.2	M1.EX.V0.1.OR.b OPPOSITE - M1 overhang over poly-contact 2nd 2 sides in Y = 0
4.4.1   M1 strict or preferred direction (1 for vertical, 0 for horizontal)...... = 0
4.4.3   M1 max wrong direction jog (-1->2D, 0->1D, otherwise->max jog length).... = -1
4.5.1   M1.A.1a / M1.W.1 - M1 minimum metal length in X direction................ = 0
4.5.2   M1.A.1b / M1.W.2 - M1 minimum metal length in Y direction................ = 0
5.1     M2 maximum utilization (fraction of available)........................... = 0.2
5.1.3   Mx.W.1 - M2 width in X direction......................................... = 70
5.1.4   Mx.W.1 - M2 width in Y direction......................................... = 70
5.2.1.3 Mx.S.1 - M2 spacing (side to side) in X direction........................ = 70
5.2.1.4 Mx.S.1 - M2 spacing (side to side) in Y direction........................ = 70
5.2.3.1 Mx.S.4a - M2 spacing (tip to tip) in X direction......................... = 70
5.2.3.2 Mx.S.4a - M2 spacing (tip to tip) in Y direction......................... = 70
5.2.4.1 Mx.S.4 - M2 spacing (tip to side) in Y direction......................... = 70
5.4.2   M2 strict or preferred direction (1 for vertical, 0 for horizontal)...... = 0
5.4.4   M2 max wrong direction jog (-1->2D, 0->1D, otherwise->max jog length).... = 0
5.5.3   Mx.A.1a / Mx.W.1 - M2 minimum metal length in X direction................ = 70
5.5.4   Mx.A.1a / Mx.W.1 - M2 minimum metal length in Y direction................ = 70
5.6.1   Mx.S.1 - M2 spacing with M2 power rail................................... = 70
6.1.1   Vx.LW.1 - Via 1 width.................................................... = 65
6.2.1   Mx.Ex.Vy.1 - Via 1 enclosure within M1 first 2 sides..................... = 35
6.2.2   Mx.Ex.Vx.1 - Via 1 enclosure within M2 first 2 sides..................... = 35
6.3.1   Via 1 enclosure within M1 second 2 sides (< or equal to previous)........ = 0
6.3.2   Via 1 enclosure within M2 second 2 sides (< or equal to previous)........ = 0
6.4.1   Vx.S.Mx.4 - Via 1 to M1 spacing.......................................... = 65
6.4.2   Via 1 spacing (side to side, must be > or eq 6.4.1) (Vx.S.1 - Vx.LW.1)... = 65
7.1.1   Vdd power-rail width on M1............................................... = 170
7.1.2   GND power-rail width on M1............................................... = 170
7.1.3   Vdd power-rail width on M2............................................... = 0
7.1.4   GND power-rail width on M2............................................... = 0
7.1.5   Vdd power-rail width on field poly....................................... = 80
7.1.6   GND power-rail width on field poly....................................... = 80
7.1.7   Vdd power-rail width on diffusion........................................ = 0
7.1.8   GND power-rail width on diffusion........................................ = 0
7.1.9   Non-shared power rail on top of diffusion (1 for true, 0 for false)...... = 0
7.2a    Given exact cell height (1 for true, 0 for false)........................ = 0
7.2b    Cell-height in [nm] (considered only if 7.2a is true).................... = 1400
7.2c    Cell-height in numb of metal tracks(considered only if 7.2a false)....... = 11
7.3.1   Cell unit-width.......................................................... = 215
7.3.2   M1 min spacing with cell side (> or equal to tip to side spacing / 2).... = 33
7.4.1   Cell-I/O M1 width in X direction (for pin access requirement)............ = 65
7.4.2   Cell-I/O M1 width in Y direction (for pin access requirement)............ = 65
8.1.1   Fixed gate-pitch (1 for true, 0 for false)............................... = 1
8.1.2   1D-poly (1 for true, 0 for false)........................................ = 0
8.1.3   Limited poly routing (1 for true, 0 for false)........................... = 0
8.1.4   Field poly with a separate layer (CB layer).............................. = 1
8.1.5   Multiple fin spacing..................................................... = 1
8.1.6   Poly diffusion tuck under................................................ = 1
8.2.1   Power-straps    (1 for diffusion, 0 for M1).............................. = 1
8.2.2   Power straps with CA instead of diffusion (just to draw CA layer)........ = 1
8.2.3   Extend power straps till end of cell..................................... = 1
8.2.4   No need for CA for single-finger devices................................. = 1
8.2.5   No need for CA stacked devices........................................... = 1
8.3.1   PMOS vertical location(0->top,1->mid,2->p/n interface)................... = 0
8.3.2   NMOS vertical location(0->bot,1->mid,2->p/n interface)................... = 0
8.4     Poly line-end extension span cell-height (1 for true, 0 for false)....... = 1
8.5     Discrete cell width (1 for true, 0 for false)............................ = 1
8.6     Redundant contacts test (see tutorial for details)....................... = 0
8.6.1   Diff-contact redundancy (enter min number of contacts, at least 1)....... = 1
8.6.2   Poly-contact redundancy (enter min number of contacts, at least 1)....... = 1
8.7.1   Input pin access requirement on M1 (0->min size,1->pad,2->vertical wire). = 0
8.7.2   Output pin access requirement on M1 (0->min size,1->pad,2->vertical wire) = 0
8.8.1   CA routing from nmos to pmos (only straight vertical connections)........ = 0
8.9.1   V0 connects directly to poly (CB needed to connect to PC)................ = 0
8.9.2   Trench contacts.......................................................... = 1
9.1.1   Allow pairing of trans with different gate signals (imperfect pairing)... = 0
9.1.2   Allow poly cross coupling (special case of imperfect pairing)............ = 1
10.1.1  FinFET or MOSFET (0 for MOSFET, 1 for FinFET)............................ = 1
10.1.2  Tapered devices (0->forbidden,1->allowed,2--> allowed w/ W increase)..... = 1
11.1.1  Cell boundary (0->at half poly space, 1->at center of poly line)......... = 0
11.1.2  Importance of placing power straps at cell boundary (w.r.t. abutment).... = 0
11.2    No contacts in power rail (no V0)........................................ = 1
11.3    Pins on M1/M2 layers (0->on M1, 1->on M2, 2->on either).................. = 2
11.4    Vertical metal on track.................................................. = 0
11.5    Maximize pin length...................................................... = 0 
Grid size [nm]................................................................... = 1
Overlay (3sigma) [nm]............................................................ = 1
CDU (3sigma, gate CD control) [nm]............................................... = 1.9
Line-end pull-back (mean) (added to mean of overlay) [nm]........................ = 1
Defect density, D0[faults/m2].................................................... = 1395
Critical (peak) defect size, r0.................................................. = 10
Maximum defect size, rmax........................................................ = 250
Fab cleanliness parameter, n..................................................... = 3
Diffusion contact-hole failure rate [ppm]........................................ = 0.00004
Poly contact-hole failure rate [ppm]............................................. = 0.00004
Critical M1 width [nm]........................................................... = 20
Critical Poly width [nm]......................................................... = 20
Critical Contact width [nm]...................................................... = 20
Tapering parameter n............................................................. = 3
Tapering parameter k............................................................. = 0
Lib Scaling factor............................................................... = 1
1D poly CD 3sigma improvement over 2D-poly....................................... = 0
Fixed pitch poly 3sigma improvement over 2D-poly................................. = 0
PMOS to NMOS optimal or desired width ratio...................................... = 1
Clustering parameter (alpha) for negative binomial yield model................... = 2
