#netlist format. currently supported formats are "spice" and "asx"
netlist_format : spice 

#power supply name in netlist. In case it is not specified, it will be set to name of bulk terminal. 
vdd_name : vdd

#Ground name in netlist. In case it is not specified, it will be set to name of bulk terminal. 
gnd_name : vss

#power supply second name in netlist (useful when there is 2 power supply names in the same netlist).
vdd_second_name : vddg

#Ground second name in netlist (useful when there is 2 power supply names in the same netlist).
gnd_second_name : gnd

#PMOS device model name. Needed only if model is different than pmos, cmosp, and pmos_vtl in order to distinguish device type in SPICE netlist (not needed for ASX format).
pmos_model : pmos_vtl

#NMOS device model name. Needed only if model is different than nmos, cmosn, and nmos_vtl in order to distinguish device type in SPICE netlist (not needed for ASX format).
nmos_model : nmos_vtl

#PMOS terminal order of appearance in the netlist device model (starting with 1 for first terminal). If using SPICE format the default order is D-G-S-B and there's no need to specify the order (but needed for ASX format). 
pmos_drain_order : 1
pmos_gate_order : 2
pmos_source_order : 3
pmos_bulk_order : 4
nmos_drain_order : 1
nmos_gate_order : 2
nmos_source_order : 3
nmos_bulk_order : 4

#unit used for gate length and width in netlist. Only um and nm are supported. Default is um.
unit : m 

#maximum number of iterations for chaining algorithm. In practice, 8 iterations lead to the optimal solution in almost every case. If this is not the case for a particular cell and runtime is tolerable, this value can be increased.
chaining_it : 28

#max number of pairs for increasing chaining iterations
max_pairs_chaining_it_increase : 10

#max chaining it increase
max_chaining_it_increase : 600

#number of folds that one transistor needs to have to decide to cluster its folds into groups and deal with each group as a stand-alone transistor pair (see /doc/iccad09_presentation.ppt for explanation of the method).
num_folds_to_split : 6

#number of clusters per folded transistor pair
num_splits_per_pair : 2

#max number of chains for running exhaustive placement of chains
max_chains_exhaustive_placement : 9

#alpha and beta parameters for modeling intra-cell routing efficiency and gamma parameter to model I/O pin-access requirement(details in /doc/Pub_Full_8pages.pdf section II-C). Current values are based on Nangate open-cell library. Automated method to estimate these parameters based on cells under test will be provided later on. Please do not modify the following values for now. 

#Gamma parameter for considering pin access in congestion 
gamma : 0

#Alpha parameter for vertical congestion 
alpha_v : 0.77

#Beta parameter for vertical congestion
beta_v : 0.3

#Alpha parameter for horizontal congestion 
alpha_h : 0.8

#Beta parameter for horizontal congestion 
beta_h : 0.4

#Path to the base line.lib file
Liberty_File_Path : /w/design/puneet/projects/YasmineBadr/Work/NingWorkReplication/library/NangateOpenCellLibrary_typical_conditional_nldm.lib

#Baseline chip area in um2
Baseline_Chip_Area : 33650

#parameter1 for Cell-area to Chip-area model(fitted for mips)
X0 : 12000

#parameter2 for Cell-area to Chip-area model(fitted for mips)
Y0 : 19571

#Wafer area in mm2
Wafer_Area : 70685

#Flag to use variability to determine worst case delay or not
Use_Var_Delay : 1

#Number of cores per die, for yield and chip area calculation (see tutorial)
N_Cores_Per_Die : 1

