WHAT'S NEW IN UCLA_DRE version 1.7
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I- Support FVGAA and RVGAA generation
II- Design rules updates given below:
1.1.4b  RX.EX.RXVGAA.1 - Diffusion overlap past active VGAA................... = 20
1.1.7	VA.W - Vertical Gate-All-Around(VGAA) pillar width.................... = 45
2.8.1	RPC.S.1 - RVGAA gate poly spacing (no contact)........................ = 100
2.8.2	RPC.S.2 - RVGAA gate poly spacing (with contact)...................... = 250
3.2		V0.S.3 - VGAA spacing (edge-to-edge).................................. = 75
9.2		Allow symmetric architecture(0->no stack;1->has stack).................= 1
10.1.1  VGAA or FinFET or MOSFET (0 for MOSFET, 1 for FinFET, 2 for VGAA)..... = 1
10.1.3  VGAA Type (0 for FVGAA, 1 for RVGAA).................................. = 0

(Note that this release doesn't contain the chip-DRE work. Chip-DRE is release 1.5, but you can use this version of DRE instead of the DRE1.4.2 enclosed in Chip-DRE (1.5).)
