
WHAT IS UCLA_DRE?
=================
UCLA_DRE is a tool written in C++ for evaluating and exploring design rules (DRs) and layout styles in standard-cell based designs.

The tool takes a transistor netlist, design rules, and estimates of process control parameters as input and evaluates cell-area, manufacturability, and variability of the entire design. It also displays evaluation results and layout information of every cell in the design separately.


AUTHOR
======
Rani S. Ghaida, UCLA
Graduate Student Researcher
NanoCAD Lab, Eng IV, 53-109 
Electrical Engineering Department
University of California, Los Angeles
Phone: (310) 825 - 7154
http://www.ee.ucla.edu/~rani
email:rani@ee.ucla.edu

Wei-Che Wang, UCLA
Graduate Student Researcher
NanoCAD Lab, Eng IV, 53-109 
Electrical Engineering Department
University of California, Los Angeles
email:weichewang@ucla.edu


PROJECT DIRECTOR
================
Puneet Gupta, UCLA
Associate Professor
6730C, Boelter Hall,
Box 951594, UCLA,
Los Angeles CA 90095-1594
Phone: (310) 825 - 1376
http://www.ee.ucla.edu/~puneet
email:puneet@ee.ucla.edu


COPYRIGHT NOTICE 
================
Copyright 2009 The Regents of the University of California
All Rights Reserved
Created by Rani S. Ghaida
Electrical Engineering Department, UCLA 


DISCLAIMER
==========
This software is provided "As Is" and without any express or implied
warranties. Neither the authors nor any of their employers (including
any of their subsidiaries and subdivisions) are responsible for maintaining
or supporting this software or for any consequences resulting from the
use of this software even if they arise from flaws in the software.


LICENSE
=======
See file LICENSE in UCLA_DRE package. 


CONTENTS
========
File/Directory Name   	  Description
----------------------------------------------------------------------------------
README                    read this file first

WHAT_IS_NEW               details on the changes and fixes in the current release

LICENSE                   license file

[binary]
 +UCLA_DRE      	  executable of the tool compiled on Red Hat Enterprise 
                          Linux WS release 4 (Nahant Update 8) with glibc 2.3.4

[doc]                     directory with the tool documentations 
 +DRE_SupportedRules      design rules and styles that are supported 
 +unsupported_styles      layout styles and rules that are NOT currently supported
 +Pub_Full_8pages         Publication (8 pages) describing methods used in the tool
 +Pub_Concise             Concise version of same publication (4 pages)

[example]                 directory with files needed to run an example
 +tutorial                step by step short tutorial on how to run the tool with 
                          examples of different netlist formats (START WITH THIS)
 +dr/freePDK45_LI_finfet  design rule file to use for FinFET and local interconnect
                          studies. This is to show how FinFET and LI can be enabled
                          in the DR file, the only difference with other DR files is
                          that FinFET and LI are enabled, i.e. set to 1)


SYSTEM REQUIREMENTS
===================
This software should compile and run on most Unix platforms with a C++ compiler.


BUGS
====
Please send all bug reports to Rani S. Ghaida <rani@ee.ucla.edu>.
Do not forget to mention which version of UCLA_DRE you have and which
operating system and C++ compiler you are using.


PATCHLEVEL
==========
This is release 1 of UCLA_DRE at patchlevel 4.


ACKNOWLEDGEMENTS
================
This work is partly supported by IMPACT, SRC, and NSF.
