Thesis and Project Reports

Ph.D. Thesis

[1] J. Lee, Implications of Modern Semiconductor Technologies on Gate Sizing. PhD thesis, 2012. [ paper ]
[2] R. S. Ghaida, Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies. PhD thesis, 2012. [ paper ]
[3] L. Cheng, Statistical Analysis and Optimization for Timing and Power of VLSI Circuits. PhD thesis, Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]

M.S. Thesis

[1] A. Sharma, “Understanding software application behaviour in presence of permanent and intermittent hardware faults,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2013. [ paper ]
[2] A. A. Kagalwalla, “Design-aware mask manufacturing,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2011. [ paper ]
[3] A. Pant, “Hardware-software interface in the presence of hardware manufacturing variations,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]

M.S. Reports

[1] J. Dong, “High Level Battery Modeling Considering Discharge Rate and Temperature Effects,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2012. [ paper ]
[2] N. Jin, “Modelling of guardbank reduction on design area,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2012. [ paper ]
[3] S. Mok, “Post-Layout Sizing for Leakage Power Optimization: A Comparative Study,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2011. [ paper ]
[4] C. Apte, “Power Consumption Variability in Embedded Processors,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2011. [ paper ]
[5] P. Kulkarni, “Trading Accuracy for Power with an Under-designed Multiplier Architecture,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2011. [ presentation ]
[6] D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]
[7] A. Kasibhatla, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]
[8] V. Popuri, “Bias-driven Robust Analog Circuit Sizing Scheme,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2009. [ paper ]

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