Thesis and Project Reports
Ph.D. Thesis
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[1]
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J. Lee, Implications of Modern Semiconductor Technologies on Gate Sizing.
PhD thesis, 2012.
[ paper ]
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[2]
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R. Ghaida, Design Enablement and Design-Centric Assessment of Future
Semiconductor Technologies.
PhD thesis, 2012.
[ paper ]
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[3]
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L. Cheng, Statistical Analysis and Optimization for Timing and Power of
VLSI Circuits.
PhD thesis, Department of Electrical Engineering, University of
California Los Angeles, 2010.
[ paper ]
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M.S. Thesis
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[1]
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A. A. Kagalwalla, “Design-aware mask manufacturing,” tech. rep., Department
of Electrical Engineering, University of California Los Angeles, 2011.
[ paper ]
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[2]
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A. Pant, “Hardware-software interface in the presence of hardware
manufacturing variations,” tech. rep., Department of Electrical Engineering,
University of California Los Angeles, 2010.
[ paper ]
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M.S. Reports
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[1]
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J. Dong, “High Level Battery Modeling Considering Discharge Rate and
Temperature Effects,” tech. rep., Department of Electrical Engineering,
University of California Los Angeles, 2012.
[ paper ]
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[2]
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N. Jin, “Modelling of guardbank reduction on design area,” tech. rep.,
Department of Electrical Engineering, University of California Los Angeles,
2012.
[ paper ]
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[3]
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S. Mok, “Post-Layout Sizing for Leakage Power Optimization: A Comparative
Study,” tech. rep., Department of Electrical Engineering, University of
California Los Angeles, 2011.
[ paper ]
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[4]
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C. Apte, “Power Consumption Variability in Embedded Processors,” tech.
rep., Department of Electrical Engineering, University of California Los
Angeles, 2011.
[ paper ]
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[5]
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P. Kulkarni, “Trading Accuracy for Power with an Under-designed Multiplier
Architecture,” tech. rep., Department of Electrical Engineering, University
of California Los Angeles, 2011.
[ presentation ]
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[6]
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D. Reinhard, “On Comparing Conventional and Electrically Driven OPC
Techniques,” tech. rep., Department of Electrical Engineering, University
of California Los Angeles, 2010.
[ paper ]
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[7]
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A. Kasibhatla, “Eyecharts: Constructive Benchmarking of Gate Sizing
Heuristics,” tech. rep., Department of Electrical Engineering, University
of California Los Angeles, 2010.
[ paper ]
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[8]
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V. Popuri, “Bias-driven Robust Analog Circuit Sizing Scheme,” tech. rep.,
Department of Electrical Engineering, University of California Los Angeles,
2009.
[ paper ]
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