Robustness and Benchmarking of Gate Sizing

We are looking into optimality of power optimization heuristics, specifically gate sizing. Gate sizing, along with gate length and Vt assignment, are important methods for physical design. They allow for an effective optimization method that can balance the power, delay and area costs. The importance of these methods highlights the importance of a systematic benchmarking and evaluation methodology to compare methods, and to gain an understanding of the "best-practices" for gate sizing. These questions are addressed in the research.

Empirical Benchmarking

By: Santiago Mok, advised by Prof. Puneet Gupta Objective: To investigate benchmarking alternatives and performance of post-layout gate sizing algorithm. The first step in this project is to enhance an open-source static timing engine. Spef-reading, Elmore wire delay calculation and power calculation are functions developed so far that serve as the infrastructure for gate sizing algorithm. The enhancement are integrated into OA Gear static timing engine. OA Gear is an open source toolkit based on Si2 OpenAccess. OpenAccess is an open source API built on C++ for IC CAD design and development.

  • UCLA-Timer Enhanced Features:
    1. Elmore wire delay calculator with SPEF including a wire slew degradation model.
    2. A simple power calculator and extended parser functionalities to parse power related entries.
    3. Added support for reading units from .lib/SPEF and ensuring consistency.
    4. A simple Ceff calculation (disabled by default).
    5. Sensitivity-based gate sizing approaches: (updated 09/14/2009)
      • Power Sensitivity
      • Duet Sensitivity based on 1) power-delay and 2) power-slack
    • Download: UCLA-Timer (LICENSE) (subset of OA Gear, for full OA Gear refer to OAGear project page)

UCSD benchmarks for gate sizing can be found in this link: UC Benchmark Suite for Gate Sizing

Benchmarking using Synthetic Eyecharts

By: Amarnath Kasibhatla, advised by Prof. Puneet Gupta

Objective: Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proved to be NP-hard. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suffered from lack of any systematic way of assessing the quality of the proposed algorithms. We develop methods to generate benchmark circuits (called eyecharts) of arbitrary size along with their optimal solutions calculated using dynamic programming. We evaluate the suboptimalities of some popular gate sizing algorithms. Eyecharts help diagnose weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research. Our results show that common sizing methods (including commercial tools) can be suboptimal by as much as 46% for realistic libraries and circuit topologies. The benchmarks and the code can be downloaded from EyeCharts.

Manufacturing-Aware Gate Sizing: Benchmarking and ECO-Awareness

By: John Lee, advised by Prof. Puneet Gupta

Objective: This research seeks to answer practical questions related to the gate sizing problem (1) what is the advantage of using a statistical power objective in gate sizing, and (2) how can gate sizing be used to perform late ECOs.

(1) In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this paper, we quantify the difference between the statistical and deterministic optima of leakage power while making no assumptions about the delay model.We develop a framework for deriving a theoretical upper bound on the suboptimality that is incurred by using the deterministic optimum as an approximation for the statistical optimum. We show that for the mean power measure, the deterministic optima is an excellent approximation, and for the mean plus standard deviation measures, the optimality gap increases as the amount of inter-die variation grows, for a suite of benchmark circuits in a 45 nm technology. For large variations, we show that there are excellent linear approximations that can be used to approximate the effects of variation. Therefore, the need to develop special statistical power optimization algorithms is questionable.

(2) Circuit design often runs in parallel with the development of the manufacturing process that will be used to fabricate it. However, as the manufacturing process matures, its models may undergo substantial changes as the design nears production. These changes may cause the design itself to fail its specifications, and in these cases it is necessary to perform an Engineering Change Order (ECO) to correct these problems. We present a new framework to perform incremental gate sizing for process changes late in the design cycle. This includes a method to measure and estimate ECO cost, transform these costs into a linear programming optimization problem, and solve the problem to find the ECO. This method performs well, compared to a leading commercial physical design tool, reducing ECO costs by 18% to 99% in changed area, and 1% to 96% in number of pins with unnecessary pin timing changes.

Publications List:

[1] J. Lee and P. Gupta, “Impact of range and precision in technology on cell-based design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2012. [ paper | presentation ]
[2] J. Lee and P. Gupta, “ECO Cost Measurement and Incremental Gate Sizing for Late Process Changes,” ACM Transactions on Design Automation of Electronic Systems, 2012. [ paper ]
[3] S. Mok, J. Lee, and P. Gupta, “Discrete sizing for leakage power optimization in physical design: A comparative study,” ACM Transactions on Design Automation of Electronic Systems, 2012. [ paper ]
[4] J. Lee and P. Gupta, “Incremental Gate Sizing for Late Process Changes,” in Proc. IEEE International Conference on Computer Design, October 2010. [ paper | presentation ]
[5] P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” in Proc. ACM/IEEE Design Automation Conference (DAC), June 2010. [ paper ]
[6] J. Cong, P. Gupta, and J. Lee, “Evaluating Statistical Power Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1750-1762, Nov 2010. [ paper ]
[7] J. Cong, P. Gupta, and J. Lee, “On the Futlity of Statistical Power Optimization,” in Proc. Asia and South Pacific Design Automation Conference, January 2009. [ paper | presentation ]
[8] P. Gupta, A. B. Kahng, and S. Shah, “Standard Cell Library Optimization for Leakage Reduction,” in Proc. ACM/IEEE Design Automation Conference (DAC), July 2006. [ paper ]
[9] P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, “Gate-Length Biasing for Runtime Leakage Control,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), June 2006. [ paper ]
[10] P. Gupta, A. B. Kahng, and P. Sharma, “A Practical Transistor-Level Threshold Voltage Assignment Methodology,” in IEEE International Symposium on Quality Electronic Design, pp. 261-265, March 2005. [ paper ]
[11] P. Gupta, A. B. Kahng, P. Sharma, and D. D. Sylvester, “Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Reduction,” in Proc. ACM/IEEE Design Automation Conference (DAC), July 2004. [ paper ]
[12] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools,” in Proc. ACM/IEEE Design Automation Conference (DAC), June 2003. [ paper | presentation ]

(This material is based in part upon work supported by the National Science Foundation under Grant No. 0811832. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.)

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