Research

Teaching

NanoCAD Group

Internal

Publications

Many of the papers below have been made available in PDF format for easy access. Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.

Journals

[1]	A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-Aware Mask Inspection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]
[2]	R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]
[3]	M. Gottscho, A. A. Kagalwalla, and P. Gupta, “Power Variability in Contemporary DRAMs,” IEEE Embedded Systems Letters, 2012. [ paper ]
[4]	T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,” IEEE Transactions on Semiconductor Manufacturing, 2012. [ paper ]
[5]	T. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2011. [ paper ]
[6]	P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading accuracy for power in a multiplier architecture,” Journal of Low Power Electronics, 2011. [ paper ]
[7]	A. Pant, P. Gupta, and M. van der Schaar, “Appadapt: Opportunistic application adaptation in presence of hardware variation,” IEEE Transactions on Very Large Scale Integration Systems, 2011. [ paper ]
[8]	R. S. Ghaida and P. Gupta, “Within-Layer Overlay Impact for Design in Metal Double Patterning,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]
[9]	P. Gupta, K. Jeong, A. Kahng, and C.-H. Park, “Electrical Assessment of Lithographic Gate Line-End Patterning,” SPIE Journal of Microlithography, Microfabrication and Microsystems, 2010. [ paper ]
[10]	J. Cong, P. Gupta, and J. Lee, “Evaluating Statistical Power Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1750-1762, Nov 2010. [ paper ]
[11]	R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]
[12]	L. Cheng, P. Gupta, C. J. Spanos, K. Qian, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010. [ paper ]
[13]	L. Cheng, P. Gupta, and L. He, “Efficient Additive Statistical Leakage Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009. [ paper ]
[14]	P. Gupta, A. B. Kahng, and C.-H. Park, “Detailed Placement for Enhanced Control of Resist and Etch CDs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2007. [ paper ]
[15]	P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, September 2007. [ paper ]
[16]	P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven Optical Proximity Correction for Mask Cost Reduction,” SPIE Journal of Microlithography, Microfabrication and Microsystems, September 2007. [ paper ]
[17]	P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, “Gate-Length Biasing for Runtime Leakage Control,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 2006. [ paper ]
[18]	P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi, and X. Xu, “Wafer Topography-Aware Optical Proximity Correction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April 2006. [ paper ]
[19]	P. Gupta, A. B. Kahng, I. Mandoiu, and P. Sharma, “Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, November 2005. [ paper ]
[20]	P. Gupta, A. B. Kahng, and S. Mantik, “Routing Driven Scan Chain Ordering,” ACM Transactions on Design Automation of Electronic Systems, March 2005. [ paper ]
[21]	P. Gupta, A. B. Kahng, and S. Muddu, “Quantifying Error in Dynamic Power Estimation of CMOS Circuits,” Journal of Analog Integrated Circuits and Signal Processing, March 2005. [ paper ]

Conferences

[1]	A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta, “Design-of-Experiments Based Design Rule Optimization,” in SPIE Advanced Lithography, February 2012. [ paper ]
[2]	R. S. Ghaida and P. Gupta, “A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition,” in SPIE Advanced Lithography, February 2012. [ paper ]
[3]	T. B. Chan, P. Gupta, A. Kahng, and L. Lai, “DDRO: A Noval Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,” in IEEE International Symposium on Quality Electronic Design, 2012. [ paper \| presentation ]
[4]	L. Bathen, N. Dutt, A. Nicolau, and P. Gupta, “Vamv: Variability-aware memory virtualization,” in IEEE/ACM Design, Automation and Test in Europe, 2012. [ paper ]
[5]	R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A Framework for Double Patterning-Enabled Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2011. [ paper \| presentation ]
[6]	T.-B. Chan, J. Sartori, P. Gupta, and R. Kumar, “On the Efficacy of NBTI Mitigation Techniques,” in Design, Automation, and Test in Europe (DATE), March 2011. [ paper \| presentation ]
[7]	L. Wanner, R. Balani, S. Zahedi, C. Apte, P. Gupta, and M. Srivastava, “Variability Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems,” in Design, Automation, and Test in Europe (DATE), March 2011. [ paper \| presentation ]
[8]	A. A. Kagalwalla, P. Gupta, D.-H. Hur, and C.-H. Park, “Defect-aware Reticle Floorplanning for EUV Masks,” in SPIE Advanced Lithography, March 2011. [ paper ]
[9]	P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading Accuracy for Power with an Underdesigned Multiplier Architecture,” in Proc. IEEE/ACM International Conference on VLSI Design, To Appear 2011. [ paper \| presentation ]
[10]	A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware Mask Inspection,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2010. [ paper \| presentation ]
[11]	T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2010. [ paper \| presentation ]
[12]	P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” in Proc. ACM/IEEE Design Automation Conference, June 2010. [ paper ]
[13]	A. Pant, P. Gupta, and M. v. d. Schaar, “Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability,” in ACM Great Lakes Symposium on Very Large Scale Integration, May 2010. [ paper ]
[14]	J. Sartori, A. Pant, R. Kumar, and P. Gupta, “Variation Aware Speed Binning of Multi-core Processors,” in IEEE International Symposium on Quality Electronic Design, March 2010. [ paper ]
[15]	T.-B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” in Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration, February 2010. [ paper \| presentation ]
[16]	T.-B. Chan and P. Gupta, “On Electrical Modeling of Imperfect Diffusion Patterning,” in Proc. IEEE/ACM International Conference on VLSI Design, January 2010. [ paper \| presentation ]
[17]	L. Cheng, P. Gupta, and L. He, “On Confidence in Characterization and Application of Variation Models,” in Proc. Asia and South Pacific Design Automation Conference, January 2010. [ paper ]
[18]	J. Lee and P. Gupta, “Incremental Gate Sizing for Late Process Changes,” in Proc. IEEE International Conference on Computer Design, Oct 2010. [ paper \| presentation ]
[19]	L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “A Case for Opportunistic Embedded Sensing In Presence of Hardware Power Varibility,” in HotPower'10, 2010. [ paper \| presentation ]
[20]	R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic Evaluation of Design Rules,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2009. [ paper \| presentation ]
[21]	R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography,” in SPIE/BACUS Symposium on Photomask Technology and Management, September 2009. [ paper \| presentation ]
[22]	R. S. Ghaida and P. Gupta, “Design-Overlay Interactions in Metal Double Patterning,” in SPIE Advanced Lithography Symposium, February 2009. [ paper \| presentation ]
[23]	J. Cong, P. Gupta, and J. Lee, “On the Futlity of Statistical Power Optimization,” in Proc. Asia and South Pacific Design Automation Conference, January 2009. [ paper \| presentation ]
[24]	L. Cheng, P. Gupta, and L. He, “Accounting for Non-linear Dependence Using Function Driven Component Analysis,” in Proc. Asia and South Pacific Design Automation Conference, January 2009. [ paper ]
[25]	P. Gupta and D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2009.
[26]	L. Cheng, P. Gupta, K. Qian, C. Spanos, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” in Proc. ACM/IEEE Design Automation Conference, 2009. [ paper ]
[27]	P. Gupta and A. B. Kahng, “Bounded Lifetime Integrated Circuits,” in Proc. ACM/IEEE Design Automation Conference, June 2008. [ paper ]
[28]	P. Gupta, K. Jeong, A. B. Kahng, and C.-H. Park, “Electrical Metrics for Lithographic Line-End Tapering,” in SPIE Photomask and NGL Mask Technology, April 2008. [ paper ]
[29]	P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, “Shaping Gate Channels for Improved Devices,” in SPIE Advanced Lithography Symposium, February 2008. [ paper ]
[30]	P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Investigation of Diffusion Rounding for Post-Lithography Analysis,” in Proc. Asia and South Pacific Design Automation Conference, January 2008. [ paper ]
[31]	P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, “Line End Shortening is not Always a Failure,” in Proc. ACM/IEEE Design Automation Conference, June 2007. [ paper ]
[32]	P. Gupta, A. B. Kahng, and S. Shah, “Standard Cell Library Optimization for Leakage Reduction,” in Proc. ACM/IEEE Design Automation Conference, July 2006. [ paper ]
[33]	P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah, and P. Sharma, “Lithography Simulation-Based Full-Chip Design Analyses,” in SPIE Microlithography, February 2006. [ paper ]
[34]	P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis,” in SPIE Microlithography, February 2006. [ paper ]
[35]	P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,” in SPIE Microlithography, February 2006. [ paper ]
[36]	P. Gupta and A. B. Kahng, “Efficient Design and Analysis of Robust Power Distribution Meshes,” in Proc. IEEE/ACM International Conference on VLSI Design, January 2006. [ paper ]
[37]	P. Gupta, A. B. Kahng, S. Muddu, and N. S., “Modeling Edge Placement Error Distribution in Standard Cell Library,” in SPIE Microlithography, January 2006. [ paper ]
[38]	P. Gupta, A. B. Kahng, and C.-H. Park, “Enhanced Resist and Etch CD Control by Design Perturbation,” in SPIE/BACUS Symposium on Photomask Technology and Management, October 2005. [ paper ]
[39]	P. Gupta, A. B. Kahng, S. Muddu, O. Nakagawa, and C.-H. Park, “Modeling OPC Complexity for Design for Manufacturability,” in SPIE/BACUS Symposium on Photomask Technology and Management, October 2005. [ paper ]
[40]	P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Focus Variation,” in Proc. ACM/IEEE Design Automation Conference, June 2005. [ paper ]
[41]	Y. Zhang, R. Gray, O. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and C. Progler, “Interaction and Balance of Mask Write Time and Design RET Strategies,” in SPIE Photomask and NGL Mask Technology, April 2005. [ paper ]
[42]	P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven OPC for Mask Cost Reduction,” in IEEE International Symposium on Quality Electronic Design, pp. 270-275, March 2005. [ paper ]
[43]	P. Gupta, A. B. Kahng, and P. Sharma, “A Practical Transistor-Level Threshold Voltage Assignment Methodology,” in IEEE International Symposium on Quality Electronic Design, pp. 261-265, March 2005. [ paper ]
[44]	P. Gupta, A. B. Kahng, and C.-H. Park, “Manufacturing-Aware Design Methodology for Assist Feature Correctness,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, March 2005. [ paper ]
[45]	P. Gupta, F.-L. Heng, and J.-F. Lee, “Toward Through-Process Layout Quality Metrics,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, March 2005. [ paper ]
[46]	P. Gupta, A. B. Kahng, and C.-H. Park, “Detailed Placement for Improved Depth of Focus and CD Control,” in Proc. Asia and South Pacific Design Automation Conference, January 2005. [ paper ]
[47]	P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi, and X. Xu, “Topography-Aware Optical Proximity Correction for Better DOF margin and CD Control,” in SPIE Photomask and NGL Mask Technology, January 2005. [ paper ]
[48]	P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward a Methodology for Manufacturability Driven Design Rule Exploration,” in Proc. ACM/IEEE Design Automation Conference, June 2004. [ paper ]
[49]	P. Gupta, F.-L. Heng, and M. Lavin, “Merits of Cellwise Model-Based OPC,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, February 2004. [ paper ]
[50]	P. Gupta, F.-L. Heng, R. Gordon, K. Lai, and J. Lee, “Taming Focus Variation in VLSI Design,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, February 2004. [ paper ]
[51]	P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Investigation of Performance Metrics for Interconnect Stack Architectures,” in Proc. g SLIP, February 2004. [ paper ]
[52]	P. Gupta, A. B. Kahng, and S. Mantik, “Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling,” in Proc. IEEE/ACM International Conference on VLSI Design, January 2004. [ paper ]
[53]	P. Gupta and F.-L. Heng, “Toward a Systematic-Variation Aware Timing Methodology,” in Proc. ACM/IEEE Design Automation Conference, 2004. [ paper ]
[54]	P. Gupta, A. B. Kahng, P. Sharma, and D. D. Sylvester, “Selective Gate-Length Biasing for Cost-Effective R gntime Leakage Reduction,” in Proc. ACM/IEEE Design Automation Conference, 2004. [ paper ]
[55]	P. Gupta, A. B. Kahng, I. Mandoiu, and P. Sharma, “Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 754-759, November 2003. [ paper ]
[56]	P. Gupta and A. B. Kahng, “Manufacturing-Aware Physical Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 681-687, November 2003. [ paper ]
[57]	Y. Chen, P. Gupta, and A. B. Kahng, “Performance-Impact Limited Area Fill Synthesis,” in Proc. ACM/IEEE Design Automation Conference, June 2003. [ paper ]
[58]	P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools,” in Proc. ACM/IEEE Design Automation Conference, June 2003. [ paper \| presentation ]
[59]	P. Gupta and A. B. Kahng, “Quantifying Error in Dynamic Power Estimation of CMOS Circuits,” in IEEE International Symposium on Quality Electronic Design, pp. 273-278, March 2003. [ paper ]
[60]	P. Gupta, A. B. Kahng, and S. Mantik, “A Proposal for Routing-Based Timing-Driven Scan Chain Ordering,” in IEEE International Symposium on Quality Electronic Design, pp. 339-343, March 2003. [ paper ]
[61]	Y. Chen, P. Gupta, and A. B. Kahng, “Performance-Impact Limited Dummy Fill Insertion,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, pp. 857-862, February 2003. [ paper \| presentation ]
[62]	P. Gupta, A. B. Kahng, and S. Mantik, “Routing-Aware Scan Chain Ordering,” in Proc. Asia and South Pacific Design Automation Conference, pp. 857-862, January 2003. [ paper \| presentation ]
[63]	Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI,” in IEEE ASIC/SoC Conference, pp. 411-415, September 2002. [ paper ]

Invited Papers

[1]	A. Neureuther, J. Rubinstein, M. Miller, K. Y. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T.-J. K. Liu, X. Sun, K. Jeong, , P. Gupta, A. Kagalwalla, R. Ghaida, and T.-B. Chan, “Collaborative research on emerging technologies and design,” in Proc. SPIE Photomask and Next-Generation Lithography Mask Technology, 2011. [ paper ]
[2]	P. Gupta and R. Gupta, “Underdesigned and opportunistic computing,” in Proc. Asian Test Symposium, 2011. [ paper \| presentation ]
[3]	T.-B. Chan, R. S. Ghaida, and P. Gupta, “Electrical Modeling of Lithographic Imperfections,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010. (embedded tutorial). [ paper \| presentation ]
[4]	P. Gupta, A. B. Kahng, O. Nakagawa, and K. Samadi, “Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing,” in Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf., October 2005. (invited paper). [ paper ]
[5]	P. Gupta, A. B. Kahng, and C.-H. Park, “Improving OPC Quality Via Interactions Within the Design-to-Manufacturing Flow,” in SPIE Photomask and NGL Mask Technology, April 2005. (Invited Paper). [ paper ]
[6]	P. Gupta, A. B. Kahng, C.-H. Park, P. Sharma, D. Sylvester, and J. Yang, “Joining the Design and Mask Flows for Better and Cheaper Masks,” in SPIE/BACUS Symposium on Photomask Technology and Management, September 2004. (Invited Paper). [ paper ]
[7]	P. Gupta and A. B. Kahng, “Manufacturing-Aware Physical Design,” Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2003. (embedded tutorial). [ paper ]
[8]	P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward Performance-Driven Reduction of the Cost of RET-based Lithography Control,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, February 2003. (invited paper). [ paper ]

Books and Book Chapters

[1]	J. Lee and P. Gupta, Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment. Now Publishers, 2012.
[2]	P. Gupta and E. Papadopoulou, “Yield analysis and optimization,” in The Handbook of Algorithms for VLSI Physical Design Automation, CRC Press, 2010.

Invited Talks and Tutorials

[1]	P. Gupta, “Design-assisted semiconductor manufacturing,” in IEEE International Symposium on Quality Electronic Design, 2012. Short tutorial.
[2]	P. Gupta, “Underdesigned and opportunistic computing machines,” in Nanosystem Design and Variability Workshop, EPFL, 2011. (invited talk).
[3]	P. Gupta, “Designing for uncertainty: Addressing process variations and aging issues in vlsi designs,” in IEEE International Symposium on VLSI Design, Automation and Test, 2011. (tutorial). [ presentation ]
[4]	P. Gupta, “Variability and reliability: Will they get better or worse in future cmos technologies ?,” in IEEE Workshop on Design for Reliability and Variability, 2011. (Panel Discussion).
[5]	P. Gupta, “Modeling performance impact of variability,” in NSF/SRC The International Variability Characterization Workshop, 2010. (invited talk).
[6]	P. Gupta, “Revisiting variation models and their reliability,” in IEEE/ACM Workshop on Variability Modeling and Characterization, 2009. (invited talk).
[7]	P. Gupta, “Design for ultra-low-k1 patterning and manufacturing,” in IEEE International Conference on Microelectronic Teststructures (ICMTS), 2009. tutorial.
[8]	P. Gupta, “Design and Use of Tweakable Devices for Future Logic Implementation,” in IEEE International Electron Devices Meeting, pp. 1-1, December 2008. (invited talk). [ presentation ]
[9]	P. Gupta, “The Electrical Design Manufacturing Interface,” in Electronic Design Processes Workshop, 2008.
[10]	P. Gupta and C. Wu, “Lithography and Memories: From Shapes to Electrical,” in IEEE VLSI Test Symposium, 2008.
[11]	D. Chidambarrao, P. Gupta, P. Elakkumanan, L. Liebmann, D. Marculescu, and N. Tamarapalli, “DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction,” in Proc. ACM/IEEE Design Automation Conference, 2008. (full-day tutorial).
[12]	P. Gupta, “Challenges at 45nm and Beyond,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, 2008. (panel discussion).
[13]	P. Gupta and R. Puri, “Impact of Variability On VLSI Circuits,” in SPIE Advanced Lithography Symposium, 2007. (short course).
[14]	P. Gupta and A. B. Kahng, “CMP and DFM,” in CMP-MIC, 2005. (Short Tutorial).
[15]	P. Gupta, “DFM Fundamentals,” in WesCon, 2005. (short tutorial).

Patents

[1]	A. Kahng, P. Gupta, D. Sylvester, and J. Yang, “Tool for modifying mask design layout.” U.S. Patent No. 8,103,981, 2012.
[2]	A. Kahng, P. Gupta, and S. Shah, “System and method for performing transistor-level static performance analysis using cell-level static analysis tools.” U.S. Patent No. 7,865,856, 2011.
[3]	P. Gupta, A. Kahng, P. Sharma, and S. Muddu, “Method and system for wafer topography-aware integrated circuit design analysis and optimization.” U.S. Patent No. 8,024,675, 2011.
[4]	P. Gupta, A. Kahng, and S. Shah, “Method and system for integrated circuit optimization by using an optimized standard-cell library.” US Patent No. 7,716,612, 2010.
[5]	P. Gupta, A. Kahng, and D. Reed, “Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objective.” US Patent No. 7,730,432, 2010.
[6]	P. Gupta and A. Kahng, “Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit.” US Patent No. 7,743,349, 2010.
[7]	S. Nakagawa, A. Kahng, P. Wong, and P. Gupta. U.S. Patent No. 7.745,239, 2010.
[8]	C. Moon, P. Gupta, P. Donehue, and A. Kahng, “Method of designing a digital circuit by correlating different static timing analyzers.” U.S. Patent No. 7,823,098, 2010.
[9]	P. Gupta and A. Kahng, “Method and system for topography-aware reticle enhancement.” U.S. Patent No. 7,814,456, 2010.
[10]	P. Gupta and A. Kahng, “System and method for varying the starting conditions for a resolution enhancement program to improve the probability that design goals will be met.” US Patent No. 7,627,849, 2009.
[11]	P. Gupta, A. Kahng, and P. C.-H., “Method and system for placing layout objects in a standard-cell layout.” US Patent No. 7,640,522, 2009.
[12]	P. Gupta, A. Kahng, D. Sylvester, and J. Yang, “Method for correcting a mask design layout.” US Patent No. 7,614,032, 2009.
[13]	P. Gupta, F.-L. Heng, and M. Lavin, “Method of IC Fabrication, IC Mask Fabrication and Program Product.” US Patent No. 7,353,492, 2008.
[14]	P. Gupta and A. Kahng, “Gate-Length Biasing for Digital Circuit Optimization.” US Patent No. 7,441,211, 2008.
[15]	P. Gupta, A. Kahng, D. Sylvester, and J. Yang, “Method for Correcting a Mask Design Layout.” US Patent No. 7,149,999, 2006.
[16]	P. Gupta, F.-L. Heng, D. Kung, and D. Ostapko, “Integrated Circuit Logic with Self Compensating Block Delays.” US Patent No. 7,084,476, 2006.

Workshops (No Published Proceedings)

[1]	J. Lee and P. Gupta, “Parametric hierarchy recovery for layout extracted netlists,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2011. [ paper \| presentation ]
[2]	L. Cheng and P. Gupta, “A Levelized Variation Modeling Scheme,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010.
[3]	A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware Mask Inspection,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010.
[4]	J. Lee and P. Gupta, “Incremental gate sizing for late process changes,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010. [ paper \| presentation ]
[5]	V. Popuri, P. Gupta, and S. Pamarti, “Bias-Driven Robust Analog Circuit Sizing Scheme,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2010.
[6]	T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring,” in SRC TECHCON'10, 2010.
[7]	R. S. Ghaida and P. Gupta, “A Framework for Systematic Evaluation and Exploration of Design Rules,” in SRC TECHCON'09, 2009.
[8]	A. Pant, P. Gupta, and M. v. d. Schaar, “Software Adaptation to Handle Manufacturing Variability and Relax Hardware Overdesign,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2009.
[9]	J. Sartori, A. Pant, P. Gupta, and R. Kumar, “On Performance Binning of Multicore Processors,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2009.
[10]	T.-B. Chan, P. Gupta, V. Balakrishnan, and Y. Cao, “Extended Burn-in for Reduced Vth Variation,” in IEEE International Workshop on Design for Manufacturibility and Yield, 2009.