Projects and Software
Design-Technology Co-Optimization
A Framework for Early and Systematic Evaluation and Exploration of Design Rules
By: Rani S. Ghaida, advised by Prof. Puneet Gupta
Objective:
A framework for co-evaluation and exploration of design rules and technology decisions at cell and chip levels. By using first order models of variability and manufacturability and layout topology/congestion-based area estimation, our framework can evaluate big decisions before exact process and design technologies are known.
UCLA_DRE is a tool written in C++ for evaluating and exploring design rules (DRs) and layout styles at cell level in standard-cell based designs.
The tool takes a transistor netlist, design rules, and estimates of process control parameters as input and evaluates cell-area, manufacturability, and variability of the entire design. It also displays evaluation results and layout information of every cell in the design separately. The latest release can be downloaded here ( LICENSE).
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[1]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “A Cost-Driven
Lihographic Correction Methodology Based on Off-the-Shelf
Sizing Tools,” in Proc. ACM/IEEE Design Automation Conference,
June 2003.
[ paper |
presentation ]
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[2]
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P. Gupta, F.-L. Heng, and M. Lavin, “Merits of Cellwise Model-Based
OPC,” in Proc. SPIE Conference on Design and Process Integration for
Microelectronic Manufacturing, February 2004.
[ paper ]
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[3]
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P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Investigation of
Performance Metrics for Interconnect Stack Architectures,” in
Proc. g SLIP, February 2004.
[ paper ]
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[4]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward a Methodology for
Manufacturability Driven Design Rule Exploration,” in Proc.
ACM/IEEE Design Automation Conference, June 2004.
[ paper ]
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[5]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven OPC
for Mask Cost Reduction,” in IEEE International Symposium on
Quality Electronic Design, pp. 270-275, March 2005.
[ paper ]
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[6]
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P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi, and X. Xu, “Topography-Aware
Optical Proximity Correction for Better DOF margin and CD
Control,” in SPIE Photomask and NGL Mask Technology, January 2005.
[ paper ]
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[7]
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P. Gupta, A. B. Kahng, S. Muddu, O. Nakagawa, and C.-H. Park, “Modeling OPC
Complexity for Design for Manufacturability,” in SPIE/BACUS
Symposium on Photomask Technology and Management, October 2005.
[ paper ]
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[8]
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Y. Zhang, R. Gray, O. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and
C. Progler, “Interaction and Balance of Mask Write Time and Design
RET Strategies,” in SPIE Photomask and NGL Mask Technology, April
2005.
[ paper ]
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[9]
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P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, “Line End Shortening is not
Always a Failure,” in Proc. ACM/IEEE Design Automation Conference,
June 2007.
[ paper ]
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[10]
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P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, “Shaping Gate Channels
for Improved Devices,” in SPIE Advanced Lithography Symposium,
February 2008.
[ paper ]
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[11]
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P. Gupta, K. Jeong, A. B. Kahng, and C.-H. Park, “Electrical Metrics for
Lithographic Line-End Tapering,” in SPIE Photomask and NGL Mask
Technology, April 2008.
[ paper ]
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[12]
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R. S. Ghaida and P. Gupta, “Design-Overlay Interactions in Metal
Double Patterning,” in SPIE Advanced Lithography Symposium,
February 2009.
[ paper |
presentation ]
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[13]
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R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning
Lithography,” in SPIE/BACUS Symposium on Photomask Technology and
Management, September 2009.
[ paper |
presentation ]
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[14]
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P. Gupta and D. Reinhard, “On Comparing Conventional and Electrically
Driven OPC Techniques,” in SPIE/BACUS Symposium on Photomask
Technology and Management, 2009.
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[15]
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R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic
Evaluation of Design Rules,” in Proc. IEEE/ACM International
Conference on Computer-Aided Design, November 2009.
[ paper |
presentation ]
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[16]
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T.-B. Chan and P. Gupta, “On Electrical Modeling of Imperfect
Diffusion Patterning,” in Proc. IEEE/ACM International Conference
on VLSI Design, January 2010.
[ paper |
presentation ]
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[17]
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T.-B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of
Electrical Process Window,” in Proc. SPIE Conference on Design
for Manufacturability through Design-Process Integration, February 2010.
[ paper |
presentation ]
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[18]
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A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware
Mask Inspection,” in Proc. IEEE/ACM International Conference on
Computer-Aided Design, November 2010.
[ paper |
presentation ]
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[19]
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T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process
Monitoring for Back-end Manufacturing Cost Reduction,” in
Proc. IEEE/ACM International Conference on Computer-Aided Design, November
2010.
[ paper |
presentation ]
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[20]
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A. A. Kagalwalla, P. Gupta, D.-H. Hur, and C.-H. Park, “Defect-aware
Reticle Floorplanning for EUV Masks,” in SPIE Advanced
Lithography, March 2011.
[ paper ]
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[21]
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R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A
Framework for Double Patterning-Enabled Design,” in Proc.
IEEE/ACM International Conference on Computer-Aided Design, November 2011.
[ paper |
presentation ]
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[22]
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A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta,
“Design-of-Experiments Based Design Rule Optimization,” in
SPIE Advanced Lithography, February 2012.
[ paper ]
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[23]
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R. S. Ghaida and P. Gupta, “A Novel Methodology for
Triple/Multiple-Patterning Layout Decomposition,” in SPIE
Advanced Lithography, February 2012.
[ paper ]
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[24]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward
Performance-Driven Reduction of the Cost of RET-based Lithography
Control,” in Proc. SPIE Conference on Design and Process Integration
for Microelectronic Manufacturing, February 2003.
(invited paper).
[ paper ]
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[25]
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P. Gupta, A. B. Kahng, C.-H. Park, P. Sharma, D. Sylvester, and J. Yang,
“Joining the Design and Mask Flows for Better and Cheaper
Masks,” in SPIE/BACUS Symposium on Photomask Technology and
Management, September 2004.
(Invited Paper).
[ paper ]
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[26]
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P. Gupta, A. B. Kahng, and C.-H. Park, “Improving OPC Quality Via
Interactions Within the Design-to-Manufacturing Flow,” in
SPIE Photomask and NGL Mask Technology, April 2005.
(Invited Paper).
[ paper ]
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[27]
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P. Gupta, “The Electrical Design Manufacturing Interface,” in
Electronic Design Processes Workshop, 2008.
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[28]
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P. Gupta, “Challenges at 45nm and Beyond,” in Proc. IEEE/ACM
International Conference on Computer-Aided Design, 2008.
(panel discussion).
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[29]
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P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi, and X. Xu, “Wafer
Topography-Aware Optical Proximity Correction,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
April 2006.
[ paper ]
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[30]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven
Optical Proximity Correction for Mask Cost Reduction,” SPIE
Journal of Microlithography, Microfabrication and Microsystems, September
2007.
[ paper ]
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[31]
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R. S. Ghaida and P. Gupta, “Within-Layer Overlay Impact for Design in
Metal Double Patterning,” IEEE Transactions on Semiconductor
Manufacturing, 2010.
[ paper ]
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[32]
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P. Gupta, K. Jeong, A. Kahng, and C.-H. Park, “Electrical Assessment of
Lithographic Gate Line-End Patterning,” SPIE Journal of
Microlithography, Microfabrication and Microsystems, 2010.
[ paper ]
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[33]
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R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning
Lithography for Reduced Cost and Improved Overlay Control,”
IEEE Transactions on Semiconductor Manufacturing, 2010.
[ paper ]
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[34]
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T. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of
Electrical Process Window,” SPIE Journal of
Micro/Nanolithography, MEMS and MOEMS (JM3), 2011.
[ paper ]
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[35]
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A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-Aware
Mask Inspection,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 2012.
[ paper ]
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[36]
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R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation
of Design Rules, Technology Choices, and Layout Methodologies,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 2012.
[ paper ]
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[37]
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R. S. Ghaida and P. Gupta, “A Framework for Systematic Evaluation and
Exploration of Design Rules,” in SRC TECHCON'09, 2009.
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[38]
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T.-B. Chan, P. Gupta, V. Balakrishnan, and Y. Cao, “Extended Burn-in for
Reduced Vth Variation,” in IEEE International Workshop on Design
for Manufacturibility and Yield, 2009.
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[39]
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A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware
Mask Inspection,” in IEEE International Workshop on Design for
Manufacturibility and Yield, 2010.
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[40]
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V. Popuri, P. Gupta, and S. Pamarti, “Bias-Driven Robust Analog Circuit
Sizing Scheme,” in IEEE International Workshop on Design for
Manufacturibility and Yield, 2010.
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[41]
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J. Lee and P. Gupta, “Parametric hierarchy recovery for layout extracted
netlists,” in IEEE International Workshop on Design for
Manufacturibility and Yield, 2011.
[ paper |
presentation ]
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Re-evaluation of Statistical Methods in Design
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across-Wafer Variability
Objective:
Modeling spatial variation is important for statistical analysis. In practice, all of which indicate that spatial variation comes from deterministic across-wafer variation, and purely random spatial variation is not significant. We analytically study the impact of across-wafer variation and show how it gives an appearance of correlation.
We have developed a new die-level variation model considering deterministic across-wafer variation and derived the range of conditions under which ignoring spatial variation altogether may be acceptable.
Package:
Spatial_detect is a Matlab script to extract across-wafer variation from measurement data. It assumes the across wafer variation to be a quadratic function. In this detection, we have two different spatial variation models: 1) Random field based spatial variation model [1, 2]; 2) Modeling across-wafer variation [3]. In practice, modeling across-wafer variation is more accurate and efficient than the random field based spatial variation model. The current release includes source code, user manual, and sample input files.
Reference:
[1] Jinjun Xiong, Vladimir Zolotov, Lei He, "Robust Extraction of Spatial Correlation," IEEE/ACM International Symposium on Physical Design, San Jose, CA, pp. 2-9, April 2006.
[2] Jinjun Xiong, Vladimir Zolotov, Lei He, "Robust Extraction of Spatial Correlation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.26, No.4, Pages 2-9, April,2007.
By: Lerong Cheng, advised by Prof. Puneet Gupta
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[1]
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L. Cheng and P. Gupta, “A Levelized Variation Modeling Scheme,” in
IEEE International Workshop on Design for Manufacturibility and Yield, 2010.
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[2]
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T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process
Monitoring,” in SRC TECHCON'10, 2010.
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[3]
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L. Cheng, Statistical Analysis and Optimization for Timing and Power of
VLSI Circuits.
PhD thesis, Department of Electrical Engineering, University of
California Los Angeles, 2010.
[ paper ]
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Robustness and Benchmarking of Gate Sizing
Gate sizing, along with gate length and Vt assignment, are important methods for physical design. They allow for an effective optimization method that can balance the power, delay and area costs. The importance of these methods highlights the importance of a systematic benchmarking and evaluation methodology to compare methods, and to gain an understanding of the "best-practices" for gate sizing. These questions are addressed in the research.
By: Santiago Mok, advised by Prof. Puneet Gupta
Objective:
To investigate benchmarking alternatives and performance of post-layout gate sizing algorithm. The first step in this project is to enhance an open-source static timing engine. Spef-reading, Elmore wire delay calculation and power calculation are
functions developed so far that serve as the infrastructure for gate sizing algorithm. The enhancement are integrated into OA Gear static timing engine. OA Gear is an open source toolkit based on Si2 OpenAccess. OpenAccess is an open source API built on C++ for IC CAD design and development.
- Enhanced Features:
- Elmore wire delay calculator with SPEF including a wire slew degradation model.
- A simple power calculator and extended parser functionalities to parse power related entries.
- Added support for reading units from .lib/SPEF and ensuring consistency.
- A simple Ceff calculation (disabled by default).
- Sensitivity-based gate sizing approaches: (updated 09/14/2009)
- Power Sensitivity
- Duet Sensitivity based on 1) power-delay and 2) power-slack
- Download: UCLA-Timer (LICENSE) (subset of OA Gear, for full OA Gear refer to OAGear project page)
By: Amarnath Kasibhatla, advised by Prof. Puneet Gupta
Objective:
Discrete gate sizing is one of the most commonly used,
flexible, and powerful techniques for digital circuit optimization. The
underlying problem has been proved to be NP-hard. Several (suboptimal)
gate sizing heuristics have been proposed over the past two
decades, but research has suffered from lack of any systematic way of
assessing the quality of the proposed algorithms. We develop methods to
generate benchmark circuits (called eyecharts) of arbitrary size along
with their optimal solutions calculated using dynamic programming.
We evaluate the suboptimalities of some popular gate sizing algorithms.
Eyecharts help diagnose weaknesses of existing gate sizing algorithms,
enable systematic and quantitative comparison of sizing algorithms, and
catalyze further gate sizing research. Our results show that common
sizing methods (including commercial tools) can be suboptimal by as
much as 46% for realistic libraries and circuit topologies.
The benchmarks and the code can be downloaded from EyeCharts.
By: John Lee, advised by Prof. Puneet Gupta
Objective:
This research seeks to answer practical questions related to the gate sizing problem. First, what is the advantage of using a statistical power objective in gate sizing. There are many papers that address the statistical delay question, but the effects of a statistical power metric is examined in this work. Also, there is the question of using gate sizing to perform late ECOs. In this step the accuracy of the timing models is important, along with the incremental properties of the algorithm. This is also explored.
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[1]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “A Cost-Driven
Lihographic Correction Methodology Based on Off-the-Shelf
Sizing Tools,” in Proc. ACM/IEEE Design Automation Conference,
June 2003.
[ paper |
presentation ]
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[2]
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P. Gupta, A. B. Kahng, P. Sharma, and D. D. Sylvester, “Selective
Gate-Length Biasing for Cost-Effective R gntime Leakage
Reduction,” in Proc. ACM/IEEE Design Automation Conference, 2004.
[ paper ]
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[3]
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P. Gupta, A. B. Kahng, and P. Sharma, “A Practical Transistor-Level
Threshold Voltage Assignment Methodology,” in IEEE
International Symposium on Quality Electronic Design, pp. 261-265, March
2005.
[ paper ]
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[4]
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P. Gupta, A. B. Kahng, and S. Shah, “Standard Cell Library Optimization
for Leakage Reduction,” in Proc. ACM/IEEE Design Automation
Conference, July 2006.
[ paper ]
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[5]
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J. Cong, P. Gupta, and J. Lee, “On the Futlity of Statistical Power
Optimization,” in Proc. Asia and South Pacific Design Automation
Conference, January 2009.
[ paper |
presentation ]
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[6]
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P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, “Eyecharts: Constructive
Benchmarking of Gate Sizing Heuristics,” in Proc. ACM/IEEE
Design Automation Conference, June 2010.
[ paper ]
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[7]
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J. Lee and P. Gupta, “Incremental Gate Sizing for Late Process
Changes,” in Proc. IEEE International Conference on Computer Design,
Oct 2010.
[ paper |
presentation ]
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[8]
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P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, “Gate-Length Biasing
for Runtime Leakage Control,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, June 2006.
[ paper ]
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[9]
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J. Cong, P. Gupta, and J. Lee, “Evaluating Statistical Power Optimization,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, vol. 29, pp. 1750-1762, Nov 2010.
[ paper ]
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[10]
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J. Lee and P. Gupta, “Incremental gate sizing for late process changes,” in
IEEE International Workshop on Design for Manufacturibility and Yield,
2010.
[ paper |
presentation ]
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[11]
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V. Popuri, “Bias-driven robust analog circuit sizing scheme,” tech. rep.,
Department of Electrical Engineering, University of California Los Angeles,
2009.
[ paper ]
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