Design-Assisted Technology Scaling

The semiconductor industry is likely to see several rad- ical changes in the fabrication and device technologies in the next decade. Each of these technologies requires enormous research investment before they can see any adoption. Con- ventional “after-the-fact” changes to design methodologies and tools to what technology offers lead to wasted research investment, delayed adoption and underutilization of technology as well as more design overhead. Therefore, early assessment of design restrictions imposed by, and design advantages of technological choices is absolutely essential. In addition to building such co-evaluation frameworks, we have pioneered several techniques to enable silicon manufacturing guided by design and also explore design-enablement of future patterning options.

A Framework for Early and Systematic Evaluation and Exploration of Design Rules

Students: Rani S. Ghaida, Abde Ali Kagalwalla

Objective: A framework for co-evaluation and exploration of design rules and technology decisions at cell and chip levels. By using first order models of variability and manufacturability and layout topology/congestion-based area estimation, our framework can evaluate big decisions before exact process and design technologies are known.

UCLA_DRE is a tool written in C++ for evaluating and exploring design rules (DRs) and layout styles at cell level in standard-cell based designs.

The tool takes a transistor netlist, design rules, and estimates of process control parameters as input and evaluates cell-area, manufacturability, and variability of the entire design. It also displays evaluation results and layout information of every cell in the design separately. The latest release can be downloaded here (LICENSE).

A Framework for Evaluating Device Variability Impact on Circuits

Students: Liangzhen Lai, Shaodi Wang

Objective: A framework for evaluating the impact of device-level variability on circuit-level performance. An evaluation flow is implemented to automatically take device-level performance figures (i.e. Ion, Ioff, DIBL, SS etc.) variations as input, and generate corresponding variation data on circuit-level performance (i.e. leakage power, delay etc.). The framework is applied to line edge roughness (LER) induced variability on double-gate finfet. The sample data can be downloaded here:

Publications List:

[1] T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, A. B. Kahng, and E. Sahouria, “Benchmarking of Mask Fracturing Heuristics,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2014. [ paper | presentation ]
[2] W.-C. Wang and P. Gupta, “Efficient Layout Generation and Evaluation of Vertical Channel Devices,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2014. [ paper | presentation ]
[3] P. Kulkarni, P. Gupta, and R. Beraha, “Minimizing Clock Domain Crossing in Network on Chip Interconnect,” in IEEE International Symposium on Quality Electronic Design, March 2014. [ paper | presentation ]
[4] A. A. Kagalwalla and P. Gupta, “Comprehensive Defect Avoidance Framework for Mitigating EUV Mask Defects,” in SPIE Advanced Lithography Symposium, March 2014. [ paper | presentation ]
[5] Y. Badr, K.-w. Ma, and P. Gupta, “Layout Pattern-driven Design Rule Evaluation,” in SPIE Advanced Lithography Symposium, March 2014. [ paper ]
[6] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, January 2014. [ paper | presentation ]
[7] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “PROCEED: a Pareto Optimization-based Circuit-level Evaluator for Emerging Devices,” in Proc. Asia and South Pacific Design Automation Conference, January 2014. [ paper | presentation ]
[8] R. S. Ghaida and P. Gupta, “Role of design in multiple patterning: Technology development, design enablement and process control,” in IEEE/ACM Design, Automation and Test in Europe, 2013. [ paper ]
[9] P. Gupta, A. Mallik, and J. Torres, “Design-patterning interactions,” in SPIE Advanced Lithography Symposium, 2013. Half-Day tutorial.
[10] A. A. Kagalwalla and P. Gupta, “Design-Aware Defect-Avoidance Floorplanning of EUV Masks,” IEEE Transactions on Semiconductor Manufacturing, 2013. Accepted for publication. [ paper ]
[11] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, “A methodology for the early exploration of design rules for multiple-patterning technologies,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2012. [ paper | presentation ]
[12] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,” in Intl. Conf. on IC Design and Technology, June 2012. [ paper | presentation ]
[13] A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta, “Design-of-Experiments Based Design Rule Optimization,” in SPIE Advanced Lithography, February 2012. [ paper ]
[14] R. S. Ghaida, K. Agarwal, L. Liebmann, S. R. Nassif, and P. Gupta, “A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition,” in SPIE Advanced Lithography, February 2012. [ paper ]
[15] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-Aware Mask Inspection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]
[16] R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]
[17] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, “Layout Decomposition and Legalization for Double-Patterning Technology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]
[18] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A Framework for Double Patterning-Enabled Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2011. [ paper | presentation ]
[19] A. A. Kagalwalla, P. Gupta, D.-H. Hur, and C.-H. Park, “Defect-aware Reticle Floorplanning for EUV Masks,” in SPIE Advanced Lithography, March 2011. [ paper ]
[20] T. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2011. [ paper ]
[21] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware Mask Inspection,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2010. [ paper | presentation ]
[22] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2010. [ paper | presentation ]
[23] T.-B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” in Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration, February 2010. [ paper | presentation ]
[24] T.-B. Chan and P. Gupta, “On Electrical Modeling of Imperfect Diffusion Patterning,” in Proc. IEEE/ACM International Conference on VLSI Design, January 2010. [ paper | presentation ]
[25] R. S. Ghaida and P. Gupta, “Within-Layer Overlay Impact for Design in Metal Double Patterning,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]
[26] P. Gupta, K. Jeong, A. Kahng, and C.-H. Park, “Electrical Assessment of Lithographic Gate Line-End Patterning,” SPIE Journal of Microlithography, Microfabrication and Microsystems, 2010. [ paper ]
[27] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]
[28] R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic Evaluation of Design Rules,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2009. [ paper | presentation ]
[29] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography,” in SPIE/BACUS Symposium on Photomask Technology and Management, September 2009. [ paper | presentation ]
[30] R. S. Ghaida and P. Gupta, “Design-Overlay Interactions in Metal Double Patterning,” in SPIE Advanced Lithography Symposium, February 2009. [ paper | presentation ]
[31] P. Gupta and D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” in SPIE/BACUS Symposium on Photomask Technology and Management, 2009.
[32] P. Gupta, K. Jeong, A. B. Kahng, and C.-H. Park, “Electrical Metrics for Lithographic Line-End Tapering,” in SPIE Photomask and NGL Mask Technology, April 2008. [ paper ]
[33] P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, “Shaping Gate Channels for Improved Devices,” in SPIE Advanced Lithography Symposium, February 2008. [ paper ]
[34] P. Gupta, “The Electrical Design Manufacturing Interface,” in Electronic Design Processes Workshop, 2008.
[35] P. Gupta, “Challenges at 45nm and Beyond,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, 2008. (panel discussion).
[36] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven Optical Proximity Correction for Mask Cost Reduction,” SPIE Journal of Microlithography, Microfabrication and Microsystems, September 2007. [ paper ]
[37] P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, “Line End Shortening is not Always a Failure,” in Proc. ACM/IEEE Design Automation Conference, June 2007. [ paper ]
[38] P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi, and X. Xu, “Wafer Topography-Aware Optical Proximity Correction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April 2006. [ paper ]
[39] P. Gupta, A. B. Kahng, S. Muddu, O. Nakagawa, and C.-H. Park, “Modeling OPC Complexity for Design for Manufacturability,” in SPIE/BACUS Symposium on Photomask Technology and Management, October 2005. [ paper ]
[40] Y. Zhang, R. Gray, O. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and C. Progler, “Interaction and Balance of Mask Write Time and Design RET Strategies,” in SPIE Photomask and NGL Mask Technology, April 2005. [ paper ]
[41] P. Gupta, A. B. Kahng, and C.-H. Park, “Improving OPC Quality Via Interactions Within the Design-to-Manufacturing Flow,” in SPIE Photomask and NGL Mask Technology, April 2005. (Invited Paper). [ paper ]
[42] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven OPC for Mask Cost Reduction,” in IEEE International Symposium on Quality Electronic Design, pp. 270-275, March 2005. [ paper ]
[43] P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi, and X. Xu, “Topography-Aware Optical Proximity Correction for Better DOF margin and CD Control,” in SPIE Photomask and NGL Mask Technology, January 2005. [ paper ]
[44] P. Gupta, A. B. Kahng, C.-H. Park, P. Sharma, D. Sylvester, and J. Yang, “Joining the Design and Mask Flows for Better and Cheaper Masks,” in SPIE/BACUS Symposium on Photomask Technology and Management, September 2004. (Invited Paper). [ paper ]
[45] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward a Methodology for Manufacturability Driven Design Rule Exploration,” in Proc. ACM/IEEE Design Automation Conference, June 2004. [ paper ]
[46] P. Gupta, F.-L. Heng, and M. Lavin, “Merits of Cellwise Model-Based OPC,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, February 2004. [ paper ]
[47] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Investigation of Performance Metrics for Interconnect Stack Architectures,” in Proc. g SLIP, February 2004. [ paper ]
[48] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools,” in Proc. ACM/IEEE Design Automation Conference, June 2003. [ paper | presentation ]
[49] P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward Performance-Driven Reduction of the Cost of RET-based Lithography Control,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, February 2003. (invited paper). [ paper ]


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