Design-Assisted Technology Scaling
The semiconductor industry is likely to see several rad-
ical changes in the fabrication and device technologies in the next decade. Each of these
technologies requires enormous research investment before they can see any adoption. Con-
ventional “after-the-fact” changes to design methodologies and tools to what technology offers
lead to wasted research investment, delayed adoption and underutilization of technology as
well as more design overhead. Therefore, early assessment of design restrictions imposed by,
and design advantages of technological choices is absolutely essential. In addition to building such co-evaluation frameworks, we have pioneered several
techniques to enable silicon manufacturing guided by design and also explore design-enablement of future patterning options.
A Framework for Early and Systematic Evaluation and Exploration of Design Rules
Students: Rani S. Ghaida, Abde Ali Kagalwalla
Objective:
A framework for co-evaluation and exploration of design rules and technology decisions at cell and chip levels. By using first order models of variability and manufacturability and layout topology/congestion-based area estimation, our framework can evaluate big decisions before exact process and design technologies are known.
UCLA_DRE is a tool written in C++ for evaluating and exploring design rules (DRs) and layout styles at cell level in standard-cell based designs.
The tool takes a transistor netlist, design rules, and estimates of process control parameters as input and evaluates cell-area, manufacturability, and variability of the entire design. It also displays evaluation results and layout information of every cell in the design separately. The latest release can be downloaded here ( LICENSE).
A Framework for Evaluating Device Variability Impact on Circuits
Students: Liangzhen Lai, Shaodi Wang
Objective:
A framework for evaluating the impact of device-level variability on circuit-level performance. An evaluation flow is implemented to automatically take device-level performance figures (i.e. Ion, Ioff, DIBL, SS etc.) variations as input, and generate corresponding variation data on circuit-level performance (i.e. leakage power, delay etc.).
The framework is applied to line edge roughness (LER) induced variability on double-gate finfet. The sample data can be downloaded here:
Publications List:
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[1]
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R. Ghaida and P. Gupta, “Role of design in multiple patterning: Technology
development, design enablement and process control,” 2013.
[ paper ]
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[2]
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P. Gupta, A. Mallik, and J. Torres, “Design-patterning interactions,” in
SPIE Advanced Lithography Symposium, 2013.
Half-Day tutorial.
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[3]
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A. A. Kagalwalla and P. Gupta, “Design-Aware Defect-Avoidance Floorplanning
of EUV Masks,” IEEE Transactions on Semiconductor Manufacturing,
2013.
Accepted for publication.
[ paper ]
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[4]
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R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, “A methodology for the early
exploration of design rules for multiple-patterning technologies,” in
Proc. IEEE/ACM International Conference on Computer-Aided Design, November
2012.
[ paper |
presentation ]
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[5]
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R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “O(n)
layout-coloring for multiple-patterning lithography and conflict-removal
using compaction,” in Intl. Conf. on IC Design and Technology, June
2012.
[ paper |
presentation ]
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[6]
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A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta,
“Design-of-Experiments Based Design Rule Optimization,” in
SPIE Advanced Lithography, February 2012.
[ paper ]
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[7]
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R. S. Ghaida, K. Agarwal, L. Liebmann, S. R. Nassif, and P. Gupta, “A
Novel Methodology for Triple/Multiple-Patterning Layout
Decomposition,” in SPIE Advanced Lithography, February 2012.
[ paper ]
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[8]
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A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-Aware
Mask Inspection,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 2012.
[ paper ]
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[9]
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R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation
of Design Rules, Technology Choices, and Layout Methodologies,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 2012.
[ paper ]
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[10]
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R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and
P. Gupta, “Layout Decomposition and Legalization for
Double-Patterning Technology,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, 2012.
[ paper ]
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[11]
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R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A
Framework for Double Patterning-Enabled Design,” in Proc.
IEEE/ACM International Conference on Computer-Aided Design, November 2011.
[ paper |
presentation ]
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[12]
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A. A. Kagalwalla, P. Gupta, D.-H. Hur, and C.-H. Park, “Defect-aware
Reticle Floorplanning for EUV Masks,” in SPIE Advanced
Lithography, March 2011.
[ paper ]
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[13]
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T. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of
Electrical Process Window,” SPIE Journal of
Micro/Nanolithography, MEMS and MOEMS (JM3), 2011.
[ paper ]
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[14]
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A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware
Mask Inspection,” in Proc. IEEE/ACM International Conference on
Computer-Aided Design, November 2010.
[ paper |
presentation ]
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[15]
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T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process
Monitoring for Back-end Manufacturing Cost Reduction,” in
Proc. IEEE/ACM International Conference on Computer-Aided Design, November
2010.
[ paper |
presentation ]
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[16]
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T.-B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of
Electrical Process Window,” in Proc. SPIE Conference on Design
for Manufacturability through Design-Process Integration, February 2010.
[ paper |
presentation ]
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[17]
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T.-B. Chan and P. Gupta, “On Electrical Modeling of Imperfect
Diffusion Patterning,” in Proc. IEEE/ACM International Conference
on VLSI Design, January 2010.
[ paper |
presentation ]
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[18]
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R. S. Ghaida and P. Gupta, “Within-Layer Overlay Impact for Design in
Metal Double Patterning,” IEEE Transactions on Semiconductor
Manufacturing, 2010.
[ paper ]
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[19]
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P. Gupta, K. Jeong, A. Kahng, and C.-H. Park, “Electrical Assessment of
Lithographic Gate Line-End Patterning,” SPIE Journal of
Microlithography, Microfabrication and Microsystems, 2010.
[ paper ]
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[20]
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R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning
Lithography for Reduced Cost and Improved Overlay Control,”
IEEE Transactions on Semiconductor Manufacturing, 2010.
[ paper ]
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[21]
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R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic
Evaluation of Design Rules,” in Proc. IEEE/ACM International
Conference on Computer-Aided Design, November 2009.
[ paper |
presentation ]
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[22]
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R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning
Lithography,” in SPIE/BACUS Symposium on Photomask Technology and
Management, September 2009.
[ paper |
presentation ]
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[23]
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R. S. Ghaida and P. Gupta, “Design-Overlay Interactions in Metal
Double Patterning,” in SPIE Advanced Lithography Symposium,
February 2009.
[ paper |
presentation ]
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[24]
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P. Gupta and D. Reinhard, “On Comparing Conventional and Electrically
Driven OPC Techniques,” in SPIE/BACUS Symposium on Photomask
Technology and Management, 2009.
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[25]
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P. Gupta, K. Jeong, A. B. Kahng, and C.-H. Park, “Electrical Metrics for
Lithographic Line-End Tapering,” in SPIE Photomask and NGL Mask
Technology, April 2008.
[ paper ]
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[26]
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P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, “Shaping Gate Channels
for Improved Devices,” in SPIE Advanced Lithography Symposium,
February 2008.
[ paper ]
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[27]
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P. Gupta, “The Electrical Design Manufacturing Interface,” in
Electronic Design Processes Workshop, 2008.
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[28]
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P. Gupta, “Challenges at 45nm and Beyond,” in Proc. IEEE/ACM
International Conference on Computer-Aided Design, 2008.
(panel discussion).
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[29]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven
Optical Proximity Correction for Mask Cost Reduction,” SPIE
Journal of Microlithography, Microfabrication and Microsystems, September
2007.
[ paper ]
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[30]
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P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, “Line End Shortening is not
Always a Failure,” in Proc. ACM/IEEE Design Automation Conference,
June 2007.
[ paper ]
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[31]
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P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi, and X. Xu, “Wafer
Topography-Aware Optical Proximity Correction,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
April 2006.
[ paper ]
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[32]
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P. Gupta, A. B. Kahng, S. Muddu, O. Nakagawa, and C.-H. Park, “Modeling OPC
Complexity for Design for Manufacturability,” in SPIE/BACUS
Symposium on Photomask Technology and Management, October 2005.
[ paper ]
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[33]
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Y. Zhang, R. Gray, O. Nakagawa, P. Gupta, H. Kamberian, G. Xiao, R. Cottle, and
C. Progler, “Interaction and Balance of Mask Write Time and Design
RET Strategies,” in SPIE Photomask and NGL Mask Technology, April
2005.
[ paper ]
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[34]
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P. Gupta, A. B. Kahng, and C.-H. Park, “Improving OPC Quality Via
Interactions Within the Design-to-Manufacturing Flow,” in
SPIE Photomask and NGL Mask Technology, April 2005.
(Invited Paper).
[ paper ]
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[35]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Performance-Driven OPC
for Mask Cost Reduction,” in IEEE International Symposium on
Quality Electronic Design, pp. 270-275, March 2005.
[ paper ]
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[36]
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P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi, and X. Xu, “Topography-Aware
Optical Proximity Correction for Better DOF margin and CD
Control,” in SPIE Photomask and NGL Mask Technology, January 2005.
[ paper ]
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[37]
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P. Gupta, A. B. Kahng, C.-H. Park, P. Sharma, D. Sylvester, and J. Yang,
“Joining the Design and Mask Flows for Better and Cheaper
Masks,” in SPIE/BACUS Symposium on Photomask Technology and
Management, September 2004.
(Invited Paper).
[ paper ]
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[38]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward a Methodology for
Manufacturability Driven Design Rule Exploration,” in Proc.
ACM/IEEE Design Automation Conference, June 2004.
[ paper ]
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[39]
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P. Gupta, F.-L. Heng, and M. Lavin, “Merits of Cellwise Model-Based
OPC,” in Proc. SPIE Conference on Design and Process Integration for
Microelectronic Manufacturing, February 2004.
[ paper ]
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[40]
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P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Investigation of
Performance Metrics for Interconnect Stack Architectures,” in
Proc. g SLIP, February 2004.
[ paper ]
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[41]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “A Cost-Driven
Lihographic Correction Methodology Based on Off-the-Shelf
Sizing Tools,” in Proc. ACM/IEEE Design Automation Conference,
June 2003.
[ paper |
presentation ]
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[42]
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P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Toward
Performance-Driven Reduction of the Cost of RET-based Lithography
Control,” in Proc. SPIE Conference on Design and Process Integration
for Microelectronic Manufacturing, February 2003.
(invited paper).
[ paper ]
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