Lab Members

Updated June 13, 2017


Faculty (Principal Investigator)

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Prof. Puneet Gupta

Homepage: http://www.ee.ucla.edu/~puneet
Contact: puneet AT ee DOT ucla DOT edu
Publications

Ph.D

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Wei-Che Wang

Contact: weichewang@ucla.edu
Research interests: Development of computational techniques and models for exploring and optimizing semiconductor technologies.
Industry experience: Taiwan Semiconductor Manufacturing Company (TSMC)
Current research project: Layout optimization for vertical channel devices, Hardware security.
Publications:
[1] W.-C. Wang and P. Gupta, “Efficient Layout Generation and Evaluation of Vertical Channel Devices,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2014. [ paper | presentation ]
[2] W.-C. Wang, Y. Yona, S. Diggavi, and P. Gupta, “LEDPUF: Stability-Guaranteed Physical Unclonable Functions through Locally Enhanced Defectivity,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2016. [ paper ]
[3] W.-C. Wang, Y. Yona, Y. Wu, S.-Y. Hung, S. Diggavi, and P. Gupta, “Implementation of Stable PUFs Using Gate Oxide Breakdown,” in IEEE International Symposium on Asian Hardware Oriented Security and Trust (AsianHOST), October 2017. [ paper ]
[4] W.-C. Wang and P. Gupta, “Efficient Layout Generation and Evaluation of Vertical Channel Devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016. [ paper ]
[5] W.-C. Wang, Y. Yona, S. Diggavi, and P. Gupta, “Design and Analysis of Stability-Guaranteed PUFs,” IEEE Transactions on Information Forensics and Security (TIFS), November 2017. [ paper ]


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Saptadeep Pal

Contact: saptadeep@ucla.edu
Research interests:Design Methodologies and Architectures for System Integration on Next Generation Interconnects, Development of Silicon Interconnect Fabric, Stochastic Computing, Technology Optimization
Experience: DISCUS, Trinity College Dublin, Ireland; Robert Bosch Centre for Cyber Physical Systems, Bengaluru, India
Publications:
[1] S. Pal, D. Petrisko, A. Bajwa, S. S. Iyer, R. Kumar, and P. Gupta, “A Case for Packageless Processors,” in IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2018. [ paper ]
[2] S. Jangam, S. Pal, A. Bajwa, S. Pamarti, P. Gupta, and S. S. Iyer, “Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme,” in IEEE Electronic Components and Technology Conference (ECTC), May 2017. [ paper | presentation ]
[3] S. Wang, S. Pal, T. Li, A. Pan, C. Grezes, P. K. Amiri, K. L. Wang, C. O. Chui, and P. Gupta, “Hybrid VC-MTJ/CMOS Non-volatile Stochastic Logic for Efficient Computing,” in IEEE/ACM Design, Automation and Test in Europe, March 2017. Best paper nomination. [ paper | presentation ]
[4] S. Pal, S. S. Iyer, and P. Gupta, “Advanced packaging and heterogeneous integration to reboot computing,” in IEEE International Conference on Rebooting Computing, 2017. [ paper ]
[5] S. Pal, “Supervia: Relieving routing congestion using double-height vias,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2017. [ paper | presentation ]


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Irina Alam

Contact: irina1@ucla.edu
Research interests:Opportunistic memory architecture for power and performance benefits, Exploring efficient memory error resilience techniques
Experience: Micron Technology Inc., Singapore
Publications:
[1] M. Gottscho, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, “Low-Cost Memory Fault Tolerance for IoT Devices,” ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS), October 2017. Best paper award. [ paper ]
[2] M. Gottscho, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, “Low-Cost Memory Fault Tolerance for IoT Devices,” ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS), October 2017. [ paper ]


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Wojciech Romaszkan

Contact: wromaszkan@ucla.edu
Industry experience: Imagination Technologies, UK; NEC, Japan
Publications:

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Tianmu Li

Contact: litianmu1995@ucla.edu
Industry experience:
Publications:
[1] S. Wang, S. Pal, T. Li, A. Pan, C. Grezes, P. K. Amiri, K. L. Wang, C. O. Chui, and P. Gupta, “Hybrid VC-MTJ/CMOS Non-volatile Stochastic Logic for Efficient Computing,” in IEEE/ACM Design, Automation and Test in Europe, March 2017. Best paper nomination. [ paper | presentation ]


M.S.

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YooJin Chae

Contact: yoojinchae@ucla.edu
Experience: Synopsys Inc


Undergraduate

Ian Chang

Contact: ichangschool@gmail.com
Current Project: X-Mem

Alumni

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Dr. Yasmine Badr

Contact: ybadr AT ucla DOT edu
Research interests:Algorithms and Computational methods for Design and Technology Co-optimization
Industry Experience: IBM Egypt, CUTEC Institute Germany, Microsoft Research Egypt, Mentor Graphics Egypt, Mentor Graphics U.S., Intel U.S.
Publications:
[1] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, January 2014. [ paper | presentation ]
[2] Y. Badr, K.-w. Ma, and P. Gupta, “Layout Pattern-driven Design Rule Evaluation,” in SPIE Advanced Lithography Symposium, March 2014. [ paper | presentation ]
[3] Y. Badr, A. Torres, and P. Gupta, “Incorporating DSA in multipatterning semiconductor manufacturing technologies,” in SPIE Advanced Lithography Symposium, February 2015. [ paper ]
[4] Y. Badr, A. Torres, and P. Gupta, “Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts/Vias,” in Proc. ACM/IEEE Design Automation Conference (DAC), June 2015. [ paper | presentation ]
[5] Y. Badr and P. Gupta, “Technology Path-finding for Directed Self-assembly for Via Layers",” in SPIE Advanced Lithography Symposium, February 2017. [ paper | presentation ]
[6] R. S. Ghaida, Y. Badr, and P. Gupta, “Pattern-restricted design at 10nm and beyond,” in Proc. IEEE International Conference on Computer Design, 2014. [ paper ]
[7] Y. Badr, K.-w. Ma, and P. Gupta, “Layout pattern-driven design rule evaluation,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2014. [ paper ]
[8] L. Zhu, Y. Badr, S. Wang, S. Iyer, and P. Gupta, “Assessing Benefits of a Buried Interconnect Layer in Digital Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), May 2016. [ paper ]
[9] Y. Badr, A. Torres, and P. Gupta, “Mask Assignment and Dsa Grouping for DSA-MP Hybrid Lithography for sub-7nm Contact/Via Holes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), September 2016. [ paper ]
[10] Y. Badr and P. Gupta, “Technology path-finding framework for directed-self assembly for via layers,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2017. [ paper ]


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Dr. Mark Gottscho

Contact: mgottscho@ucla.edu
PhD thesis: Opportunistic Memory Systems in Presence of Hardware Variability
Previous industry experience: Microsoft Research, Altera, National Aeronautics and Space Administration (NASA)
[1] M. Gottscho, A. A. Kagalwalla, and P. Gupta, “Power Variability in Contemporary DRAMs,” IEEE Embedded Systems Letters, vol. 4, pp. 37-40, 2012. [ paper ]
[2] L. Bathen, M. Gottscho, N. Dutt, P. Gupta, and A. Nicolau, “ViPZonE: OS-Level Memory Variability-Aware Physical Address Zoning for Energy Savings,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, October 2012. [ paper ]
[3] N. Dutt, P. Gupta, A. Nicolau, L. Bathen, and M. Gottscho, “Variability-Aware Memory Management for Nanoscale Computing,” in Proc. Asia and South Pacific Design Automation Conference, 2013. [ paper ]
[4] N. Dutt, P. Gupta, A. Nicolau, A. BanaiyanMofrad, M. Gottscho, and M. Shoushtari, “Multi-Layer Memory Resiliency,” in Proc. ACM/IEEE Design Automation Conference (DAC), June 2014. [ paper ]
[5] M. Gottscho, A. Banaiyan, Mofrad, N. Dutt, A. Nicolau, and P. Gupta, “Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches,” in Proc. ACM/IEEE Design Automation Conference (DAC), June 2014. [ paper | presentation ]
[6] S. Elmalaki, M. Gottscho, P. Gupta, and M. Srivastava, “A Case for Battery Charging-Aware Power Management and Deferrable Task Scheduling in Smartphones,” in USENIX Workshop on Power-Aware Computing and Systems (HotPower), October 2014. [ paper | presentation ]
[7] M. Gottscho, L. A. D. Bathen, N. Dutt, A. Nicolau, and P. Gupta, “ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings,” IEEE Transactions on Computers, vol. 64, pp. 1483-1496, May 2015. [ paper ]
[8] L. Wanner, L. Lai, A. Rahimi, M. Gottscho, P. Mercati, C.-H. Huang, F. Sala, Y. Agarwal, L. Dolecek, N. Dutt, P. Gupta, R. Gupta, R. Jhala, R. Kumar, S. Lerner, M. Subhasish, A. Nicolau, T. S. Rosing, M. B. Srivastava, S. Swanson, D. Sylvester, and Y. Zhou, “NSF Expedition on Variability-Aware Software: Recent Results and Contributions,” De Gruyter Information Technology (it), vol. 57, pp. 181-198, June 2015. [ paper ]
[9] M. Gottscho, A. BanaiyanMofrad, N. Dutt, A. Nicolau, and P. Gupta, “DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era,” ACM Transactions on Architecture and Code Optimization (TACO), vol. 12, August 2015. [ paper ]
[10] Q. Zhang, L. Lai, M. Gottscho, and P. Gupta, “Multi-Story Power Distribution Networks for GPUs,” in IEEE/ACM Design, Automation and Test in Europe, March 2016. [ paper | presentation ]
[11] M. Gottscho, S. Govindan, B. Sharma, M. Shoaib, and P. Gupta, “X-Mem: A Cross-Platform and Extensible Memory Characterization Tool for the Cloud,” in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016. [ paper | presentation ]
[12] M. Gottscho, C. Schoeny, L. Dolecek, and P. Gupta, “Software-Defined Error-Correcting Codes,” in IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), June 2016. [ paper | presentation ]
[13] M. Gottscho, M. Shoaib, S. Govindan, B. Sharma, D. Wang, and P. Gupta, “Measuring the Impact of Memory Errors on Application Performance,” IEEE Computer Architecture Letters (CAL), August 2016. [ paper ]
[14] M. Gottscho, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, “Low-Cost Memory Fault Tolerance for IoT Devices,” ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS), October 2017. [ paper ]
[15] M. Gottscho, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, “Low-Cost Memory Fault Tolerance for IoT Devices,” ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transcations on Embedded Computing Systems (TECS), October 2017. Best paper award. [ paper ]


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Dr. Shaodi Wang

Contact: shaodiwang AT g DOT ucla DOT edu
Research interests: Design for manufacturing modeling, novel device modeling and circuit analysis.
Industry experience: Samsung Semiconductor, ARM
Current projects: Emerging memory technology, Negative differential resistance
[1] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “PROCEED: a Pareto Optimization-based Circuit-level Evaluator for Emerging Devices,” in Proc. Asia and South Pacific Design Automation Conference, January 2014. [ paper | presentation ]
[2] S. Wang, H. Lee, C. Grezes, P. Khalili, K. L. Wang, and P. Gupta, “MTJ Variation Monitor-assisted Adaptive MRAM Write,” in Proc. ACM/IEEE Design Automation Conference (DAC), June 2016. [ paper | presentation ]
[3] S. Wang, S. Pal, T. Li, A. Pan, C. Grezes, P. K. Amiri, K. L. Wang, C. O. Chui, and P. Gupta, “Hybrid VC-MTJ/CMOS Non-volatile Stochastic Logic for Efficient Computing,” in IEEE/ACM Design, Automation and Test in Europe, March 2017. Best paper nomination. [ paper | presentation ]
[4] S. Wang, G. Leung, A. Pan, C. O. Chui, and P. Gupta, “Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless Finfet Technologies,” IEEE Transactions on Electronic Devices, vol. 60, pp. 2186 - 2193, July 2013. [ paper ]
[5] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “Proceed: A pareto optimization-based circuit-level evaluator for emerging devices,” IEEE Transactions on Very Large Scale Integration Systems, 2015. [ paper ]
[6] G. Leung, S. Wang, A. Pan, P. Gupta, and C. O. Chui, “An Evaluation Framework for Nanotransfer Printing Based Feature-Level Heterogeneous Integration in VLSI Circuits,” IEEE Transactions on Very Large Scale Integration Systems, 2016. [ paper ]
[7] S. Wang, H. Lee, F. Ebrahimi, P. K. Amiri, K. L. Wang, and P. Gupta, “Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, June 2016. [ paper ]
[8] H. Lee, C. Grezes, S. Wang, P. K. Amiri, P. Gupta, and K. L. Wang, “A Source Line Sensing (SLS) Scheme in Magnetoelectric Random Access Memory (MeRAM) for Reducing Read Disturbance and Improving Sensing Margin,” IEEE Magnetics Letters, vol. 7, 2016. [ paper ]
[9] L. Zhu, Y. Badr, S. Wang, S. Iyer, and P. Gupta, “Assessing Benefits of a Buried Interconnect Layer in Digital Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), May 2016. [ paper ]
[10] S. Wang, H. Hu, H. Zheng, and P. Gupta, “MEMRES: A Fast Memory System Reliability Simulator,” IEEE Transactions on Reliability, vol. 65, pp. 1783-1797, October 2016. [ paper ]
[11] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operation,” IEEE Transactions on Electronic Devices, vol. 64, 1 2017. [ paper ]
[12] C. Grezes, H. Lee, A. Lee, S. Wang, F. Ebrahimi, X. Li, K. Wong, Q. Hu, P. Gupta, P. K. Amiri, and K. L. Wang, “Write Error Rate and Read Disturbance in Electric-Field-Controlled MRAM,” IEEE Magnetic Letters, vol. 8, 2017. [ paper ]
[13] H. Lee, A. Lee, S. Wang, F. Ebrahimi, P. Gupta, P. K. Amiri, and K. L. Wang, “A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory,” IEEE Transactions on Very Large Scale Integration Systems, March 2017. [ paper ]
[14] S. Wang, A. Pan, C. Grezes, P. Amiri, C. O. Chui, and P. Gupta, “Leveraging NMOS Negative Differential Resistance for Low Power, High Reliability Magnetic Memory,” IEEE Transactions on Electronic Devices, vol. PP, 8 2017. [ paper ]


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Dr. Liangzhen Lai

Contact: liangzhen AT ucla DOT edu
[1] T. B. Chan, P. Gupta, A. Kahng, and L. Lai, “DDRO: A Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,” in IEEE International Symposium on Quality Electronic Design, March 2012. [ paper | presentation ]
[2] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: A low overhead in situ on-line timing slack monitoring methodology,” in IEEE/ACM Design, Automation and Test in Europe, March 2013. [ paper | presentation ]
[3] L. Wanner, S. Elmalaki, L. Lai, P. Gupta, and M. Srivastava, “VarEMU: An Emulation Testbed for Variability-Aware Software,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, October 2013. [ paper ]
[4] L. Lai, V. Chandra, and P. Gupta, “Evaluating and Exploiting Impacts of Dynamic Power Management Schemes on System Reliability,” in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), October 2015. [ paper | presentation ]
[5] Q. Zhang, L. Lai, M. Gottscho, and P. Gupta, “Multi-Story Power Distribution Networks for GPUs,” in IEEE/ACM Design, Automation and Test in Europe, March 2016. [ paper | presentation ]
[6] L. Lai and P. Gupta, “Hardware Reliability Margining for the Dark Silicon Era,” in Proc. Asia and South Pacific Design Automation Conference, January 2016. [ paper | presentation ]
[7] L. Lai and P. Gupta, “Accurate and inexpensive performance monitoring for variability-aware systems,” in Proc. Asia and South Pacific Design Automation Conference, pp. 467-473, Jan 2014. [ paper ]
[8] G. Leung, L. Lai, P. Gupta, and C. O. Chui, “Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32nm Finfet Technologies,” IEEE Transactions on Electronic Devices, vol. 59, pp. 2057 -2063, aug. 2012. [ paper ]
[9] T.-B. Chan, P. Gupta, A. B. Kahng, and L. Lai, “Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors,” IEEE Transactions on Very Large Scale Integration Systems, 2013. [ paper ]
[10] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “BTI-Gater: An Aging-Resilient Clock Gating Methodology,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, pp. 180-189, June 2014. [ paper ]
[11] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, pp. 1168-1179, Aug 2014. [ paper ]
[12] L. Wanner, L. Lai, A. Rahimi, M. Gottscho, P. Mercati, C.-H. Huang, F. Sala, Y. Agarwal, L. Dolecek, N. Dutt, P. Gupta, R. Gupta, R. Jhala, R. Kumar, S. Lerner, M. Subhasish, A. Nicolau, T. S. Rosing, M. B. Srivastava, S. Swanson, D. Sylvester, and Y. Zhou, “NSF Expedition on Variability-Aware Software: Recent Results and Contributions,” De Gruyter Information Technology (it), vol. 57, pp. 181-198, June 2015. [ paper ]
[13] L. Lai and P. Gupta, “System-level Dynamic Variation Margining in Presence of Monitoring and Actuation,” IEEE Embedded System Letters, June 2017. [ paper ]


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Dr. Abde Ali Kagalwalla

Contact: abdeali AT ucla DOT edu
Research interests: Computer-Aided Design of VLSI Systems, Design-for-Manufacturability, Layout Optimization, Lithography
Industry experience: Globalfoundries, Mentor Graphics, Intel
Current research project: EUV Mask Defect Avoidance Strategies, Design Rule Optimization
Publications:
[1] T.-B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” in Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration, February 2010. [ paper | presentation ]
[2] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware Mask Inspection,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2010. [ paper | presentation ]
[3] A. A. Kagalwalla, P. Gupta, D.-H. Hur, and C.-H. Park, “Defect-aware Reticle Floorplanning for EUV Masks,” in SPIE Advanced Lithography, March 2011. [ paper ]
[4] A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta, “Design-of-Experiments Based Design Rule Optimization,” in SPIE Advanced Lithography, February 2012. [ paper ]
[5] A. A. Kagalwalla, M. Lam, K. Adam, and P. Gupta, “EUV-CDA: Pattern Shift Aware Critical Density Analysis for EUV Mask Layouts,” in Proc. Asia and South Pacific Design Automation Conference, January 2014. [ paper | presentation ]
[6] A. A. Kagalwalla and P. Gupta, “Comprehensive Defect Avoidance Framework for Mitigating EUV Mask Defects,” in SPIE Advanced Lithography Symposium, March 2014. [ paper | presentation ]
[7] T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, A. B. Kahng, and E. Sahouria, “Benchmarking of Mask Fracturing Heuristics,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2014. [ paper | presentation ]
[8] A. A. Kagalwalla and P. Gupta, “Effective Model-Based Mask Fracturing for Mask Cost Reduction,” in Proc. ACM/IEEE Design Automation Conference (DAC), June 2015. [ paper | presentation ]
[9] A. Neureuther, J. Rubinstein, M. Miller, K. Y. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T.-J. K. Liu, X. Sun, K. Jeong, , P. Gupta, A. A. Kagalwalla, R. S. Ghaida, and T.-B. Chan, “Collaborative research on emerging technologies and design,” in Proc. SPIE Photomask and Next-Generation Lithography Mask Technology, 2011. [ paper ]
[10] T. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2011. [ paper ]
[11] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-Aware Mask Inspection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012. [ paper ]
[12] M. Gottscho, A. A. Kagalwalla, and P. Gupta, “Power Variability in Contemporary DRAMs,” IEEE Embedded Systems Letters, vol. 4, pp. 37-40, 2012. [ paper ]
[13] A. A. Kagalwalla and P. Gupta, “Design-Aware Defect-Avoidance Floorplanning of EUV Masks,” IEEE Transactions on Semiconductor Manufacturing, vol. 26, 2013. [ paper ]
[14] A. A. Kagalwalla and P. Gupta, “Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), vol. 13, no. 4, p. 043005, 2014. [ DOI | paper ]
[15] T. B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, and A. B. Kahng, “Benchmarking of Mask Fracturing Heuristics,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016. [ paper ]


Vishesh Dokania

Degree: M.S.
Current Coordinates: Cadence
Contact: vdokania AT ucla DOT edu
[1] V. Dokania, “Intrusive routing for improved standard cell pin access,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2017. [ paper | presentation ]


Ankur Sharma

Homepage: http://www.ee.ucla.edu/~ankur
Contact: ankursharma AT ucla DOT edu

Mukul Gupta

Contact: mukulg AT ucla DOT edu

Tanaya Sahu

Homepage: https://sites.google.com/site/tanayasahu1987
Contact: tanayasahu AT ucla DOT edu

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Aashish Pant

Homepage: http://www.ee.ucla.edu/~apant
Degree: M.S.
Current Coordinates: Mentor Graphics
Contact: apant AT ucla DOT edu
Publications:
[1] J. Sartori, A. Pant, R. Kumar, and P. Gupta, “Variation Aware Speed Binning of Multi-core Processors,” in IEEE International Symposium on Quality Electronic Design, March 2010. [ paper ]
[2] A. Pant, P. Gupta, and M. v. d. Schaar, “Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability,” in ACM Great Lakes Symposium on Very Large Scale Integration, May 2010. [ paper ]
[3] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2010. [ paper | presentation ]
[4] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,” IEEE Transactions on Semiconductor Manufacturing, 2012. [ paper ]


Amarnath Kasibhatla

Homepage: http://www.ee.ucla.edu/~amar
Degree: M.S.
Current Coordinates: Intel
Contact: amar AT ee DOT ucla DOT edu
Research interests: Power efficient Digital and Analog VLSI design and CAD for Low Power IC design
Publications:
[1] P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” in Proc. ACM/IEEE Design Automation Conference (DAC), June 2010. [ paper ]
[2] A. Kasibhatla, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]


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Charwak S Apte

Contact: charwak AT ee DOT ucla DOT edu
Research interests: Low Power Mixed-signal IC Design
Industry experience: NVIDIA Graphics Pvt Ltd, Qualcomm Inc.
Publications:
[1] L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “A Case for Opportunistic Embedded Sensing In Presence of Hardware Power Varibility,” in HotPower'10, October 2010. [ paper | presentation ]

Chia-Hao Chang

Homepage: http://www.ee.ucla.edu/~chiahao
Contact: changchiahao AT ucla DOT edu
Industry experience: Taiwan Semiconductor Manufacturing Company

Dominic Reinhard

Homepage: http://www.ee.ucla.edu/~lerong
Degree: M.S.
Current Coordinates: Western Digital
Contact: dominicr AT ucla DOT edu
M.S. Report:
[1] D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]


George Torres

Degree: B.S.
[1] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography,” in SPIE/BACUS Symposium on Photomask Technology and Management, September 2009. [ paper | presentation ]
[2] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]

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Dr. John Lee

Homepage: http://www.ee.ucla.edu/~lee
Degree: Ph.D.
Current Coordinates: TBD
Contact: lee at ee dot ucla
Publications:
[1] J. Cong, P. Gupta, and J. Lee, “On the Futlity of Statistical Power Optimization,” in Proc. Asia and South Pacific Design Automation Conference, January 2009. [ paper | presentation ]
[2] J. Lee and P. Gupta, “Incremental Gate Sizing for Late Process Changes,” in Proc. IEEE International Conference on Computer Design, October 2010. [ paper | presentation ]
[3] J. Lee, P. Gupta, and F. Pikus, “Parametric hierarchy recovery in layout extracted netlists,” in Proc. IEEE Computer Society Annual Symposium on VLSI, August 2012. [ paper | presentation ]
[4] J. Lee and P. Gupta, “Impact of range and precision in technology on cell-based design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2012. [ paper | presentation ]
[5] J. Cong, P. Gupta, and J. Lee, “Evaluating Statistical Power Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1750-1762, Nov 2010. [ paper ]


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Dr. Lerong Cheng

Homepage: http://www.ee.ucla.edu/~lerong
Degree: Ph.D.
Current Coordinates: Sandisk
Contact: lerong AT ucla DOT edu
Publications and Thesis:
[1] L. Cheng, P. Gupta, and L. He, “Accounting for Non-linear Dependence Using Function Driven Component Analysis,” in Proc. Asia and South Pacific Design Automation Conference, January 2009. [ paper ]
[2] L. Cheng, P. Gupta, K. Qian, C. Spanos, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” in Proc. ACM/IEEE Design Automation Conference (DAC), July 2009. [ paper ]
[3] L. Cheng, P. Gupta, and L. He, “On Confidence in Characterization and Application of Variation Models,” in Proc. Asia and South Pacific Design Automation Conference, January 2010. [ paper ]
[4] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2010. [ paper | presentation ]
[5] L. Cheng, P. Gupta, and L. He, “Efficient Additive Statistical Leakage Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2009. [ paper ]
[6] L. Cheng, P. Gupta, C. J. Spanos, K. Qian, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2010. [ paper ]
[7] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,” IEEE Transactions on Semiconductor Manufacturing, 2012. [ paper ]
[8] L. Cheng, Statistical Analysis and Optimization for Timing and Power of VLSI Circuits. PhD thesis, Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]


Parag Kulkarni

Degree: M.S.
Current Coordinates: Qualcomm
Contact: paragk AT ucla DOT edu
Research interests: Low Power Digital Logic/Arithmetic Design, CAD algorithms
Industry experience: Altera, Qualcomm, Cadence Design Systems

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Dr. Rani S. Ghaida

Homepage: http://nanocad.ee.ucla.edu/pub/rani
Degree: Ph.D.
Current Coordinates: GLOBALFOUNDRIES
Contact: ranighaida AT ucla DOT edu
Thesis and Publications:
[1] R. S. Ghaida and P. Gupta, “Design-Overlay Interactions in Metal Double Patterning,” in SPIE Advanced Lithography Symposium, February 2009. [ paper | presentation ]
[2] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography,” in SPIE/BACUS Symposium on Photomask Technology and Management, September 2009. [ paper | presentation ]
[3] R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic Evaluation of Design Rules,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2009. [ paper | presentation ]
[4] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A Framework for Double Patterning-Enabled Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2011. [ paper | presentation ]
[5] R. S. Ghaida, K. Agarwal, L. Liebmann, S. R. Nassif, and P. Gupta, “A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition,” in SPIE Advanced Lithography, February 2012. [ paper ]
[6] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, “A methodology for the early exploration of design rules for multiple-patterning technologies,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2012. [ paper | presentation ]
[7] R. S. Ghaida, M. Gupta, and P. Gupta, “A Framework for Exploring the Interaction between Design Rules and Overlay Control,” in SPIE Advanced Lithography, Feburary 2013. [ paper ]
[8] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, January 2014. [ paper | presentation ]
[9] T.-B. Chan, R. S. Ghaida, and P. Gupta, “Electrical Modeling of Lithographic Imperfections,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010. (embedded tutorial). [ paper | presentation ]
[10] A. Neureuther, J. Rubinstein, M. Miller, K. Y. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T.-J. K. Liu, X. Sun, K. Jeong, , P. Gupta, A. A. Kagalwalla, R. S. Ghaida, and T.-B. Chan, “Collaborative research on emerging technologies and design,” in Proc. SPIE Photomask and Next-Generation Lithography Mask Technology, 2011. [ paper ]
[11] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,” in Intl. Conf. on IC Design and Technology, June 2012. [ paper | presentation ]
[12] R. S. Ghaida and P. Gupta, “Role of design in multiple patterning: Technology development, design enablement and process control,” in IEEE/ACM Design, Automation and Test in Europe, 2013. [ paper ]
[13] R. S. Ghaida and P. Gupta, “Within-Layer Overlay Impact for Design in Metal Double Patterning,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]
[14] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]
[15] R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012. [ paper ]
[16] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, “Layout Decomposition and Legalization for Double-Patterning Technology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012. [ paper ]
[17] R. S. Ghaida, M. Gupta, and P. Gupta, “Framework for exploring the interaction between design rules and overlay control,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), vol. 12, August 2013. [ paper ]
[18] R. S. Ghaida, Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies. PhD thesis, 2012. [ paper ]


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Santiago Mok

Homepage: http://www.ee.ucla.edu/~smok
Degree: M.S.
Current Coordinates: Altera
Contact: smok AT ee DOT ucla DOT edu

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Tuck Boon Chan

Homepage: http://www.ee.ucla.edu/~tuckie
Current Coordinates: UCSD
Contact: tuckie AT ucla DOT edu
Publications:
[1] T.-B. Chan and P. Gupta, “On Electrical Modeling of Imperfect Diffusion Patterning,” in Proc. IEEE/ACM International Conference on VLSI Design, January 2010. [ paper | presentation ]
[2] T.-B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” in Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration, February 2010. [ paper | presentation ]
[3] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2010. [ paper | presentation ]
[4] T.-B. Chan, J. Sartori, P. Gupta, and R. Kumar, “On the Efficacy of NBTI Mitigation Techniques,” in Design, Automation, and Test in Europe (DATE), March 2011. [ paper | presentation ]
[5] T.-B. Chan, R. S. Ghaida, and P. Gupta, “Electrical Modeling of Lithographic Imperfections,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010. (embedded tutorial). [ paper | presentation ]


Viswakiran Popuri

Degree: M.S.
Current Coordinates: Sandisk
Contact: viswa AT ee DOT ucla DOT edu
Research interests: Analog/Mixed-signal IC Design and CAD
M.S. Report:
[1] V. Popuri, “Bias-driven Robust Analog Circuit Sizing Scheme,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2009. [ paper ]



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