Login

Research

Teaching

NanoCAD Group

Internal

Lab Members

Updated Sep. 13 2012

Faculty (Principal Investigator)

puneetgupta_small.jpg

Prof. Puneet Gupta
Homepage: http://www.ee.ucla.edu/~puneet
Contact: puneet AT ee DOT ucla DOT edu
Publications

Ph.D

abdeali_bigsur.jpg

Abde Ali Kagalwalla
Homepage: http://www.ee.ucla.edu/~abdeali
Contact: abdeali AT ucla DOT edu
Research interests: Computer-Aided Design of VLSI Systems, Design-for-Manufacturability, Layout Optimization, Lithography
Industry experience: Globalfoundries, Mentor Graphics
Current research project: EUV Mask Defect Avoidance Strategies, Design Rule Optimization
Publications:
[1] T.-B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” in Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration, February 2010. [ paper | presentation ]
[2] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-aware Mask Inspection,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2010. [ paper | presentation ]
[3] A. A. Kagalwalla, P. Gupta, D.-H. Hur, and C.-H. Park, “Defect-aware Reticle Floorplanning for EUV Masks,” in SPIE Advanced Lithography, March 2011. [ paper ]
[4] A. A. Kagalwalla, S. Muddu, L. Capodieci, C. Zelnik, and P. Gupta, “Design-of-Experiments Based Design Rule Optimization,” in SPIE Advanced Lithography, February 2012. [ paper ]
[5] T. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2011. [ paper ]
[6] A. A. Kagalwalla, P. Gupta, C. Progler, and S. McDonald, “Design-Aware Mask Inspection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]
[7] M. Gottscho, A. A. Kagalwalla, and P. Gupta, “Power Variability in Contemporary DRAMs,” IEEE Embedded Systems Letters, 2012. [ paper ]
[8] A. A. Kagalwalla and P. Gupta, “Design-Aware Defect-Avoidance Floorplanning of EUV Masks,” IEEE Transactions on Semiconductor Manufacturing, 2013. Accepted for publication. [ paper ]


Liangzhen Lai
Homepage: http://www.ee.ucla.edu/~liangzhe
Contact: liangzhen AT ucla DOT edu
[1] T. B. Chan, P. Gupta, A. Kahng, and L. Lai, “DDRO: A Noval Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,” in IEEE International Symposium on Quality Electronic Design, 2012. [ paper | presentation ]
[2] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: A low overhead in situ on-line timing slack monitoring methodology,” in IEEE/ACM Design, Automation and Test in Europe, March 2013. [ paper | presentation ]
[3] G. Leung, L. Lai, P. Gupta, and C. O. Chui, “Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32nm Finfet Technologies,” IEEE Transactions on Electronic Devices, vol. 59, pp. 2057 -2063, aug. 2012. [ paper ]


DSC_9285.jpg

Mark Gottscho
Contact: mgottscho@ucla.edu
Homepage: http://www.ee.ucla.edu/~mgottscho/
Research interests: Hardware/software interface, energy-efficient embedded systems
Industry experience: Altera Corporation, National Aeronautics and Space Administration (NASA)
Current research project: Variability-aware Linux kernel for reduction of memory power consumption.
[1] L. Bathen, M. Gottscho, N. Dutt, P. Gupta, and A. Nicolau, “ViPZonE: OS-level memory variability-aware physical address zoning for energy savings,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, Oct 2012. [ paper ]
[2] N. Dutt, P. Gupta, A. Nicolau, L. Bathen, and M. Gottscho, “Variability-aware memory management for nanoscale computing,” in Proc. Asia and South Pacific Design Automation Conference, 2013. to appear. [ paper ]
[3] M. Gottscho, A. A. Kagalwalla, and P. Gupta, “Power Variability in Contemporary DRAMs,” IEEE Embedded Systems Letters, 2012. [ paper ]


shaodi.JPG

Shaodi Wang
Contact: shaodiwang AT ee DOT ucla DOT edu
Research interests: Design for manufacturing modeling, novel device modeling and circuit analysis.
Current projects:
Circuit-level Junctionless device LER effect
Tunneling FET circuit analysis

YasmineBadr.jpg

Yasmine Badr
Contact: ybadr AT ucla DOT edu

M.S.

Ankur Sharma
Homepage: http://www.ee.ucla.edu/~ankur
Contact: ankursharma AT ucla DOT edu

Mukul Gupta
Contact: mukulg AT ucla DOT edu

Tanaya Sahu
Homepage: https://sites.google.com/site/tanayasahu1987
Contact: tanayasahu AT ucla DOT edu

Undergraduate

Alumni

pic.JPG

Aashish Pant
Homepage: http://www.ee.ucla.edu/~apant
Degree: M.S.
Current Coordinates: Mentor Graphics
Contact: apant AT ucla DOT edu
Publications:
[1] J. Sartori, A. Pant, R. Kumar, and P. Gupta, “Variation Aware Speed Binning of Multi-core Processors,” in IEEE International Symposium on Quality Electronic Design, March 2010. [ paper ]
[2] A. Pant, P. Gupta, and M. v. d. Schaar, “Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability,” in ACM Great Lakes Symposium on Very Large Scale Integration, May 2010. [ paper ]
[3] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2010. [ paper | presentation ]
[4] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,” IEEE Transactions on Semiconductor Manufacturing, 2012. [ paper ]


Amarnath Kasibhatla

Homepage: http://www.ee.ucla.edu/~amar
Degree: M.S.
Current Coordinates: Intel
Contact: amar AT ee DOT ucla DOT edu
Research interests: Power efficient Digital and Analog VLSI design and CAD for Low Power IC design
Publications:
[1] P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” in Proc. ACM/IEEE Design Automation Conference, June 2010. [ paper ]
[2] A. Kasibhatla, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]


charwak.bmp

Charwak S Apte
Contact: charwak AT ee DOT ucla DOT edu
Research interests: Low Power Mixed-signal IC Design
Industry experience: NVIDIA Graphics Pvt Ltd, Qualcomm Inc.
Publications:
[1] L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “A Case for Opportunistic Embedded Sensing In Presence of Hardware Power Varibility,” in HotPower'10, 2010. [ paper | presentation ]

Chia-Hao Chang
Homepage: http://www.ee.ucla.edu/~chiahao
Contact: changchiahao AT ucla DOT edu
Industry experience: Taiwan Semiconductor Manufacturing Company

Dominic Reinhard
Homepage: http://www.ee.ucla.edu/~lerong
Degree: M.S.
Current Coordinates: Western Digital
Contact: dominicr AT ucla DOT edu
M.S. Report:
[1] D. Reinhard, “On Comparing Conventional and Electrically Driven OPC Techniques,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]


George Torres

Degree: B.S.
[1] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography,” in SPIE/BACUS Symposium on Photomask Technology and Management, September 2009. [ paper | presentation ]
[2] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]

john_lee.JPG

John Lee
Homepage: http://www.ee.ucla.edu/~lee
Degree: Ph.D.
Current Coordinates: TBD
Contact: lee at ee dot ucla
Publications:
[1] J. Cong, P. Gupta, and J. Lee, “On the Futlity of Statistical Power Optimization,” in Proc. Asia and South Pacific Design Automation Conference, January 2009. [ paper | presentation ]
[2] J. Lee and P. Gupta, “Incremental Gate Sizing for Late Process Changes,” in Proc. IEEE International Conference on Computer Design, Oct 2010. [ paper | presentation ]
[3] J. Lee, P. Gupta, and F. Pikus, “Parametric hierarchy recovery in layout extracted netlists,” in Proc. IEEE Computer Society Annual Symposium on VLSI, August 2012. [ paper | presentation ]
[4] J. Lee and P. Gupta, “Impact of range and precision in technology on cell-based design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2012. [ paper | presentation ]
[5] J. Cong, P. Gupta, and J. Lee, “Evaluating Statistical Power Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1750-1762, Nov 2010. [ paper ]


lerong.jpg

Lerong Cheng
Homepage: http://www.ee.ucla.edu/~lerong
Degree: Ph.D.
Current Coordinates: Sandisk
Contact: lerong AT ucla DOT edu
Publications and Thesis:
[1] L. Cheng, P. Gupta, and L. He, “Accounting for Non-linear Dependence Using Function Driven Component Analysis,” in Proc. Asia and South Pacific Design Automation Conference, January 2009. [ paper ]
[2] L. Cheng, P. Gupta, K. Qian, C. Spanos, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” in Proc. ACM/IEEE Design Automation Conference, 2009. [ paper ]
[3] L. Cheng, P. Gupta, and L. He, “On Confidence in Characterization and Application of Variation Models,” in Proc. Asia and South Pacific Design Automation Conference, January 2010. [ paper ]
[4] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2010. [ paper | presentation ]
[5] L. Cheng, P. Gupta, and L. He, “Efficient Additive Statistical Leakage Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009. [ paper ]
[6] L. Cheng, P. Gupta, C. J. Spanos, K. Qian, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010. [ paper ]
[7] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction,” IEEE Transactions on Semiconductor Manufacturing, 2012. [ paper ]
[8] L. Cheng, Statistical Analysis and Optimization for Timing and Power of VLSI Circuits. PhD thesis, Department of Electrical Engineering, University of California Los Angeles, 2010. [ paper ]


Parag Kulkarni
Degree: M.S.
Current Coordinates: Qualcomm
Contact: paragk AT ucla DOT edu
Research interests: Low Power Digital Logic/Arithmetic Design, CAD algorithms
Industry experience: Altera, Qualcomm, Cadence Design Systems

rani.JPG

Rani S. Ghaida
Homepage: http://www.ee.ucla.edu/~rani
Contact: rani AT ee DOT ucla DOT edu
Research interests: design for manufacturability/yield/reliability, design-manufacturing interface, and system-level modeling.
Current projects:
* Design rules evaluation and exploration
* Design/manufacturing techniques for efficient double-patterning lithography
* System-level modeling of area/variability tradeoffs
Publications:
[1] R. S. Ghaida and P. Gupta, “Design-Overlay Interactions in Metal Double Patterning,” in SPIE Advanced Lithography Symposium, February 2009. [ paper | presentation ]
[2] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography,” in SPIE/BACUS Symposium on Photomask Technology and Management, September 2009. [ paper | presentation ]
[3] R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic Evaluation of Design Rules,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2009. [ paper | presentation ]
[4] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A Framework for Double Patterning-Enabled Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2011. [ paper | presentation ]
[5] R. S. Ghaida, K. Agarwal, L. Liebmann, S. R. Nassif, and P. Gupta, “A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition,” in SPIE Advanced Lithography, February 2012. [ paper ]
[6] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, “A methodology for the early exploration of design rules for multiple-patterning technologies,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2012. [ paper | presentation ]
[7] T.-B. Chan, R. S. Ghaida, and P. Gupta, “Electrical Modeling of Lithographic Imperfections,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010. (embedded tutorial). [ paper | presentation ]
[8] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,” in Intl. Conf. on IC Design and Technology, June 2012. [ paper | presentation ]
[9] R. S. Ghaida and P. Gupta, “Within-Layer Overlay Impact for Design in Metal Double Patterning,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]
[10] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control,” IEEE Transactions on Semiconductor Manufacturing, 2010. [ paper ]
[11] R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]
[12] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, “Layout Decomposition and Legalization for Double-Patterning Technology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]


Santiago.JPG

Santiago Mok
Homepage: http://www.ee.ucla.edu/~smok
Degree: M.S.
Current Coordinates: Altera
Contact: smok AT ee DOT ucla DOT edu

tuckie.jpg

Tuck Boon. Chan
Homepage: http://www.ee.ucla.edu/~tuckie
Current Coordinates: UCSD
Contact: tuckie AT ucla DOT edu
Publications:
[1] T.-B. Chan and P. Gupta, “On Electrical Modeling of Imperfect Diffusion Patterning,” in Proc. IEEE/ACM International Conference on VLSI Design, January 2010. [ paper | presentation ]
[2] T.-B. Chan, A. A. Kagalwalla, and P. Gupta, “Measurement and Optimization of Electrical Process Window,” in Proc. SPIE Conference on Design for Manufacturability through Design-Process Integration, February 2010. [ paper | presentation ]
[3] T.-B. Chan, A. Pant, L. Cheng, and P. Gupta, “Design Dependent Process Monitoring for Back-end Manufacturing Cost Reduction,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2010. [ paper | presentation ]
[4] T.-B. Chan, J. Sartori, P. Gupta, and R. Kumar, “On the Efficacy of NBTI Mitigation Techniques,” in Design, Automation, and Test in Europe (DATE), March 2011. [ paper | presentation ]
[5] T.-B. Chan, R. S. Ghaida, and P. Gupta, “Electrical Modeling of Lithographic Imperfections,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010. (embedded tutorial). [ paper | presentation ]


Viswakiran Popuri

Degree: M.S.
Current Coordinates: Sandisk
Contact: viswa AT ee DOT ucla DOT edu
Research interests: Analog/Mixed-signal IC Design and CAD
M.S. Report:
[1] V. Popuri, “Bias-driven Robust Analog Circuit Sizing Scheme,” tech. rep., Department of Electrical Engineering, University of California Los Angeles, 2009. [ paper ]



Copyright (C) 2013 NanoCAD. All Rights Reserved.
For questions and feedbacks, contact Webmaster