Downloads

Note that we have public source code repositories hosted at https://github.com/nanocad-lab. Research data is available upon request. For downloads of research data, please contact the authors of the relevant paper, or email Prof. Puneet Gupta directly.

Software Descriptions:

UCLA_EUV CDA_

UCLA_EUV_CDA is a tool written in C++ for computing the mask yield of EUV layouts while accounting for EUV mask blank defect avoidance techniques like pattern sift and rotation. EUV CDA

DSA_pathfind

DSA_pathfind is a framework for DSA technology path-finding, for via layers, to be used by the foundry as part of Design and Technology Co-optimization (DTCO). The framework optimally evaluates a DSA-based technology where an arbitrary lithography technique is used to print the guiding templates, possibly using many masks/exposures and provides a design-friendliness metric. In addition, if the evaluated technology is not design-friendly, the framework provides a diagnosis of the failures, and computes the minimum-cost technology change that makes the technology design-friendly.

X-Mem

X-Mem is a flexible software tool for characterizing modern memory hierarchies in a variety of ways. The tool was developed jointly by Microsoft and our lab to address emerging challenges particular to cloud computing. X-Mem was originally authored by lab member Mark Gottscho as a Summer 2014 Ph.D. intern at Microsoft Research. To benefit the research and development community, we have open-sourced the code under the MIT License. Project homepage: https://nanocad-lab.github.io/X-Mem

X-Mem Online Plotter: Click Here

UCLA_DRE

UCLA_DRE is a tool written in C++ that essentially creates a virtual standard-cell library for evaluating and exploring design rules, technology choices, and layout methodologies in terms of area, yield, and variability. A chip-level evaluation of design rules now also exists.
Publications:
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PROCEED

PROCEED is a tool written in MATLAB for evaluating and exploring emerging Boolean devices in the context of circuit designs. The tool takes a device model (compatible with SPICE) and logic depth histogram of a digital circuit as input and evaluates trade-off of power, minimum working clock period, and area of the digital circuit design. It models and performs circuit optimizations including picking best supply voltage and threshold voltage, gate sizing, and dynamic voltage and frequency scaling. It outputs metrics of design power, minimum working clock period, and design area inwide ranges (up to several orders of magnitudes).
Publications:
BibtexPlugin Errors:
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MRAM_Switching_Model

MRAM_Switching_Model is a Monte-Carlo simulator, which can simulate the switching behavior and failure rate of the STT-MTJ and the VC-MTJ. It is a LLG equation based model including voltage-controlled magnetic anisotropy effect, Spin-transfer torque effect, temperature dependence, and thermal fluctuation. The model is written in C++ and CUDA. If you use this software or a modified version of it, please cite the most relevant among the following papers:
Publications:
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UCLA_TIMER

UCLA_TIMER: An enhanced OAGear-Static-Timer with SPEF-reading, Elmore-based wire delay calculation, power calculation, and Greedy Heuristic for Gate Sizing.

UCLA_SHAPE

uclaShape: uclaShape API is an extension of oaShape in Open Access, It is implemented by boost library 1.45.0. and Open Access.It allows users to do basic operations between layers that Open Access API does not provide.

RDSim

An efficient Reaction-diffusion model to simulate NBTI degradation.
Publications:
BibtexPlugin Errors:
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UCLA_Eyecharts

UCLA_Eyecharts is a tool to generate benchmark circuits (called eyecharts) of arbitrary size along with their optimal solutions calculated using dynamic programming. The tool evaluates the suboptimalities of some popular gate sizing algorithms and helps diagnose weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research.
Publications:
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UCLA_ENCOUNTER_TCL_SIZING

UCLA_ENCOUNTER_TCL_SIZING: Implementations of greedy and LP slack assignment heuristics for gate sizing. Implemented in TCL for Cadence Encounter. Methods implemented are:

Greedy Sizing Power: Sizing method similar to TILOS (Fishburn and Dunlop, "TILOS: a Posynomial Programming Approach to Transistor Sizing", 1985). Starts with a timing-infeasible design, and iteratively sizes the critical path using a greedy Delay/Power metric until the design is timing-feasible.

Greedy Sizing Recover Power: Starts with a timing-feasible design, and trades power for slack using a greedy Power/Delay metric until no improvements are possible. See tech report for more details.

LP Slack Allocation: Starts with a timing-feasible design, and iterates between allocating slack using linear programming, and converting the allocated slacks for power savings using gate sizing. This implementation follows the work in Nguyen, Davare, Orshansky, Chinnery, Thompson, and Keutzer, "Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization," 2003.

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