Note that we have public source code repositories hosted at Research data is available upon request. For downloads of research data, please contact the authors of the relevant paper, or email Prof. Puneet Gupta directly.

Software Descriptions:


UCLA_EUV_CDA is a tool written in C++ for computing the mask yield of EUV layouts while accounting for EUV mask blank defect avoidance techniques like pattern sift and rotation. EUV CDA


DSA_pathfind is a framework for DSA technology path-finding, for via layers, to be used by the foundry as part of Design and Technology Co-optimization (DTCO). The framework optimally evaluates a DSA-based technology where an arbitrary lithography technique is used to print the guiding templates, possibly using many masks/exposures and provides a design-friendliness metric. In addition, if the evaluated technology is not design-friendly, the framework provides a diagnosis of the failures, and computes the minimum-cost technology change that makes the technology design-friendly.


X-Mem is a flexible software tool for characterizing modern memory hierarchies in a variety of ways. The tool was developed jointly by Microsoft and our lab to address emerging challenges particular to cloud computing. X-Mem was originally authored by lab member Mark Gottscho as a Summer 2014 Ph.D. intern at Microsoft Research. To benefit the research and development community, we have open-sourced the code under the MIT License. Project homepage:

X-Mem Online Plotter: Click Here


UCLA_DRE is a tool written in C++ that essentially creates a virtual standard-cell library for evaluating and exploring design rules, technology choices, and layout methodologies in terms of area, yield, and variability. A chip-level evaluation of design rules now also exists.
[1] R. S. Ghaida and P. Gupta, “A Framework for Early and Systematic Evaluation of Design Rules,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2009. [ paper | presentation ]
[2] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “A Framework for Double Patterning-Enabled Design,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2011. [ paper | presentation ]
[3] R. S. Ghaida, T. Sahu, P. Kulkarni, and P. Gupta, “A methodology for the early exploration of design rules for multiple-patterning technologies,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2012. [ paper | presentation ]
[4] R. S. Ghaida, M. Gupta, and P. Gupta, “A Framework for Exploring the Interaction between Design Rules and Overlay Control,” in SPIE Advanced Lithography, Feburary 2013. [ paper ]
[5] R. S. Ghaida, Y. Badr, M. Gupta, N. Jin, and P. Gupta, “Comprehensive Die-level Assessment of Design Rules and Layouts,” in Proc. Asia and South Pacific Design Automation Conference, January 2014. [ paper | presentation ]
[6] R. S. Ghaida, K. Agarwal, S. Nassif, X. Yuan, L. Liebmann, and P. Gupta, “O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction,” in Intl. Conf. on IC Design and Technology, June 2012. [ paper | presentation ]
[7] R. S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]
[8] R. S. Ghaida, K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta, “Layout Decomposition and Legalization for Double-Patterning Technology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. [ paper ]


PROCEED is a tool written in MATLAB for evaluating and exploring emerging Boolean devices in the context of circuit designs. The tool takes a device model (compatible with SPICE) and logic depth histogram of a digital circuit as input and evaluates trade-off of power, minimum working clock period, and area of the digital circuit design. It models and performs circuit optimizations including picking best supply voltage and threshold voltage, gate sizing, and dynamic voltage and frequency scaling. It outputs metrics of design power, minimum working clock period, and design area inwide ranges (up to several orders of magnitudes).
[1] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “PROCEED: a Pareto Optimization-based Circuit-level Evaluator for Emerging Devices,” in Proc. Asia and South Pacific Design Automation Conference, January 2014. [ paper | presentation ]
[2] S. Wang, A. Pan, C. O. Chui, and P. Gupta, “Proceed: A pareto optimization-based circuit-level evaluator for emerging devices,” IEEE Transactions on Very Large Scale Integration Systems, 2015. [ paper ]


MRAM_Switching_Model is a Monte-Carlo simulator, which can simulate the switching behavior and failure rate of the STT-MTJ and the VC-MTJ. It is a LLG equation based model including voltage-controlled magnetic anisotropy effect, Spin-transfer torque effect, temperature dependence, and thermal fluctuation. The model is written in C++ and CUDA. If you use this software or a modified version of it, please cite the most relevant among the following papers:
[1] S. Wang, H. Lee, F. Ebrahimi, P. K. Amiri, K. L. Wang, and P. Gupta, “Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, June 2016. [ paper ]


UCLA_TIMER: An enhanced OAGear-Static-Timer with SPEF-reading, Elmore-based wire delay calculation, power calculation, and Greedy Heuristic for Gate Sizing.


uclaShape: uclaShape API is an extension of oaShape in Open Access, It is implemented by boost library 1.45.0. and Open Access.It allows users to do basic operations between layers that Open Access API does not provide.


An efficient Reaction-diffusion model to simulate NBTI degradation.
[1] T.-B. Chan, J. Sartori, P. Gupta, and R. Kumar, “On the Efficacy of NBTI Mitigation Techniques,” in Design, Automation, and Test in Europe (DATE), March 2011. [ paper | presentation ]


UCLA_Eyecharts is a tool to generate benchmark circuits (called eyecharts) of arbitrary size along with their optimal solutions calculated using dynamic programming. The tool evaluates the suboptimalities of some popular gate sizing algorithms and helps diagnose weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research.
[1] P. Gupta, A. Kahng, A. Kasibhatla, and P. Sharma, “Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics,” in Proc. ACM/IEEE Design Automation Conference, June 2010. [ paper ]


UCLA_ENCOUNTER_TCL_SIZING: Implementations of greedy and LP slack assignment heuristics for gate sizing. Implemented in TCL for Cadence Encounter. Methods implemented are:

Greedy Sizing Power: Sizing method similar to TILOS (Fishburn and Dunlop, "TILOS: a Posynomial Programming Approach to Transistor Sizing", 1985). Starts with a timing-infeasible design, and iteratively sizes the critical path using a greedy Delay/Power metric until the design is timing-feasible.

Greedy Sizing Recover Power: Starts with a timing-feasible design, and trades power for slack using a greedy Power/Delay metric until no improvements are possible. See tech report for more details.

LP Slack Allocation: Starts with a timing-feasible design, and iterates between allocating slack using linear programming, and converting the allocated slacks for power savings using gate sizing. This implementation follows the work in Nguyen, Davare, Orshansky, Chinnery, Thompson, and Keutzer, "Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization," 2003.

To download the software, simply fill out this form:

Fields marked ** are required
First Name: **
Last Name: **
E-mail address: **
Affiliation: **
Software: **

Copyright (C) 2017 NanoCAD. All Rights Reserved.
For questions and feedbacks, contact Webmaster