Manufacturing Aware Design

 For design for manufacturing (DFM) models and methods to be  defensible  and  adoptable,  they  have  to  be  as  simple  as  possible  without  losing  physical  justification.  Our  ongoing  research  is  re-evaluating  several  assumptions  that  CAD  research  has  made  in  recent  years  to  avoid  "DFM  overkill".  Starting from a deep understanding of the makeup of different physical phenomena that lead to the observed electrical variability, we have developed variability models and methods in physical design to deal with patterning constraints.

Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across-Wafer Variability*

Objective: Modeling spatial variation is important for statistical analysis. In practice, all of which indicate that spatial variation comes from deterministic across-wafer variation, and purely random spatial variation is not significant. We analytically study the impact of across-wafer variation and show how it gives an appearance of correlation. We have developed a new die-level variation model considering deterministic across-wafer variation and derived the range of conditions under which ignoring spatial variation altogether may be acceptable.

Package: Spatial_detect is a Matlab script to extract across-wafer variation from measurement data. It assumes the across wafer variation to be a quadratic function. In this detection, we have two different spatial variation models: 1) Random field based spatial variation model [1, 2]; 2) Modeling across-wafer variation [3]. In practice, modeling across-wafer variation is more accurate and efficient than the random field based spatial variation model. The current release includes source code, user manual, and sample input files.

By: Lerong Cheng, advised by Prof. Puneet Gupta

Publications List:

[1] R. Puri, N. Charudhattan, S. Saha, S. Rangarajan, R. Rao, and P. Gupta, “Design of deep sub-micron cmos circuit and design methodologies for high performance microprocessors,” in IEEE International Conference on VLSI Design, 2013. Tutorial.
[2] P. Gupta, “Design-assisted semiconductor manufacturing,” in IEEE International Symposium on Quality Electronic Design, 2012. Short tutorial.
[3] A. Neureuther, J. Rubinstein, M. Miller, K. Y. E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T.-J. K. Liu, X. Sun, K. Jeong, , P. Gupta, A. A. Kagalwalla, R. S. Ghaida, and T.-B. Chan, “Collaborative research on emerging technologies and design,” in Proc. SPIE Photomask and Next-Generation Lithography Mask Technology, 2011. [ paper ]
[4] P. Gupta, “Designing for uncertainty: Addressing process variations and aging issues in vlsi designs,” in IEEE International Symposium on VLSI Design, Automation and Test, 2011. (tutorial). [ presentation ]
[5] P. Gupta, “Variability and reliability: Will they get better or worse in future cmos technologies ?,” in IEEE Workshop on Design for Reliability and Variability, 2011. (Panel Discussion).
[6] J. Lee and P. Gupta, “Incremental Gate Sizing for Late Process Changes,” in Proc. IEEE International Conference on Computer Design, October 2010. [ paper | presentation ]
[7] T.-B. Chan and P. Gupta, “On Electrical Modeling of Imperfect Diffusion Patterning,” in Proc. IEEE/ACM International Conference on VLSI Design, January 2010. [ paper | presentation ]
[8] L. Cheng, P. Gupta, and L. He, “On Confidence in Characterization and Application of Variation Models,” in Proc. Asia and South Pacific Design Automation Conference, January 2010. [ paper ]
[9] T.-B. Chan, R. S. Ghaida, and P. Gupta, “Electrical Modeling of Lithographic Imperfections,” in Proc. IEEE/ACM International Conference on VLSI Design, 2010. (embedded tutorial). [ paper | presentation ]
[10] P. Gupta, “Modeling performance impact of variability,” in NSF/SRC The International Variability Characterization Workshop, 2010. (invited talk).
[11] P. Gupta, K. Jeong, A. Kahng, and C.-H. Park, “Electrical Assessment of Lithographic Gate Line-End Patterning,” SPIE Journal of Microlithography, Microfabrication and Microsystems, 2010. [ paper ]
[12] J. Cong, P. Gupta, and J. Lee, “Evaluating Statistical Power Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1750-1762, Nov 2010. [ paper ]
[13] L. Cheng, P. Gupta, C. J. Spanos, K. Qian, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010. [ paper ]
[14] L. Cheng, P. Gupta, K. Qian, C. Spanos, and L. He, “Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability,” in Proc. ACM/IEEE Design Automation Conference, July 2009. [ paper ]
[15] J. Cong, P. Gupta, and J. Lee, “On the Futlity of Statistical Power Optimization,” in Proc. Asia and South Pacific Design Automation Conference, January 2009. [ paper | presentation ]
[16] L. Cheng, P. Gupta, and L. He, “Accounting for Non-linear Dependence Using Function Driven Component Analysis,” in Proc. Asia and South Pacific Design Automation Conference, January 2009. [ paper ]
[17] P. Gupta, “Revisiting variation models and their reliability,” in IEEE/ACM Workshop on Variability Modeling and Characterization, 2009. (invited talk).
[18] P. Gupta, “Design for ultra-low-k1 patterning and manufacturing,” in IEEE International Conference on Microelectronic Teststructures (ICMTS), 2009. tutorial.
[19] L. Cheng, P. Gupta, and L. He, “Efficient Additive Statistical Leakage Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009. [ paper ]
[20] P. Gupta and A. B. Kahng, “Bounded Lifetime Integrated Circuits,” in Proc. ACM/IEEE Design Automation Conference, June 2008. [ paper ]
[21] P. Gupta, K. Jeong, A. B. Kahng, and C.-H. Park, “Electrical Metrics for Lithographic Line-End Tapering,” in SPIE Photomask and NGL Mask Technology, April 2008. [ paper ]
[22] P. Gupta, A. B. Kahng, S. Shah, and D. Sylvester, “Shaping Gate Channels for Improved Devices,” in SPIE Advanced Lithography Symposium, February 2008. [ paper ]
[23] P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Investigation of Diffusion Rounding for Post-Lithography Analysis,” in Proc. Asia and South Pacific Design Automation Conference, January 2008. [ paper ]
[24] P. Gupta, “The Electrical Design Manufacturing Interface,” in Electronic Design Processes Workshop, 2008.
[25] P. Gupta and C. Wu, “Lithography and Memories: From Shapes to Electrical,” in IEEE VLSI Test Symposium, 2008.
[26] D. Chidambarrao, P. Gupta, P. Elakkumanan, L. Liebmann, D. Marculescu, and N. Tamarapalli, “DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction,” in Proc. ACM/IEEE Design Automation Conference, 2008. (full-day tutorial).
[27] P. Gupta, “Challenges at 45nm and Beyond,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, 2008. (panel discussion).
[28] P. Gupta, A. B. Kahng, and C.-H. Park, “Detailed Placement for Enhanced Control of Resist and Etch CDs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2007. [ paper ]
[29] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, September 2007. [ paper ]
[30] P. Gupta, A. B. Kahng, Y. Kim, and S. Shah, “Line End Shortening is not Always a Failure,” in Proc. ACM/IEEE Design Automation Conference, June 2007. [ paper ]
[31] P. Gupta and R. Puri, “Impact of Variability On VLSI Circuits,” in SPIE Advanced Lithography Symposium, 2007. (short course).
[32] P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, “Gate-Length Biasing for Runtime Leakage Control,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 2006. [ paper ]
[33] P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah, and P. Sharma, “Lithography Simulation-Based Full-Chip Design Analyses,” in SPIE Microlithography, February 2006. [ paper ]
[34] P. Gupta, A. B. Kahng, Y. Kim, S. Shah, and D. Sylvester, “Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis,” in SPIE Microlithography, February 2006. [ paper ]
[35] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation,” in SPIE Microlithography, February 2006. [ paper ]
[36] P. Gupta and A. B. Kahng, “Efficient Design and Analysis of Robust Power Distribution Meshes,” in Proc. IEEE/ACM International Conference on VLSI Design, January 2006. [ paper ]
[37] P. Gupta, A. B. Kahng, S. Muddu, and N. S., “Modeling Edge Placement Error Distribution in Standard Cell Library,” in SPIE Microlithography, January 2006. [ paper ]
[38] P. Gupta, A. B. Kahng, and C.-H. Park, “Enhanced Resist and Etch CD Control by Design Perturbation,” in SPIE/BACUS Symposium on Photomask Technology and Management, October 2005. [ paper ]
[39] P. Gupta, A. B. Kahng, O. Nakagawa, and K. Samadi, “Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing,” in Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf., October 2005. (invited paper). [ paper ]
[40] P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Focus Variation,” in Proc. ACM/IEEE Design Automation Conference, June 2005. [ paper ]
[41] P. Gupta, A. B. Kahng, and C.-H. Park, “Manufacturing-Aware Design Methodology for Assist Feature Correctness,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, March 2005. [ paper ]
[42] P. Gupta, F.-L. Heng, and J.-F. Lee, “Toward Through-Process Layout Quality Metrics,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, March 2005. [ paper ]
[43] P. Gupta, A. B. Kahng, and C.-H. Park, “Detailed Placement for Improved Depth of Focus and CD Control,” in Proc. Asia and South Pacific Design Automation Conference, January 2005. [ paper ]
[44] P. Gupta and A. B. Kahng, “CMP and DFM,” in CMP-MIC, 2005. (Short Tutorial).
[45] P. Gupta, “DFM Fundamentals,” in WesCon, 2005. (short tutorial).
[46] P. Gupta and F.-L. Heng, “Toward a Systematic-Variation Aware Timing Methodology,” in Proc. ACM/IEEE Design Automation Conference, July 2004. [ paper ]
[47] P. Gupta, A. B. Kahng, P. Sharma, and D. D. Sylvester, “Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Reduction,” in Proc. ACM/IEEE Design Automation Conference, July 2004. [ paper ]
[48] P. Gupta, F.-L. Heng, R. Gordon, K. Lai, and J. Lee, “Taming Focus Variation in VLSI Design,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, February 2004. [ paper ]
[49] P. Gupta and A. B. Kahng, “Manufacturing-Aware Physical Design,” Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2003. (embedded tutorial). [ paper ]
[50] Y. Chen, P. Gupta, and A. B. Kahng, “Performance-Impact Limited Area Fill Synthesis,” in Proc. ACM/IEEE Design Automation Conference, June 2003. [ paper ]
[51] Y. Chen, P. Gupta, and A. B. Kahng, “Performance-Impact Limited Dummy Fill Insertion,” in Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, pp. 857-862, February 2003. [ paper | presentation ]
[52] Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, “Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI,” in IEEE ASIC/SoC Conference, pp. 411-415, September 2002. [ paper ]

-- NanoMembers - 06 Jan 2011

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