Hardware-Software Interface in Presence of Variability

While a well-defined firm hardware-software in- terface enabled advances in software and hardware design methods, it is increasingly harder to sustain as the newer semiconductor technologies exhibit growing manufacturing variabil- ity across different instances of a chip, aging-related wear-out, and variability due to the operating environment. We are developing techniques to establish a bidirectional dataflow between the system/application layer and the physical/circuit implementation layer to en- able software to opportunistically take advantage of underdesigned hardware systems. The resulting Underdesigned and Opportunistic (UnO) computing machines monitor hardware power/performance and use instance-specific adaptation in software to relax variation-induced guard-bands in hardware design.

Circuit Performance Monitoring

Students: Liangzhen Lai

Circuit performance monitors are essential for systems with hardware and software adaptation to reduce the design margin. This project aims at developing accurate and inexpensive performance monitoring methodologies. Design-dependent ring oscillator (DDRO) is a replica monitoring methodology, which designs multiple smart canary structures that can reliably predict achievable chip frequency but with margins for local variations. Early silicon results indicate that DDROs can reduce delay monitoring error by 35% compared to conventional ring oscillators. To further improve the prediction (albeit at a higher overhead), we propose SlackProbein situ slack monitors which can match local variations as well at overheads much smaller than monitoring all sequential elements. SlackProbe reduces the number of monitors required by over 15X with 5% additional delay margin in several commercial processor benchmarks.

Hardware Variability-Aware Duty Cycling for Embedded Sensors

Instance and temperature-dependent power variation has a direct impact on quality of sensing for battery powered, long running sensing applications. We measure and characterize active and leakage power for an ARM Cortex M3 processor, and show that across a temperature range of 2060◦C there is 10% variation in active power, and 14x variation in leakage power. We introduce variability aware duty cycling methods and a duty cycle abstraction for TinyOS that allows ap- plications to explicitly specify lifetime and minimum duty cycle requirements for individual tasks, and dynamically adjusts duty cycle rates so that overall quality of service is maximized in the presence of power variability. We show that variability-aware duty cycling yields a 322x improve- ment in total active time over schedules based on worst- case estimations of power, with an average improvement of 6.4x across a wide variety of deployment scenarios based on collected temperature traces. Conversely, datasheet power specifications fail to meet required lifetimes by 7 15%, with an average 37 days short of a required lifetime of one year. Finally, we show that a target localization application using variability-aware duty cycle yields a 50% improvement in quality of results over one based on worst- case estimations of power consumption.

A demo of variability-aware duty-cycling using our own testchip and testbed platform is shown in the following youtube video. Detailed description can be found in the technical report(link).

AppAdapt: Leveraging Application Adaptativity to Compensate Hardware Variation

Students: Aashish Pant

Objective: In this project, we seek to build on the flexible hardware-software interface paradigm by proposing the notion of hardware instance guided software adaptation for performance constrained applications. where the actual hardware state guides application adaptation on a die specific basis. We show that, by adapting the application to the post manufacturing hardware characteristics (hardware signatures) across different die, it is possible to compensate for application quality losses that might otherwise be significant in presence of process variations. This in turn results in improved manufacturing yield, relaxed requirement for hardware over-design and better application quality.

This work is motivated by the fact that a plethora of modern applications are reconfigurable and adaptive, i.e. they are capable of operating in various configurations by adapting to certain input or environmental conditions in turn producing similar or different quality of service. Moreover, process variation is increasing and hence, the conventional methods of incorporating variation-resistant design techniques, post manufacturing hardware tuning or hardware over-design have become too expensive to use for practical reasons. We observe that it is easier and cheaper to implement adaptation at the software layer as compared to designing a robust and dependable hardware in the presence of manufacturing variations. Moreover, adaptation is much better informed of the die-specific variation scenario at the application software layer.

Please see the videos below for a comparison of hardware adaptive vs non-adaptive encoder. Use the player provided with a frame resolution of 352x288 (CIF).

  • vidview.exe: VidView Player to play the raw .yuv video files (CIF 352x288 frame format)

  • orig.yuv: Original Un-Encoded Mobile Video Sequence

  • output_29_m15.yuv: Encoded Video on 20% over-designed hardware which is slower by 15%

  • output_59_m10.yuv: Encoded Video on 20% over-designed hardware which is slower by 10%

  • output_85_m5.enc: Encoded Video on 20% over-designed hardware which is slower by 5%

  • output_87_0.yuv: Encoded Video on 20% over-designed hardware which is slower by 0%

Variation Aware Binning of Multi-core Processors

Students: Aashish Pant

Objective: Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. In this project, our major focus is to leverage information obtained from a process variation model to evaluate the binning metrics more efficiently and accurately.

Publications List:

[1] L. Lai and P. Gupta, “Hardware Reliability Margining for the Dark Silicon Era,” in Proc. Asia and South Pacific Design Automation Conference, January 2016. [ paper | presentation ]
[2] L. Lai, V. Chandra, and P. Gupta, “Evaluating and Exploiting Impacts of Dynamic Power Management Schemes on System Reliability,” in International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), October 2015. [ paper | presentation ]
[3] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “BTI-Gater: An Aging-Resilient Clock Gating Methodology,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, pp. 180-189, June 2014. [ paper ]
[4] L. Lai and P. Gupta, “Accurate and inexpensive performance monitoring for variability-aware systems,” in Proc. Asia and South Pacific Design Automation Conference, pp. 467-473, Jan 2014. [ paper ]
[5] L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1168-1179, Aug 2014. [ paper ]
[6] L. Wanner, S. Elmalaki, L. Lai, P. Gupta, and M. Srivastava, “VarEMU: An Emulation Testbed for Variability-Aware Software,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, October 2013. [ paper ]
[7] M. Namaki-Shoushtari, A. Rahimi, N. Dutt, P. Gupta, and R. K. Gupta, “ARGO: Aging-aware GPGPU register file allocation,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, October 2013. [ paper ]
[8] N. Dutt, P. Gupta, A. Nicolau, L. Bathen, and M. Gottscho, “Variability-Aware Memory Management for Nanoscale Computing,” in Proc. Asia and South Pacific Design Automation Conference, 2013. [ paper ]
[9] J. Henkel, L. Bauer, N. Dutt, P. Gupta, S. Nassif, M. Shafique, M. Tahoori, and N. Wehn, “Reliable on-chip systems in the nano-era: lessons learnt and future trends,” in Proc. ACM/IEEE Design Automation Conference, pp. 99:1-99:10, 2013.
[10] T.-B. Chan, P. Gupta, A. B. Kahng, and L. Lai, “Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors,” IEEE Transactions on Very Large Scale Integration Systems, 2013. [ paper ]
[11] L. Bathen, M. Gottscho, N. Dutt, P. Gupta, and A. Nicolau, “ViPZonE: OS-Level Memory Variability-Aware Physical Address Zoning for Energy Savings,” in ACM International Conference on Hardware/Software Codesign and System Synthesis, October 2012. [ paper ]
[12] T. B. Chan, P. Gupta, A. Kahng, and L. Lai, “DDRO: A Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators,” in IEEE International Symposium on Quality Electronic Design, March 2012. [ paper | presentation ]
[13] L. Bathen, N. Dutt, A. Nicolau, and P. Gupta, “Vamv: Variability-aware memory virtualization,” in IEEE/ACM Design, Automation and Test in Europe, March 2012. Best interactive presentation. [ paper ]
[14] P. Gupta, “Measuring and monitoring variability,” in IEEE International On-Line Test Symposium, 2012. Invited Talk.
[15] M. Gottscho, A. A. Kagalwalla, and P. Gupta, “Power Variability in Contemporary DRAMs,” IEEE Embedded Systems Letters, vol. 4, pp. 37-40, 2012. [ paper ]
[16] L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “Hardware Variability-Aware Duty Cycling for Embedded Sensors,” IEEE Transactions on Very Large Scale Integration Systems, 2012. [ paper ]
[17] P. Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. N. T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester, “Underdesigned and opportunistic computing in presence of hardware variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. Keynote Paper. [ paper ]
[18] T.-B. Chan, J. Sartori, P. Gupta, and R. Kumar, “On the Efficacy of NBTI Mitigation Techniques,” in Design, Automation, and Test in Europe (DATE), March 2011. [ paper | presentation ]
[19] L. Wanner, R. Balani, S. Zahedi, C. Apte, P. Gupta, and M. Srivastava, “Variability Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems,” in Design, Automation, and Test in Europe (DATE), March 2011. [ paper | presentation ]
[20] P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading Accuracy for Power with an Underdesigned Multiplier Architecture,” in Proc. IEEE/ACM International Conference on VLSI Design, January 2011. [ paper | presentation ]
[21] P. Gupta and R. Gupta, “Underdesigned and opportunistic computing,” in Proc. Asian Test Symposium, 2011. [ paper | presentation ]
[22] P. Gupta, “Underdesigned and opportunistic computing machines,” in Nanosystem Design and Variability Workshop, EPFL, 2011. (invited talk).
[23] P. Gupta, “Designing for uncertainty: Addressing process variations and aging issues in vlsi designs,” in IEEE International Symposium on VLSI Design, Automation and Test, 2011. (tutorial). [ presentation ]
[24] P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading accuracy for power in a multiplier architecture,” Journal of Low Power Electronics, 2011. [ paper ]
[25] A. Pant, P. Gupta, and M. van der Schaar, “Appadapt: Opportunistic application adaptation in presence of hardware variation,” IEEE Transactions on Very Large Scale Integration Systems, 2011. [ paper ]
[26] L. Wanner, C. Apte, R. Balani, P. Gupta, and M. Srivastava, “A Case for Opportunistic Embedded Sensing In Presence of Hardware Power Varibility,” in HotPower'10, October 2010. [ paper | presentation ]
[27] A. Pant, P. Gupta, and M. v. d. Schaar, “Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability,” in ACM Great Lakes Symposium on Very Large Scale Integration, May 2010. [ paper ]
[28] J. Sartori, A. Pant, R. Kumar, and P. Gupta, “Variation Aware Speed Binning of Multi-core Processors,” in IEEE International Symposium on Quality Electronic Design, March 2010. [ paper ]


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